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Merge branch 'icc-misc' into icc-next

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* icc-misc
  interconnect: qcom: Constify struct qcom_icc_qosbox
  interconnect: fix typo "commited" in comments
  interconnect: Add kernel-doc for devm_of_icc_get(), icc_enable() and icc_disable()
  interconnect: exynos: Remove the PM QoS request on unbind
  interconnect: qcom: implement get_bw with rpmh_read
  interconnect: qcom: Skip get_bw on QoS programming providers
  interconnect: qcom: fix endian annotations of BCM aux data
  interconnect: mediatek: fix Makefile typo for mt8196

Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov 2026-10-02 00:43:48 +03:00
commit 3fd56a2833
11 changed files with 246 additions and 117 deletions
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32
drivers/interconnect/core.c
View File

@ -423,6 +423,17 @@ static void devm_icc_release(struct device *dev, void *res)
icc_put(*(struct icc_path **)res);
}
/**
* devm_of_icc_get() - get a path handle from a DT node based on name
* @dev: device pointer for the consumer device
* @name: interconnect path name
*
* This function is the resource managed version of of_icc_get(). The path
* is released with icc_put() automatically when @dev is unbound.
*
* Return: icc_path pointer on success or ERR_PTR() on error. NULL is returned
* when the API is disabled or the "interconnects" DT property is missing.
*/
struct icc_path *devm_of_icc_get(struct device *dev, const char *name)
{
struct icc_path **ptr, *path;
@ -786,12 +797,33 @@ static int __icc_enable(struct icc_path *path, bool enable)
path->reqs[0].peak_bw);
}
/**
* icc_enable() - enable a path
* @path: interconnect path
*
* Mark all requests on the path as enabled and reapply the bandwidth that
* was last set with icc_set_bw().
* Passing a NULL @path is a no-op and returns 0.
*
* Return: 0 on success, or an appropriate error code otherwise.
*/
int icc_enable(struct icc_path *path)
{
return __icc_enable(path, true);
}
EXPORT_SYMBOL_GPL(icc_enable);
/**
* icc_disable() - disable a path
* @path: interconnect path
*
* Mark all requests on the path as disabled, so that they no longer count
* towards the aggregated bandwidth, and reapply the constraints. The
* requested bandwidth is kept and restored by icc_enable().
* Passing a NULL @path is a no-op and returns 0.
*
* Return: 0 on success, or an appropriate error code otherwise.
*/
int icc_disable(struct icc_path *path)
{
return __icc_enable(path, false);

2
drivers/interconnect/mediatek/Makefile
View File

@ -3,4 +3,4 @@
obj-$(CONFIG_INTERCONNECT_MTK_DVFSRC_EMI) += icc-emi.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8183) += mt8183.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8195) += mt8195.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8195) += mt8196.o
obj-$(CONFIG_INTERCONNECT_MTK_MT8196) += mt8196.o

42
drivers/interconnect/qcom/bcm-voter.c
View File

@ -88,20 +88,20 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
for (bucket = 0; bucket < QCOM_ICC_NUM_BUCKETS; bucket++) {
for (i = 0; i < bcm->num_nodes; i++) {
node = bcm->nodes[i];
temp = qcom_bw_div(node->sum_avg[bucket] * bcm->aux_data.width,
temp = qcom_bw_div(node->sum_avg[bucket] * le16_to_cpu(bcm->aux_data.width),
node->buswidth * node->channels);
agg_avg[bucket] = max(agg_avg[bucket], temp);
temp = qcom_bw_div(node->max_peak[bucket] * bcm->aux_data.width,
temp = qcom_bw_div(node->max_peak[bucket] * le16_to_cpu(bcm->aux_data.width),
node->buswidth);
agg_peak[bucket] = max(agg_peak[bucket], temp);
}
temp = agg_avg[bucket] * bcm->vote_scale;
bcm->vote_x[bucket] = qcom_bw_div(temp, bcm->aux_data.unit);
bcm->vote_x[bucket] = qcom_bw_div(temp, le32_to_cpu(bcm->aux_data.unit));
temp = agg_peak[bucket] * bcm->vote_scale;
bcm->vote_y[bucket] = qcom_bw_div(temp, bcm->aux_data.unit);
bcm->vote_y[bucket] = qcom_bw_div(temp, le32_to_cpu(bcm->aux_data.unit));
}
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
@ -250,6 +250,40 @@ void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm)
}
EXPORT_SYMBOL_GPL(qcom_icc_bcm_voter_add);
/**
* qcom_icc_bcm_get_bw - get current bcm vote
* @voter: voter used to query bcm
* @bcm: bcm to get current vote from
*/
void qcom_icc_bcm_get_bw(struct bcm_voter *voter,
struct qcom_icc_bcm *bcm)
{
struct tcs_cmd cmd = { .addr = bcm->addr };
int ret, i;
u64 x, y;
mutex_lock(&voter->lock);
ret = rpmh_read(voter->dev, &cmd);
if (ret) {
pr_err("Error sending AMC RPMH requests (%d)\n", ret);
goto out;
}
x = FIELD_GET(BCM_TCS_CMD_VOTE_X_MASK, cmd.data);
y = FIELD_GET(BCM_TCS_CMD_VOTE_Y_MASK, cmd.data);
/* For boot-up, fill the AMC vote in all buckets */
for (i = 0; i < QCOM_ICC_NUM_BUCKETS; i++) {
bcm->vote_x[i] = x;
bcm->vote_y[i] = y;
}
out:
mutex_unlock(&voter->lock);
}
EXPORT_SYMBOL_GPL(qcom_icc_bcm_get_bw);
/**
* qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms
* @voter: voter that needs flushing

1
drivers/interconnect/qcom/bcm-voter.h
View File

@ -13,6 +13,7 @@
#include "icc-rpmh.h"
struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name);
void qcom_icc_bcm_get_bw(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);
void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm);
int qcom_icc_bcm_voter_commit(struct bcm_voter *voter);

18
drivers/interconnect/qcom/eliza.c
View File

@ -451,7 +451,7 @@ static struct qcom_icc_node qns_gem_noc_cnoc = {
.link_nodes = { &qnm_gemnoc_cnoc },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0x155000 },
.prio = 1,
@ -468,7 +468,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0x157000 },
.prio = 6,
@ -494,7 +494,7 @@ static struct qcom_icc_node chm_apps = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_gpu_qos = {
static const struct qcom_icc_qosbox qnm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x31000, 0xb1000 },
.prio = 0,
@ -511,7 +511,7 @@ static struct qcom_icc_node qnm_gpu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
.num_ports = 1,
.port_offsets = { 0x159000 },
.prio = 0,
@ -538,7 +538,7 @@ static struct qcom_icc_node qnm_mdsp = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0xb3000 },
.prio = 0,
@ -555,7 +555,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x35000, 0xb5000 },
.prio = 0,
@ -572,7 +572,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
.num_ports = 2,
.port_offsets = { 0x37000, 0xb7000 },
.prio = 0,
@ -590,7 +590,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_pcie_qos = {
static const struct qcom_icc_qosbox qnm_pcie_qos = {
.num_ports = 1,
.port_offsets = { 0x15b000 },
.prio = 2,
@ -688,7 +688,7 @@ static struct qcom_icc_node qnm_lpiaon_noc = {
.link_nodes = { &qns_lpass_ag_noc_gemnoc },
};
static struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x25000 },
.prio = 4,

4
drivers/interconnect/qcom/icc-rpm.c
View File

@ -462,7 +462,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
if (ret)
return ret;
/* Cache the rate after we've successfully commited it to RPM */
/* Cache the rate after we've successfully committed it to RPM */
qp->bus_clk_rate[QCOM_SMD_RPM_ACTIVE_STATE] = active_rate;
}
@ -472,7 +472,7 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
if (ret)
return ret;
/* Cache the rate after we've successfully commited it to RPM */
/* Cache the rate after we've successfully committed it to RPM */
qp->bus_clk_rate[QCOM_SMD_RPM_SLEEP_STATE] = sleep_rate;
}

71
drivers/interconnect/qcom/icc-rpmh.c
View File

@ -136,6 +136,61 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
}
EXPORT_SYMBOL_GPL(qcom_icc_set);
static int qcom_icc_get_bw(struct icc_node *node, u32 *avg, u32 *peak)
{
struct qcom_icc_node *qn = node->data;
u32 avg_max = 0;
u32 peak_max = 0;
u64 x, y;
int i;
if (!qn->num_bcms) {
*avg = INT_MAX;
*peak = INT_MAX;
return 0;
}
for (i = 0; i < qn->num_bcms; ++i) {
struct qcom_icc_bcm *bcm = qn->bcms[i];
/* Use AMC vote for boot-up */
x = bcm->vote_x[QCOM_ICC_BUCKET_AMC];
y = bcm->vote_y[QCOM_ICC_BUCKET_AMC];
/* Consider enable mask and convert to INT_MAX */
if (bcm->enable_mask) {
if (x & bcm->enable_mask)
avg_max = INT_MAX;
if (y & bcm->enable_mask)
peak_max = INT_MAX;
} else {
if (x) {
x *= le32_to_cpu(bcm->aux_data.unit);
do_div(x, bcm->vote_scale);
x *= qn->buswidth * qn->channels;
do_div(x, le16_to_cpu(bcm->aux_data.width));
avg_max = max(avg_max, x);
}
if (y) {
y *= le32_to_cpu(bcm->aux_data.unit);
do_div(y, bcm->vote_scale);
y *= qn->buswidth;
do_div(y, le16_to_cpu(bcm->aux_data.width));
peak_max = max(peak_max, y);
}
}
}
*avg = avg_max;
*peak = peak_max;
return 0;
}
/**
* qcom_icc_bcm_init - populates bcm aux data and connect qnodes
* @bcm: bcm to be initialized
@ -173,10 +228,7 @@ int qcom_icc_bcm_init(struct qcom_icc_bcm *bcm, struct device *dev)
return -EINVAL;
}
bcm->aux_data.unit = le32_to_cpu(data->unit);
bcm->aux_data.width = le16_to_cpu(data->width);
bcm->aux_data.vcd = data->vcd;
bcm->aux_data.reserved = data->reserved;
bcm->aux_data = *data;
INIT_LIST_HEAD(&bcm->list);
INIT_LIST_HEAD(&bcm->ws_list);
@ -255,6 +307,13 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
provider = &qp->provider;
provider->dev = dev;
provider->set = qcom_icc_set;
/*
* Programming the QoS registers below requires the NoC to be clocked,
* which during probe is only guaranteed by the INT_MAX initial votes
* the interconnect core applies when get_bw() is absent.
*/
if (!desc->config)
provider->get_bw = qcom_icc_get_bw;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate;
provider->xlate_extended = qcom_icc_xlate_extended;
@ -272,8 +331,10 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev)
if (IS_ERR(qp->voter))
return PTR_ERR(qp->voter);
for (i = 0; i < qp->num_bcms; i++)
for (i = 0; i < qp->num_bcms; i++) {
qcom_icc_bcm_init(qp->bcms[i], dev);
qcom_icc_bcm_get_bw(qp->voter, qp->bcms[i]);
}
for (i = 0; i < num_nodes; i++) {
qn = qnodes[i];

66
drivers/interconnect/qcom/milos.c
View File

@ -137,7 +137,7 @@ static struct qcom_icc_node srvc_pcie_aggre_noc;
static struct qcom_icc_node qns_gemnoc_gc;
static struct qcom_icc_node qns_gemnoc_sf;
static struct qcom_icc_qosbox qhm_qup1_qos = {
static const struct qcom_icc_qosbox qhm_qup1_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -154,7 +154,7 @@ static struct qcom_icc_node qhm_qup1 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
static const struct qcom_icc_qosbox xm_ufs_mem_qos = {
.num_ports = 1,
.port_offsets = { 0xf200 },
.prio = 2,
@ -171,7 +171,7 @@ static struct qcom_icc_node xm_ufs_mem = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
.num_ports = 1,
.port_offsets = { 0x10000 },
.prio = 2,
@ -188,7 +188,7 @@ static struct qcom_icc_node xm_usb3_0 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
.num_ports = 1,
.port_offsets = { 0x14000 },
.prio = 2,
@ -205,7 +205,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qspi_qos = {
static const struct qcom_icc_qosbox qhm_qspi_qos = {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio = 2,
@ -222,7 +222,7 @@ static struct qcom_icc_node qhm_qspi = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup0_qos = {
static const struct qcom_icc_qosbox qhm_qup0_qos = {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio = 2,
@ -239,7 +239,7 @@ static struct qcom_icc_node qhm_qup0 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
static const struct qcom_icc_qosbox qxm_crypto_qos = {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio = 2,
@ -256,7 +256,7 @@ static struct qcom_icc_node qxm_crypto = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
static const struct qcom_icc_qosbox qxm_ipa_qos = {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio = 2,
@ -273,7 +273,7 @@ static struct qcom_icc_node qxm_ipa = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio = 2,
@ -290,7 +290,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio = 2,
@ -307,7 +307,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc1_qos = {
static const struct qcom_icc_qosbox xm_sdc1_qos = {
.num_ports = 1,
.port_offsets = { 0x1a000 },
.prio = 2,
@ -324,7 +324,7 @@ static struct qcom_icc_node xm_sdc1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
static const struct qcom_icc_qosbox xm_sdc2_qos = {
.num_ports = 1,
.port_offsets = { 0x19000 },
.prio = 2,
@ -404,7 +404,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie = {
.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xf1000 },
.prio = 1,
@ -421,7 +421,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xf3000 },
.prio = 6,
@ -447,7 +447,7 @@ static struct qcom_icc_node chm_apps = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_gpu_qos = {
static const struct qcom_icc_qosbox qnm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x31000, 0x71000 },
.prio = 0,
@ -464,7 +464,7 @@ static struct qcom_icc_node qnm_gpu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
.num_ports = 1,
.port_offsets = { 0xf5000 },
.prio = 0,
@ -491,7 +491,7 @@ static struct qcom_icc_node qnm_mdsp = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x73000 },
.prio = 0,
@ -508,7 +508,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x35000, 0x75000 },
.prio = 0,
@ -525,7 +525,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
.num_ports = 2,
.port_offsets = { 0x37000, 0x77000 },
.prio = 0,
@ -543,7 +543,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_pcie_qos = {
static const struct qcom_icc_qosbox qnm_pcie_qos = {
.num_ports = 1,
.port_offsets = { 0xf7000 },
.prio = 2,
@ -560,7 +560,7 @@ static struct qcom_icc_node qnm_pcie = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
.num_ports = 1,
.port_offsets = { 0xf9000 },
.prio = 0,
@ -577,7 +577,7 @@ static struct qcom_icc_node qnm_snoc_gc = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0xfb000 },
.prio = 0,
@ -620,7 +620,7 @@ static struct qcom_icc_node llcc_mc = {
.link_nodes = { &ebi },
};
static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0xa8000, 0xa9000 },
.prio = 0,
@ -637,7 +637,7 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
.num_ports = 1,
.port_offsets = { 0x2a000 },
.prio = 5,
@ -654,7 +654,7 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x2b000, 0x2c000 },
.prio = 0,
@ -671,7 +671,7 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_mdp_qos = {
static const struct qcom_icc_qosbox qnm_mdp_qos = {
.num_ports = 1,
.port_offsets = { 0xad000 },
.prio = 0,
@ -688,7 +688,7 @@ static struct qcom_icc_node qnm_mdp = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_video_qos = {
static const struct qcom_icc_qosbox qnm_video_qos = {
.num_ports = 1,
.port_offsets = { 0x30000 },
.prio = 0,
@ -737,7 +737,7 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.link_nodes = { &srvc_pcie_aggre_noc },
};
static struct qcom_icc_qosbox xm_pcie3_0_qos = {
static const struct qcom_icc_qosbox xm_pcie3_0_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 2,
@ -754,7 +754,7 @@ static struct qcom_icc_node xm_pcie3_0 = {
.link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_qosbox xm_pcie3_1_qos = {
static const struct qcom_icc_qosbox xm_pcie3_1_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -787,7 +787,7 @@ static struct qcom_icc_node qnm_aggre2_noc = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_apss_noc_qos = {
static const struct qcom_icc_qosbox qnm_apss_noc_qos = {
.num_ports = 1,
.port_offsets = { 0x1c000 },
.prio = 2,
@ -804,7 +804,7 @@ static struct qcom_icc_node qnm_apss_noc = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_cnoc_data_qos = {
static const struct qcom_icc_qosbox qnm_cnoc_data_qos = {
.num_ports = 1,
.port_offsets = { 0x1d000 },
.prio = 2,
@ -821,7 +821,7 @@ static struct qcom_icc_node qnm_cnoc_data = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qxm_pimem_qos = {
static const struct qcom_icc_qosbox qxm_pimem_qos = {
.num_ports = 1,
.port_offsets = { 0x1e000 },
.prio = 2,
@ -838,7 +838,7 @@ static struct qcom_icc_node qxm_pimem = {
.link_nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_qosbox xm_gic_qos = {
static const struct qcom_icc_qosbox xm_gic_qos = {
.num_ports = 1,
.port_offsets = { 0x1f000 },
.prio = 2,

56
drivers/interconnect/qcom/sm6350.c
View File

@ -149,7 +149,7 @@ static struct qcom_icc_node qhm_a1noc_cfg = {
.link_nodes = { &srvc_aggre1_noc },
};
static struct qcom_icc_qosbox qhm_qup_0_qos = {
static const struct qcom_icc_qosbox qhm_qup_0_qos = {
.num_ports = 1,
.port_offsets = { 0xa000 },
.prio = 2,
@ -165,7 +165,7 @@ static struct qcom_icc_node qhm_qup_0 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_emmc_qos = {
static const struct qcom_icc_qosbox xm_emmc_qos = {
.num_ports = 1,
.port_offsets = { 0x7000 },
.prio = 2,
@ -181,7 +181,7 @@ static struct qcom_icc_node xm_emmc = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
static const struct qcom_icc_qosbox xm_ufs_mem_qos = {
.num_ports = 1,
.port_offsets = { 0x8000 },
.prio = 4,
@ -205,7 +205,7 @@ static struct qcom_icc_node qhm_a2noc_cfg = {
.link_nodes = { &srvc_aggre2_noc },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 2,
@ -221,7 +221,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup_1_qos = {
static const struct qcom_icc_qosbox qhm_qup_1_qos = {
.num_ports = 1,
.port_offsets = { 0x9000 },
.prio = 2,
@ -236,7 +236,7 @@ static struct qcom_icc_node qhm_qup_1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
static const struct qcom_icc_qosbox qxm_crypto_qos = {
.num_ports = 1,
.port_offsets = { 0x6000 },
.prio = 2,
@ -252,7 +252,7 @@ static struct qcom_icc_node qxm_crypto = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
static const struct qcom_icc_qosbox qxm_ipa_qos = {
.num_ports = 1,
.port_offsets = { 0x7000 },
.prio = 2,
@ -268,7 +268,7 @@ static struct qcom_icc_node qxm_ipa = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -284,7 +284,7 @@ static struct qcom_icc_node xm_qdss_etr = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
static const struct qcom_icc_qosbox xm_sdc2_qos = {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio = 2,
@ -300,7 +300,7 @@ static struct qcom_icc_node xm_sdc2 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 2,
@ -356,7 +356,7 @@ static struct qcom_icc_node qup1_core_master = {
.link_nodes = { &qup1_core_slave },
};
static struct qcom_icc_qosbox qnm_npu_qos = {
static const struct qcom_icc_qosbox qnm_npu_qos = {
.num_ports = 2,
.port_offsets = { 0xf000, 0x11000 },
.prio = 0,
@ -372,7 +372,7 @@ static struct qcom_icc_node qnm_npu = {
.link_nodes = { &qns_cdsp_gemnoc },
};
static struct qcom_icc_qosbox qxm_npu_dsp_qos = {
static const struct qcom_icc_qosbox qxm_npu_dsp_qos = {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio = 0,
@ -495,7 +495,7 @@ static struct qcom_icc_node qhm_cnoc_dc_noc = {
&qhs_gemnoc },
};
static struct qcom_icc_qosbox acm_apps_qos = {
static const struct qcom_icc_qosbox acm_apps_qos = {
.num_ports = 2,
.port_offsets = { 0x2f100, 0x2f000 },
.prio = 0,
@ -512,7 +512,7 @@ static struct qcom_icc_node acm_apps = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox acm_sys_tcu_qos = {
static const struct qcom_icc_qosbox acm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0x35000 },
.prio = 6,
@ -539,7 +539,7 @@ static struct qcom_icc_node qhm_gemnoc_cfg = {
&qhs_mdsp_ms_mpu_cfg },
};
static struct qcom_icc_qosbox qnm_cmpnoc_qos = {
static const struct qcom_icc_qosbox qnm_cmpnoc_qos = {
.num_ports = 1,
.port_offsets = { 0x2e000 },
.prio = 0,
@ -556,7 +556,7 @@ static struct qcom_icc_node qnm_cmpnoc = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 1,
.port_offsets = { 0x30000 },
.prio = 0,
@ -573,7 +573,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x34000 },
.prio = 0,
@ -590,7 +590,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
&qns_gem_noc_snoc },
};
static struct qcom_icc_qosbox qnm_snoc_gc_qos = {
static const struct qcom_icc_qosbox qnm_snoc_gc_qos = {
.num_ports = 1,
.port_offsets = { 0x32000 },
.prio = 0,
@ -606,7 +606,7 @@ static struct qcom_icc_node qnm_snoc_gc = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x31000 },
.prio = 0,
@ -622,7 +622,7 @@ static struct qcom_icc_node qnm_snoc_sf = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox qxm_gpu_qos = {
static const struct qcom_icc_qosbox qxm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x33080 },
.prio = 0,
@ -655,7 +655,7 @@ static struct qcom_icc_node qhm_mnoc_cfg = {
.link_nodes = { &srvc_mnoc },
};
static struct qcom_icc_qosbox qnm_video0_qos = {
static const struct qcom_icc_qosbox qnm_video0_qos = {
.num_ports = 1,
.port_offsets = { 0xf000 },
.prio = 2,
@ -671,7 +671,7 @@ static struct qcom_icc_node qnm_video0 = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_cvp_qos = {
static const struct qcom_icc_qosbox qnm_video_cvp_qos = {
.num_ports = 1,
.port_offsets = { 0xe000 },
.prio = 5,
@ -687,7 +687,7 @@ static struct qcom_icc_node qnm_video_cvp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qxm_camnoc_hf_qos = {
static const struct qcom_icc_qosbox qxm_camnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0xa000, 0xb000 },
.prio = 3,
@ -703,7 +703,7 @@ static struct qcom_icc_node qxm_camnoc_hf = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qxm_camnoc_icp_qos = {
static const struct qcom_icc_qosbox qxm_camnoc_icp_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 5,
@ -719,7 +719,7 @@ static struct qcom_icc_node qxm_camnoc_icp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qxm_camnoc_sf_qos = {
static const struct qcom_icc_qosbox qxm_camnoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0x9000 },
.prio = 3,
@ -735,7 +735,7 @@ static struct qcom_icc_node qxm_camnoc_sf = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qxm_mdp0_qos = {
static const struct qcom_icc_qosbox qxm_mdp0_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 3,
@ -822,7 +822,7 @@ static struct qcom_icc_node qnm_gemnoc = {
&xs_qdss_stm },
};
static struct qcom_icc_qosbox qxm_pimem_qos = {
static const struct qcom_icc_qosbox qxm_pimem_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 2,
@ -839,7 +839,7 @@ static struct qcom_icc_node qxm_pimem = {
&qxs_imem },
};
static struct qcom_icc_qosbox xm_gic_qos = {
static const struct qcom_icc_qosbox xm_gic_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 3,

70
drivers/interconnect/qcom/sm8650.c
View File

@ -154,7 +154,7 @@ static const struct regmap_config icc_regmap_config = {
.fast_io = true,
};
static struct qcom_icc_qosbox qhm_qspi_qos = {
static const struct qcom_icc_qosbox qhm_qspi_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -171,7 +171,7 @@ static struct qcom_icc_node qhm_qspi = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup1_qos = {
static const struct qcom_icc_qosbox qhm_qup1_qos = {
.num_ports = 1,
.port_offsets = { 0xd000 },
.prio = 2,
@ -196,7 +196,7 @@ static struct qcom_icc_node qxm_qup02 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc4_qos = {
static const struct qcom_icc_qosbox xm_sdc4_qos = {
.num_ports = 1,
.port_offsets = { 0xe000 },
.prio = 2,
@ -213,7 +213,7 @@ static struct qcom_icc_node xm_sdc4 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_ufs_mem_qos = {
static const struct qcom_icc_qosbox xm_ufs_mem_qos = {
.num_ports = 1,
.port_offsets = { 0xf000 },
.prio = 2,
@ -230,7 +230,7 @@ static struct qcom_icc_node xm_ufs_mem = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox xm_usb3_0_qos = {
static const struct qcom_icc_qosbox xm_usb3_0_qos = {
.num_ports = 1,
.port_offsets = { 0x10000 },
.prio = 2,
@ -247,7 +247,7 @@ static struct qcom_icc_node xm_usb3_0 = {
.link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_qosbox qhm_qdss_bam_qos = {
static const struct qcom_icc_qosbox qhm_qdss_bam_qos = {
.num_ports = 1,
.port_offsets = { 0x12000 },
.prio = 2,
@ -264,7 +264,7 @@ static struct qcom_icc_node qhm_qdss_bam = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qhm_qup2_qos = {
static const struct qcom_icc_qosbox qhm_qup2_qos = {
.num_ports = 1,
.port_offsets = { 0x13000 },
.prio = 2,
@ -281,7 +281,7 @@ static struct qcom_icc_node qhm_qup2 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_crypto_qos = {
static const struct qcom_icc_qosbox qxm_crypto_qos = {
.num_ports = 1,
.port_offsets = { 0x15000 },
.prio = 2,
@ -298,7 +298,7 @@ static struct qcom_icc_node qxm_crypto = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox qxm_ipa_qos = {
static const struct qcom_icc_qosbox qxm_ipa_qos = {
.num_ports = 1,
.port_offsets = { 0x16000 },
.prio = 2,
@ -323,7 +323,7 @@ static struct qcom_icc_node qxm_sp = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = {
.num_ports = 1,
.port_offsets = { 0x17000 },
.prio = 2,
@ -340,7 +340,7 @@ static struct qcom_icc_node xm_qdss_etr_0 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = {
.num_ports = 1,
.port_offsets = { 0x18000 },
.prio = 2,
@ -357,7 +357,7 @@ static struct qcom_icc_node xm_qdss_etr_1 = {
.link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_qosbox xm_sdc2_qos = {
static const struct qcom_icc_qosbox xm_sdc2_qos = {
.num_ports = 1,
.port_offsets = { 0x19000 },
.prio = 2,
@ -448,7 +448,7 @@ static struct qcom_icc_node qnm_gemnoc_pcie = {
.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
};
static struct qcom_icc_qosbox alm_gpu_tcu_qos = {
static const struct qcom_icc_qosbox alm_gpu_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xbf000 },
.prio = 1,
@ -465,7 +465,7 @@ static struct qcom_icc_node alm_gpu_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_sys_tcu_qos = {
static const struct qcom_icc_qosbox alm_sys_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xc1000 },
.prio = 6,
@ -482,7 +482,7 @@ static struct qcom_icc_node alm_sys_tcu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = {
static const struct qcom_icc_qosbox alm_ubwc_p_tcu_qos = {
.num_ports = 1,
.port_offsets = { 0xc5000 },
.prio = 1,
@ -508,7 +508,7 @@ static struct qcom_icc_node chm_apps = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_gpu_qos = {
static const struct qcom_icc_qosbox qnm_gpu_qos = {
.num_ports = 2,
.port_offsets = { 0x31000, 0x71000 },
.prio = 0,
@ -525,7 +525,7 @@ static struct qcom_icc_node qnm_gpu = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = {
.num_ports = 1,
.port_offsets = { 0xb5000 },
.prio = 0,
@ -552,7 +552,7 @@ static struct qcom_icc_node qnm_mdsp = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x73000 },
.prio = 0,
@ -569,7 +569,7 @@ static struct qcom_icc_node qnm_mnoc_hf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x35000, 0x75000 },
.prio = 0,
@ -586,7 +586,7 @@ static struct qcom_icc_node qnm_mnoc_sf = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = {
.num_ports = 2,
.port_offsets = { 0x37000, 0x77000 },
.prio = 0,
@ -604,7 +604,7 @@ static struct qcom_icc_node qnm_nsp_gemnoc = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_pcie_qos = {
static const struct qcom_icc_qosbox qnm_pcie_qos = {
.num_ports = 1,
.port_offsets = { 0xb7000 },
.prio = 2,
@ -621,7 +621,7 @@ static struct qcom_icc_node qnm_pcie = {
.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
};
static struct qcom_icc_qosbox qnm_snoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_snoc_sf_qos = {
.num_ports = 1,
.port_offsets = { 0xbb000 },
.prio = 0,
@ -639,7 +639,7 @@ static struct qcom_icc_node qnm_snoc_sf = {
&qns_pcie },
};
static struct qcom_icc_qosbox qnm_ubwc_p_qos = {
static const struct qcom_icc_qosbox qnm_ubwc_p_qos = {
.num_ports = 1,
.port_offsets = { 0xc3000 },
.prio = 1,
@ -656,7 +656,7 @@ static struct qcom_icc_node qnm_ubwc_p = {
.link_nodes = { &qns_llcc },
};
static struct qcom_icc_qosbox xm_gic_qos = {
static const struct qcom_icc_qosbox xm_gic_qos = {
.num_ports = 1,
.port_offsets = { 0xb9000 },
.prio = 4,
@ -705,7 +705,7 @@ static struct qcom_icc_node llcc_mc = {
.link_nodes = { &ebi },
};
static struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = {
.num_ports = 2,
.port_offsets = { 0x28000, 0x29000 },
.prio = 0,
@ -722,7 +722,7 @@ static struct qcom_icc_node qnm_camnoc_hf = {
.link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = {
.num_ports = 1,
.port_offsets = { 0x2a000 },
.prio = 4,
@ -739,7 +739,7 @@ static struct qcom_icc_node qnm_camnoc_icp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = {
.num_ports = 2,
.port_offsets = { 0x2b000, 0x2c000 },
.prio = 0,
@ -756,7 +756,7 @@ static struct qcom_icc_node qnm_camnoc_sf = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_mdp_qos = {
static const struct qcom_icc_qosbox qnm_mdp_qos = {
.num_ports = 2,
.port_offsets = { 0x2d000, 0x2e000 },
.prio = 0,
@ -781,7 +781,7 @@ static struct qcom_icc_node qnm_vapss_hcp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_qos = {
static const struct qcom_icc_qosbox qnm_video_qos = {
.num_ports = 2,
.port_offsets = { 0x30000, 0x31000 },
.prio = 0,
@ -798,7 +798,7 @@ static struct qcom_icc_node qnm_video = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = {
.num_ports = 1,
.port_offsets = { 0x32000 },
.prio = 4,
@ -815,7 +815,7 @@ static struct qcom_icc_node qnm_video_cv_cpu = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_cvp_qos = {
static const struct qcom_icc_qosbox qnm_video_cvp_qos = {
.num_ports = 2,
.port_offsets = { 0x33000, 0x34000 },
.prio = 0,
@ -832,7 +832,7 @@ static struct qcom_icc_node qnm_video_cvp = {
.link_nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = {
.num_ports = 1,
.port_offsets = { 0x35000 },
.prio = 4,
@ -873,7 +873,7 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg = {
.link_nodes = { &srvc_pcie_aggre_noc },
};
static struct qcom_icc_qosbox xm_pcie3_0_qos = {
static const struct qcom_icc_qosbox xm_pcie3_0_qos = {
.num_ports = 1,
.port_offsets = { 0xb000 },
.prio = 3,
@ -890,7 +890,7 @@ static struct qcom_icc_node xm_pcie3_0 = {
.link_nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_qosbox xm_pcie3_1_qos = {
static const struct qcom_icc_qosbox xm_pcie3_1_qos = {
.num_ports = 1,
.port_offsets = { 0xc000 },
.prio = 2,
@ -923,7 +923,7 @@ static struct qcom_icc_node qnm_aggre2_noc = {
.link_nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_qosbox qnm_apss_noc_qos = {
static const struct qcom_icc_qosbox qnm_apss_noc_qos = {
.num_ports = 1,
.port_offsets = { 0x1c000 },
.prio = 2,

1
drivers/interconnect/samsung/exynos.c
View File

@ -98,6 +98,7 @@ static void exynos_generic_icc_remove(struct platform_device *pdev)
struct exynos_icc_priv *priv = platform_get_drvdata(pdev);
icc_provider_deregister(&priv->provider);
dev_pm_qos_remove_request(&priv->qos_req);
icc_nodes_remove(&priv->provider);
}