mirror of
https://github.com/torvalds/linux.git
synced 2026-06-01 02:53:36 +02:00
More devicetree changes for omaps
Devicetree updates for few boards and more clean-up for make dtbs warnings: - Updates for am335x-myirtech oscillator and mtd - Firmware configuration for i2c voltage scaling and IO isolation for am3/4 that are wired for these features - A series of omap3 clock node clean-up for make dtbs warnings for unique_unit_address and node_name_chars_strict - Updates for dma-channel usage to add the generic dma-common properties -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAmJzWPgRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXOAww/8CCUn6y8amao2RuT+VuZmssg3eet4gHdD CGOdBPUEZCD2SX+sAhRPvuavucHokPHngJsdEMdpyITwFxl0OmBExR9UDa57tgqo KiAQz7b5FT+DaDsero8lu/pre92WR/QnWEh7KRwyWqm4XFotJgE6UrS6mH6oLOl7 J4snjUZvsdPOPANwqN9OlzGJ94F2FlV7Q1qNlbXxSmh4lvE9FH8mqiGBgJRWs/DF pPDqYe+iUi92E0W30/bzdy0+hsXp8cG8dlIqoUb9YSqNsubCe11Jrmu9Sx8b5IAU KKo5op9eYKKpIbw3X+9IndcaRspL8ioOpla/xqieyJ8RQsuQqIY9LFu2bubB/8Ly vA4Xiux4oG81T+vruRjWnnLfxR5gBthEhpAsboy3hkqlyU2BLwhlbCdasu4wFH1F FwISIgZ7mORTEVtM8kts6QljuFESrjxWuWQzHhOhmFpO7yBbTLGrudjz9vq6Olbu pupL3IkH75S0fF4ukWsmHw3Y71mYbLU39fkgWhXz7hqBKUkeryagsDE1glUiXxzA uKBT/WoTgdS4fS5ReWWs1vlu91eA+b6iTTGO7fdgTS0WNnGqtxEOL7MF5moIl0Vu xK+FRwtDu33Pkwpo3zbrwAcxTXNKg2HsZKiFnU3mEf3XoJPDu9uUTW7LLipn0xAU ZVOCL0gLVM8= =Vx4R -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ0GhsACgkQmmx57+YA GNlBxxAAnifnJBgUXC6TH4zIkiRGt2leStQ6EBo4pKKnQCMdmKr638QWDFbpFX4y qHYbKPozfmZS9rJQ7Ngf1tYyeSs2H6Ddj9UntJpM79qXDczLehzHFQKgaXTtEcZv zoj/TPSEoepqEgWlh1blWknReJvomVv02cWomLeueX4e+Pj5iFzLuWkokzJzpbpl s363RvcllIBenzvfCCgMTOilYC5IRXuc5jkIC0vx1HAAn4LlPaflsZarwKSdpTsu ZQIckcz3z6eR/AoDunPD+pR30AEKvz17AW9zpnftQoIxBQlIOCQx7MgbFqb4BDZz 4DsKGT1kZdSNxXq3ejyyYFFYoLVbIo/7mFOuX8kf2Lze1XbRCNW5RhVb1lBxpXvg PLQC4tjhxh3cNgs8CyHlT0B3KBSBSGGfpjoHlb6vkBnSunm21YRIZBCOI0jW7+mb NLbleV2GQ+yZ4c2wXBH4UDkhUMhb99JzAVbYRJ+iEhyAAoMKzHjRKM1EEMz5dfSS c4Nl83sx6HsvIGz71Nl3fxMr2qpmQOnc9wEFnBQC3zlEVg8aJRBYrS5ofGg3LJZR PPRTx1QTtUnwBf21HCnD9ksvpcLSrp6VVoPB5savWD5SwXsL01XaG9GE66UwVHVD 6iXUoKgf00AMTBj45vpdHamuGQil2COnZ+CrN6KJ1CI7oXW6QFk= =6jOE -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.19/dt-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt More devicetree changes for omaps Devicetree updates for few boards and more clean-up for make dtbs warnings: - Updates for am335x-myirtech oscillator and mtd - Firmware configuration for i2c voltage scaling and IO isolation for am3/4 that are wired for these features - A series of omap3 clock node clean-up for make dtbs warnings for unique_unit_address and node_name_chars_strict - Updates for dma-channel usage to add the generic dma-common properties * tag 'omap-for-v5.19/dt-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (26 commits) ARM: dts: dm81xx: use new 'dma-channels/requests' properties ARM: dts: am33xx: use new 'dma-channels/requests' properties ARM: dts: Group omap3 CM_CLKSEL1_EMU clocks ARM: dts: Group omap3 CM_CLKSEL_PER clocks ARM: dts: Group omap3 CM_ICLKEN_PER clocks ARM: dts: Group omap3 CM_FCLKEN_PER clocks ARM: dts: Group omap3 CM_FCLKEN_CAM clocks ARM: dts: Group omap3 CM_CLKSEL_DSS clocks ARM: dts: Group omap3 CM_FCLKEN_DSS clocks ARM: dts: Group omap3 CM_CLKOUT_CTRL clocks ARM: dts: Group omap3 CM_CLKSEL1_PLL clocks ARM: dts: Group omap3 CM_CLKSEL_WKUP clocks ARM: dts: Group omap3 CM_ICLKEN_WKUP clocks ARM: dts: Group omap3 CM_FCLKEN_WKUP clocks ARM: dts: Group omap3 CM_CLKSEL_CORE clocks ARM: dts: Group omap3 CM_ICLKEN3_CORE clocks ARM: dts: Group omap3 CM_ICLKEN1_CORE clocks ARM: dts: Group omap3 crypto accelerator clocks ARM: dts: Group omap3 CM_FCLKEN1_CORE clocks ARM: dts: Group omap3 CONTROL_DEVCONF1 clocks ... Link: https://lore.kernel.org/r/pull-1651726643-535261@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
485b5afae6
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@ -405,3 +405,7 @@ &rtc {
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&pruss_tm {
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status = "okay";
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};
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&wkup_m3_ipc {
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firmware-name = "am335x-bone-scale-data.bin";
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};
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@ -782,3 +782,7 @@ &rtc {
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&pruss_tm {
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status = "okay";
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};
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&wkup_m3_ipc {
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firmware-name = "am335x-evm-scale-data.bin";
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};
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@ -719,3 +719,7 @@ &rtc {
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&pruss_tm {
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status = "okay";
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};
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&wkup_m3_ipc {
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firmware-name = "am335x-evm-scale-data.bin";
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};
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@ -27,6 +27,13 @@ memory@80000000 {
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reg = <0x80000000 0x10000000>;
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};
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clk32k: clk32k {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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vdd_mod: vdd_mod_reg {
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compatible = "regulator-fixed";
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regulator-name = "vdd-mod";
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@ -124,9 +131,6 @@ nand0: nand@0,0 {
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gpmc,wr-data-mux-bus-ns = <0>;
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ti,elm-id = <&elm>;
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ti,nand-ecc-opt = "bch8";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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@ -149,6 +153,8 @@ eeprom: eeprom@50 {
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};
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&rtc {
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clocks = <&clk32k>;
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clock-names = "ext-clk";
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system-power-controller;
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};
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@ -227,14 +227,20 @@ &mmc1 {
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};
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&nand0 {
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partition@0 {
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label = "MLO";
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reg = <0x00000 0x20000>;
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};
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nand_parts: partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@20000 {
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label = "boot";
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reg = <0x20000 0x80000>;
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partition@0 {
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label = "MLO";
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reg = <0x00000 0x20000>;
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};
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partition@80000 {
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label = "boot";
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reg = <0x80000 0x100000>;
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};
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};
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};
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@ -461,8 +461,11 @@ cppi41dma: dma-controller@2000 {
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interrupts = <17>;
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interrupt-names = "glue";
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#dma-cells = <2>;
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/* For backwards compatibility: */
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#dma-channels = <30>;
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dma-channels = <30>;
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#dma-requests = <256>;
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dma-requests = <256>;
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};
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};
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@ -62,12 +62,27 @@ hecc_ck: hecc_ck@32c {
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};
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};
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&cm_clocks {
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ipss_ick: ipss_ick@a10 {
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#clock-cells = <0>;
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compatible = "ti,am35xx-interface-clock";
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clocks = <&core_l3_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <4>;
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clock@a10 {
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compatible = "ti,clksel";
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reg = <0xa10>;
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#clock-cells = <2>;
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#address-cells = <0>;
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ipss_ick: clock-ipss-ick {
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#clock-cells = <0>;
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compatible = "ti,am35xx-interface-clock";
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clock-output-names = "ipss_ick";
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clocks = <&core_l3_ick>;
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ti,bit-shift = <4>;
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};
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uart4_ick_am35xx: clock-uart4-ick-am35xx {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clock-output-names = "uart4_ick_am35xx";
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clocks = <&core_l4_ick>;
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ti,bit-shift = <23>;
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};
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};
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rmii_ck: rmii_ck {
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@ -82,20 +97,19 @@ pclk_ck: pclk_ck {
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clock-frequency = <27000000>;
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};
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uart4_ick_am35xx: uart4_ick_am35xx@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <23>;
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};
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clock@a00 {
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compatible = "ti,clksel";
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reg = <0xa00>;
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#clock-cells = <2>;
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#address-cells = <0>;
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uart4_fck_am35xx: uart4_fck_am35xx@a00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_48m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <23>;
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uart4_fck_am35xx: clock-uart4-fck-am35xx {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clock-output-names = "uart4_fck_am35xx";
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clocks = <&core_48m_fck>;
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ti,bit-shift = <23>;
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};
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};
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};
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@ -1127,6 +1127,11 @@ &cpu {
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cpu0-supply = <&dcdc2>;
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};
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&wkup_m3_ipc {
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ti,set-io-isolation;
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firmware-name = "am43x-evm-scale-data.bin";
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};
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&pruss1_mdio {
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status = "disabled";
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};
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@ -893,6 +893,10 @@ vpfe0_ep: endpoint {
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};
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};
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&wkup_m3_ipc {
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firmware-name = "am43x-evm-scale-data.bin";
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};
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&pruss1_mdio {
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status = "disabled";
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};
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@ -1019,6 +1019,10 @@ &cpu {
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cpu0-supply = <&dcdc2>;
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};
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&wkup_m3_ipc {
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firmware-name = "am43x-evm-scale-data.bin";
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};
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&pruss1_mdio {
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status = "disabled";
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};
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@ -167,8 +167,11 @@ cppi41dma: dma-controller@47402000 {
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interrupts = <17>;
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interrupt-names = "glue";
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#dma-cells = <2>;
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/* For backwards compatibility: */
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#dma-channels = <30>;
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dma-channels = <30>;
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#dma-requests = <256>;
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dma-requests = <256>;
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};
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};
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@ -655,8 +655,11 @@ cppi41dma: dma-controller@47402000 {
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interrupts = <17>;
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interrupt-names = "glue";
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#dma-cells = <2>;
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/* For backwards compatibility: */
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#dma-channels = <30>;
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dma-channels = <30>;
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#dma-requests = <256>;
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dma-requests = <256>;
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};
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};
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@ -46,37 +46,61 @@ gfx_cg2_ck: gfx_cg2_ck@b00 {
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ti,bit-shift = <2>;
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};
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d2d_26m_fck: d2d_26m_fck@a00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&sys_ck>;
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reg = <0x0a00>;
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ti,bit-shift = <3>;
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clock@a00 {
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compatible = "ti,clksel";
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reg = <0xa00>;
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#clock-cells = <2>;
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#address-cells = <0>;
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d2d_26m_fck: clock-d2d-26m-fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clock-output-names = "d2d_26m_fck";
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clocks = <&sys_ck>;
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ti,bit-shift = <3>;
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};
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fshostusb_fck: clock-fshostusb-fck {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clock-output-names = "fshostusb_fck";
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clocks = <&core_48m_fck>;
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ti,bit-shift = <5>;
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};
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ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clock-output-names = "ssi_ssr_gate_fck_3430es1";
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clocks = <&corex2_fck>;
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ti,bit-shift = <0>;
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};
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};
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fshostusb_fck: fshostusb_fck@a00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_48m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <5>;
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};
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clock@a40 {
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compatible = "ti,clksel";
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reg = <0xa40>;
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#clock-cells = <2>;
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#address-cells = <0>;
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ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <0>;
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reg = <0x0a00>;
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};
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ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clock-output-names = "ssi_ssr_div_fck_3430es1";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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usb_l4_div_ick: clock-usb-l4-div-ick {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clock-output-names = "usb_l4_div_ick";
|
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clocks = <&l4_ick>;
|
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ti,bit-shift = <4>;
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ti,max-div = <1>;
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ti,index-starts-at-one;
|
||||
};
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||||
};
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ssi_ssr_fck: ssi_ssr_fck_3430es1 {
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|
|
@ -93,20 +117,43 @@ ssi_sst_fck: ssi_sst_fck_3430es1 {
|
|||
clock-div = <2>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
clock@a10 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
fac_ick: fac_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <8>;
|
||||
hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clock-output-names = "hsotgusb_ick_3430es1";
|
||||
clocks = <&core_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
fac_ick: clock-fac-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "fac_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
};
|
||||
|
||||
ssi_ick: clock-ssi-ick-3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clock-output-names = "ssi_ick_3430es1";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usb_l4_gate_ick: clock-usb-l4-gate-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-interface-clock";
|
||||
clock-output-names = "usb_l4_gate_ick";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
|
|
@ -117,45 +164,26 @@ ssi_l4_ick: ssi_l4_ick {
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ssi_ick: ssi_ick_3430es1@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
usb_l4_gate_ick: usb_l4_gate_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0a10>;
|
||||
};
|
||||
|
||||
usb_l4_div_ick: usb_l4_div_ick@a40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&l4_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
ti,max-div = <1>;
|
||||
reg = <0x0a40>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
usb_l4_ick: usb_l4_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-clock";
|
||||
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
|
||||
};
|
||||
|
||||
dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0e00>;
|
||||
ti,set-rate-parent;
|
||||
clock@e00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xe00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "dss1_alwon_fck_3430es1";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
};
|
||||
|
||||
dss_ick: dss_ick_3430es1@e10 {
|
||||
|
|
|
|||
|
|
@ -13,45 +13,76 @@ security_l4_ick2: security_l4_ick2 {
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes1_ick: aes1_ick@a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0a14>;
|
||||
clock@a14 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa14>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
aes1_ick: clock-aes1-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "aes1_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
rng_ick: clock-rng-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "rng_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
sha11_ick: clock-sha11-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "sha11_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
des1_ick: clock-des1-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "des1_ick";
|
||||
clocks = <&security_l4_ick2>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
pka_ick: clock-pka-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "pka_ick";
|
||||
clocks = <&security_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
rng_ick: rng_ick@a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
/* CM_FCLKEN_CAM */
|
||||
clock@f00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xf00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
sha11_ick: sha11_ick@a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
cam_mclk: clock-cam-mclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "cam_mclk";
|
||||
clocks = <&dpll4_m5x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
des1_ick: des1_ick@a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
cam_mclk: cam_mclk@f00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll4_m5x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0f00>;
|
||||
ti,set-rate-parent;
|
||||
csi2_96m_fck: clock-csi2-96m-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clock-output-names = "csi2_96m_fck";
|
||||
clocks = <&core_96m_fck>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
cam_ick: cam_ick@f10 {
|
||||
|
|
@ -62,14 +93,6 @@ cam_ick: cam_ick@f10 {
|
|||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
csi2_96m_fck: csi2_96m_fck@f00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0f00>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
security_l3_ick: security_l3_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
|
|
@ -78,44 +101,51 @@ security_l3_ick: security_l3_ick {
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pka_ick: pka_ick@a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l3_ick>;
|
||||
reg = <0x0a14>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
clock@a10 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
icr_ick: icr_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <29>;
|
||||
};
|
||||
icr_ick: clock-icr-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "icr_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <29>;
|
||||
};
|
||||
|
||||
des2_ick: des2_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <26>;
|
||||
};
|
||||
des2_ick: clock-des2-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "des2_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <26>;
|
||||
};
|
||||
|
||||
mspro_ick: mspro_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
mspro_ick: clock-mspro-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mspro_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
mailboxes_ick: mailboxes_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <7>;
|
||||
mailboxes_ick: clock-mailboxes-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mailboxes_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
|
||||
sad2d_ick: clock-sad2d-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "sad2d_ick";
|
||||
clocks = <&l3_ick>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
|
|
@ -126,20 +156,27 @@ ssi_l4_ick: ssi_l4_ick {
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sr1_fck: sr1_fck@c00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <6>;
|
||||
};
|
||||
clock@c00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
sr2_fck: sr2_fck@c00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0c00>;
|
||||
ti,bit-shift = <7>;
|
||||
sr1_fck: clock-sr1-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "sr1_fck";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <6>;
|
||||
};
|
||||
|
||||
sr2_fck: clock-sr2-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "sr2_fck";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
sr_l4_ick: sr_l4_ick {
|
||||
|
|
@ -187,37 +224,45 @@ iva2_ck: iva2_ck@0 {
|
|||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
modem_fck: modem_fck@a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <31>;
|
||||
clock@a00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
modem_fck: clock-modem-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "modem_fck";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <31>;
|
||||
};
|
||||
|
||||
mspro_fck: clock-mspro-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "mspro_fck";
|
||||
clocks = <&core_96m_fck>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
sad2d_ick: sad2d_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <3>;
|
||||
/* CM_ICLKEN3_CORE */
|
||||
clock@a18 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa18>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
mad2d_ick: clock-mad2d-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mad2d_ick";
|
||||
clocks = <&l3_ick>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
mad2d_ick: mad2d_ick@a18 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&l3_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
mspro_fck: mspro_fck@a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
|
|
|
|||
|
|
@ -133,37 +133,66 @@ usbtll_fck: usbtll_fck@a08 {
|
|||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
usbtll_ick: usbtll_ick@a18 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a18>;
|
||||
ti,bit-shift = <2>;
|
||||
/* CM_ICLKEN3_CORE */
|
||||
clock@a18 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa18>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
usbtll_ick: clock-usbtll-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "usbtll_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
mmchs3_ick: mmchs3_ick@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <30>;
|
||||
clock@a10 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
mmchs3_ick: clock-mmchs3-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "mmchs3_ick";
|
||||
clocks = <&core_l4_ick>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
};
|
||||
|
||||
mmchs3_fck: mmchs3_fck@a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <30>;
|
||||
clock@a00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
mmchs3_fck: clock-mmchs3-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "mmchs3_fck";
|
||||
clocks = <&core_96m_fck>;
|
||||
ti,bit-shift = <30>;
|
||||
};
|
||||
};
|
||||
|
||||
dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0e00>;
|
||||
ti,set-rate-parent;
|
||||
clock@e00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xe00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clock-output-names = "dss1_alwon_fck_3430es2";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
};
|
||||
|
||||
dss_ick: dss_ick_3430es2@e10 {
|
||||
|
|
|
|||
|
|
@ -58,12 +58,19 @@ dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
|
|||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
uart4_fck: uart4_fck@1000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&per_48m_fck>;
|
||||
clock@1000 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0x1000>;
|
||||
ti,bit-shift = <18>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
uart4_fck: clock-uart4-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clock-output-names = "uart4_fck";
|
||||
clocks = <&per_48m_fck>;
|
||||
ti,bit-shift = <18>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -5,21 +5,35 @@
|
|||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*/
|
||||
&cm_clocks {
|
||||
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0a00>;
|
||||
clock@a00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clock-output-names = "ssi_ssr_gate_fck_3430es2";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
clock@a40 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa40>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clock-output-names = "ssi_ssr_div_fck_3430es2";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
};
|
||||
|
||||
ssi_ssr_fck: ssi_ssr_fck_3430es2 {
|
||||
|
|
@ -36,12 +50,27 @@ ssi_sst_fck: ssi_sst_fck_3430es2 {
|
|||
clock-div = <2>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-hsotgusb-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
clock@a10 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xa10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-hsotgusb-interface-clock";
|
||||
clock-output-names = "hsotgusb_ick_3430es2";
|
||||
clocks = <&core_l3_ick>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
ssi_ick: clock-ssi-ick-3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clock-output-names = "ssi_ick_3430es2";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ssi_l4_ick: ssi_l4_ick {
|
||||
|
|
@ -52,20 +81,19 @@ ssi_l4_ick: ssi_l4_ick {
|
|||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ssi_ick: ssi_ick_3430es2@a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
clock@c00 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc00>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
usim_gate_fck: usim_gate_fck@c00 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&omap_96m_fck>;
|
||||
ti,bit-shift = <9>;
|
||||
reg = <0x0c00>;
|
||||
usim_gate_fck: clock-usim-gate-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clock-output-names = "usim_gate_fck";
|
||||
clocks = <&omap_96m_fck>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
};
|
||||
|
||||
sys_d2_ck: sys_d2_ck {
|
||||
|
|
@ -140,13 +168,20 @@ dpll5_m2_d20_ck: dpll5_m2_d20_ck {
|
|||
clock-div = <20>;
|
||||
};
|
||||
|
||||
usim_mux_fck: usim_mux_fck@c40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0c40>;
|
||||
ti,index-starts-at-one;
|
||||
clock@c40 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc40>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
usim_mux_fck: clock-usim-mux-fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clock-output-names = "usim_mux_fck";
|
||||
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
};
|
||||
|
||||
usim_fck: usim_fck {
|
||||
|
|
@ -155,12 +190,19 @@ usim_fck: usim_fck {
|
|||
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
|
||||
};
|
||||
|
||||
usim_ick: usim_ick@c10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&wkup_l4_ick>;
|
||||
reg = <0x0c10>;
|
||||
ti,bit-shift = <9>;
|
||||
clock@c10 {
|
||||
compatible = "ti,clksel";
|
||||
reg = <0xc10>;
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <0>;
|
||||
|
||||
usim_ick: clock-usim-ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clock-output-names = "usim_ick";
|
||||
clocks = <&wkup_l4_ick>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user