From 97fab2004d11577dfe17aaaacdbf02093194dbb9 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 27 Apr 2022 11:19:13 +0300 Subject: [PATCH 01/26] ARM: dts: am335x-myirtech: Add an external clock oscillator for CPU RTC The CPU RTC has an external crystal, so to keep time, let's define it for devicetree. Signed-off-by: Alexander Shiyan Message-Id: <20220427081914.6773-1-eagle.alexander923@gmail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-myirtech-myc.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index 245c35f41cdf..d94e096983c7 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -27,6 +27,13 @@ memory@80000000 { reg = <0x80000000 0x10000000>; }; + clk32k: clk32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + + #clock-cells = <0>; + }; + vdd_mod: vdd_mod_reg { compatible = "regulator-fixed"; regulator-name = "vdd-mod"; @@ -149,6 +156,8 @@ eeprom: eeprom@50 { }; &rtc { + clocks = <&clk32k>; + clock-names = "ext-clk"; system-power-controller; }; From 165c79da163f9909aba8fad68b897148399a1ba5 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 27 Apr 2022 11:19:14 +0300 Subject: [PATCH 02/26] ARM: dts: am335x-myirtech: Update NAND default partition table layout This patch replaces the legacy partition table layout with a modern style. As an additional change, we are reserving space for three backup MLO entries and increasing space for the main bootloader. Signed-off-by: Alexander Shiyan Message-Id: <20220427081914.6773-2-eagle.alexander923@gmail.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-myirtech-myc.dtsi | 3 --- arch/arm/boot/dts/am335x-myirtech-myd.dts | 20 +++++++++++++------- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi index d94e096983c7..6eea18b29355 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myc.dtsi +++ b/arch/arm/boot/dts/am335x-myirtech-myc.dtsi @@ -131,9 +131,6 @@ nand0: nand@0,0 { gpmc,wr-data-mux-bus-ns = <0>; ti,elm-id = <&elm>; ti,nand-ecc-opt = "bch8"; - - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts index 1479fd95dec2..9d81d4cc6890 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/am335x-myirtech-myd.dts @@ -227,14 +227,20 @@ &mmc1 { }; &nand0 { - partition@0 { - label = "MLO"; - reg = <0x00000 0x20000>; - }; + nand_parts: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@20000 { - label = "boot"; - reg = <0x20000 0x80000>; + partition@0 { + label = "MLO"; + reg = <0x00000 0x20000>; + }; + + partition@80000 { + label = "boot"; + reg = <0x80000 0x100000>; + }; }; }; From e348101bbaed4a0263ccc37e9b6c68f686465588 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Sun, 1 May 2022 19:15:07 -0700 Subject: [PATCH 03/26] ARM: dts: am437x-gp-evm: Enable wkup_m3 control of IO isolation With this flag wkup_m3 is able to control IO isolation during suspend on the board. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Drew Fustini Message-Id: <20220502021508.1342869-2-dfustini@baylibre.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 4416ddb559e4..91b67b428a06 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1127,6 +1127,10 @@ &cpu { cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + ti,set-io-isolation; +}; + &pruss1_mdio { status = "disabled"; }; From d480ecc9752d2b5a46f6f590e5853337bf4754f6 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Sun, 1 May 2022 19:15:08 -0700 Subject: [PATCH 04/26] ARM: dts: am33xx: Add i2c voltage scaling firmware to wkup_m3_ipc Add appropriate firmware-name property for all am33xx platforms. Signed-off-by: Dave Gerlach [dfustini: change property from 'ti,scale-data-fw' to 'firmware-name'] Signed-off-by: Drew Fustini Message-Id: <20220502021508.1342869-3-dfustini@baylibre.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-bone-common.dtsi | 4 ++++ arch/arm/boot/dts/am335x-evm.dts | 4 ++++ arch/arm/boot/dts/am335x-evmsk.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 56ae5095a5b8..02e04a12a270 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -405,3 +405,7 @@ &rtc { &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-bone-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 659e99eabe66..b9745a2f0e4d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -782,3 +782,7 @@ &rtc { &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index a2db65538e51..9c458e5a95b7 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -719,3 +719,7 @@ &rtc { &pruss_tm { status = "okay"; }; + +&wkup_m3_ipc { + firmware-name = "am335x-evm-scale-data.bin"; +}; From 392ab2e2af060962ee1e37a5e2aa358f878a8f77 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Sun, 1 May 2022 19:15:09 -0700 Subject: [PATCH 05/26] ARM: dts: am43xx: Add i2c voltage scaling firmware to wkup_m3_ipc Add appropriate firmware-name property for all am43xx platforms. Signed-off-by: Dave Gerlach Signed-off-by: Keerthy [dfustini: change property from 'ti,scale-data-fw' to 'firmware-name'] Signed-off-by: Drew Fustini Message-Id: <20220502021508.1342869-4-dfustini@baylibre.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 1 + arch/arm/boot/dts/am437x-sk-evm.dts | 4 ++++ arch/arm/boot/dts/am43x-epos-evm.dts | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 91b67b428a06..46d5361fe876 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -1129,6 +1129,7 @@ &cpu { &wkup_m3_ipc { ti,set-io-isolation; + firmware-name = "am43x-evm-scale-data.bin"; }; &pruss1_mdio { diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 20a34d2d85df..e5a825a525f9 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -893,6 +893,10 @@ vpfe0_ep: endpoint { }; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 4f9a7251a107..50c33418703a 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -1019,6 +1019,10 @@ &cpu { cpu0-supply = <&dcdc2>; }; +&wkup_m3_ipc { + firmware-name = "am43x-evm-scale-data.bin"; +}; + &pruss1_mdio { status = "disabled"; }; From 24a3db53ec9cac80b71e14b3c489b98e7537cdae Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 06/26] ARM: dts: Group omap3 CONTROL_DEVCONF0 clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 36 ++++++++++++++++---------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 0656c32439d2..b40832103dd6 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -92,12 +92,28 @@ mcbsp5_fck: mcbsp5_fck { clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; }; - mcbsp1_mux_fck: mcbsp1_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x04>; + /* CONTROL_DEVCONF0 */ + clock@4 { + compatible = "ti,clksel"; + reg = <0x4>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp1_mux_fck: clock-mcbsp1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp1_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; + + mcbsp2_mux_fck: clock-mcbsp2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp2_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + }; }; mcbsp1_fck: mcbsp1_fck { @@ -106,14 +122,6 @@ mcbsp1_fck: mcbsp1_fck { clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; }; - mcbsp2_mux_fck: mcbsp2_mux_fck@4 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <6>; - reg = <0x04>; - }; - mcbsp2_fck: mcbsp2_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 1e7079d32e6ae9ec8caae2a4e7d9696b97307b7a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 07/26] ARM: dts: Group omap3 CONTROL_DEVCONF1 clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 48 +++++++++++++++----------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index b40832103dd6..7518fd57f9dc 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -78,12 +78,35 @@ wkup_l4_ick: wkup_l4_ick { }; &scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <4>; + /* CONTROL_DEVCONF1 */ + clock@68 { + compatible = "ti,clksel"; reg = <0x68>; + #clock-cells = <2>; + #address-cells = <0>; + + mcbsp5_mux_fck: clock-mcbsp5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp5_mux_fck"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + }; + + mcbsp3_mux_fck: clock-mcbsp3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp3_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + }; + + mcbsp4_mux_fck: clock-mcbsp4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "mcbsp4_mux_fck"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + }; }; mcbsp5_fck: mcbsp5_fck { @@ -128,27 +151,12 @@ mcbsp2_fck: mcbsp2_fck { clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; }; - mcbsp3_mux_fck: mcbsp3_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x68>; - }; - mcbsp3_fck: mcbsp3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; }; - mcbsp4_mux_fck: mcbsp4_mux_fck@68 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&per_96m_fck>, <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x68>; - }; - mcbsp4_fck: mcbsp4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 3408a95f213e71fae8a9530872ecd2a77be78926 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 08/26] ARM: dts: Group omap3 CM_FCLKEN1_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am35xx-clocks.dtsi | 19 +- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 47 ++-- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 35 ++- ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 19 +- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 19 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 260 +++++++++--------- 6 files changed, 221 insertions(+), 178 deletions(-) diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index 220d0a52797e..93a12ddf4b7e 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -90,12 +90,19 @@ uart4_ick_am35xx: uart4_ick_am35xx@a10 { ti,bit-shift = <23>; }; - uart4_fck_am35xx: uart4_fck_am35xx@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck_am35xx: clock-uart4-fck-am35xx { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck_am35xx"; + clocks = <&core_48m_fck>; + ti,bit-shift = <23>; + }; }; }; diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 2ec3628d3315..6509ae0b036c 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -46,28 +46,35 @@ gfx_cg2_ck: gfx_cg2_ck@b00 { ti,bit-shift = <2>; }; - d2d_26m_fck: d2d_26m_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <3>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; - fshostusb_fck: fshostusb_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <5>; - }; + d2d_26m_fck: clock-d2d-26m-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "d2d_26m_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; + fshostusb_fck: clock-fshostusb-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "fshostusb_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <5>; + }; + + ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; }; ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 21079cdf2663..37556b464f79 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -187,14 +187,28 @@ iva2_ck: iva2_ck@0 { ti,bit-shift = <0>; }; - modem_fck: modem_fck@a00 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&sys_ck>; - reg = <0x0a00>; - ti,bit-shift = <31>; - }; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + modem_fck: clock-modem-fck { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "modem_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <31>; + }; + + mspro_fck: clock-mspro-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mspro_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <23>; + }; + }; sad2d_ick: sad2d_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; @@ -211,13 +225,6 @@ mad2d_ick: mad2d_ick@a18 { ti,bit-shift = <3>; }; - mspro_fck: mspro_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <23>; - }; }; &cm_clockdomains { diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 9974d5226971..d698b05b742d 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -149,12 +149,19 @@ mmchs3_ick: mmchs3_ick@a10 { ti,bit-shift = <30>; }; - mmchs3_fck: mmchs3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <30>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_fck: clock-mmchs3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <30>; + }; }; dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 945537aee3ca..247236326da5 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -5,12 +5,19 @@ * Copyright (C) 2013 Texas Instruments, Inc. */ &cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <0>; - reg = <0x0a00>; + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "ssi_ssr_gate_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + }; }; ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 7518fd57f9dc..20b855959f1a 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -603,12 +603,140 @@ rm_ick: rm_ick@c40 { ti,index-starts-at-one; }; - gpt10_gate_fck: gpt10_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <11>; - reg = <0x0a00>; + /* CM_FCLKEN1_CORE */ + clock@a00 { + compatible = "ti,clksel"; + reg = <0xa00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt10_gate_fck: clock-gpt10-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt10_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <11>; + }; + + gpt11_gate_fck: clock-gpt11-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt11_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <12>; + }; + + mmchs2_fck: clock-mmchs2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <25>; + }; + + mmchs1_fck: clock-mmchs1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mmchs1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <24>; + }; + + i2c3_fck: clock-i2c3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c3_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <17>; + }; + + i2c2_fck: clock-i2c2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c2_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <16>; + }; + + i2c1_fck: clock-i2c1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "i2c1_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <15>; + }; + + mcbsp5_gate_fck: clock-mcbsp5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp5_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <10>; + }; + + mcbsp1_gate_fck: clock-mcbsp1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp1_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <9>; + }; + + mcspi4_fck: clock-mcspi4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi4_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <21>; + }; + + mcspi3_fck: clock-mcspi3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi3_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <20>; + }; + + mcspi2_fck: clock-mcspi2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <19>; + }; + + mcspi1_fck: clock-mcspi1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "mcspi1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <18>; + }; + + uart2_fck: clock-uart2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart2_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <14>; + }; + + uart1_fck: clock-uart1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart1_fck"; + clocks = <&core_48m_fck>; + ti,bit-shift = <13>; + }; + + hdq_fck: clock-hdq-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "hdq_fck"; + clocks = <&core_12m_fck>; + ti,bit-shift = <22>; + }; }; gpt10_mux_fck: gpt10_mux_fck@a40 { @@ -625,14 +753,6 @@ gpt10_fck: gpt10_fck { clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_gate_fck: gpt11_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <12>; - reg = <0x0a00>; - }; - gpt11_mux_fck: gpt11_mux_fck@a40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -655,62 +775,6 @@ core_96m_fck: core_96m_fck { clock-div = <1>; }; - mmchs2_fck: mmchs2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <25>; - }; - - mmchs1_fck: mmchs1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <24>; - }; - - i2c3_fck: i2c3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <17>; - }; - - i2c2_fck: i2c2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <16>; - }; - - i2c1_fck: i2c1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0a00>; - ti,bit-shift = <15>; - }; - - mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <10>; - reg = <0x0a00>; - }; - - mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <9>; - reg = <0x0a00>; - }; - core_48m_fck: core_48m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -719,54 +783,6 @@ core_48m_fck: core_48m_fck { clock-div = <1>; }; - mcspi4_fck: mcspi4_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <21>; - }; - - mcspi3_fck: mcspi3_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <20>; - }; - - mcspi2_fck: mcspi2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <19>; - }; - - mcspi1_fck: mcspi1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <18>; - }; - - uart2_fck: uart2_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <14>; - }; - - uart1_fck: uart1_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_48m_fck>; - reg = <0x0a00>; - ti,bit-shift = <13>; - }; - core_12m_fck: core_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -775,14 +791,6 @@ core_12m_fck: core_12m_fck { clock-div = <1>; }; - hdq_fck: hdq_fck@a00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_12m_fck>; - reg = <0x0a00>; - ti,bit-shift = <22>; - }; - core_l3_ick: core_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; From aeb4dcf2c2bf0f8b0ae354ea37cf55fd0e17de65 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 09/26] ARM: dts: Group omap3 crypto accelerator clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 77 ++++++++++--------- 1 file changed, 42 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 37556b464f79..518eb7d60bcf 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -13,36 +13,51 @@ security_l4_ick2: security_l4_ick2 { clock-div = <1>; }; - aes1_ick: aes1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - ti,bit-shift = <3>; - reg = <0x0a14>; - }; + clock@a14 { + compatible = "ti,clksel"; + reg = <0xa14>; + #clock-cells = <2>; + #address-cells = <0>; - rng_ick: rng_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <2>; - }; + aes1_ick: clock-aes1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <3>; + }; - sha11_ick: sha11_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <1>; - }; + rng_ick: clock-rng-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "rng_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <2>; + }; - des1_ick: des1_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l4_ick2>; - reg = <0x0a14>; - ti,bit-shift = <0>; + sha11_ick: clock-sha11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha11_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <1>; + }; + + des1_ick: clock-des1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des1_ick"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <0>; + }; + + pka_ick: clock-pka-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "pka_ick"; + clocks = <&security_l3_ick>; + ti,bit-shift = <4>; + }; }; cam_mclk: cam_mclk@f00 { @@ -78,14 +93,6 @@ security_l3_ick: security_l3_ick { clock-div = <1>; }; - pka_ick: pka_ick@a14 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&security_l3_ick>; - reg = <0x0a14>; - ti,bit-shift = <4>; - }; - icr_ick: icr_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; From eea4b03528410bc893b031860885e25e4f856bf3 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 10/26] ARM: dts: Group omap3 CM_ICLKEN1_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am35xx-clocks.dtsi | 35 +- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 65 ++-- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 77 +++-- ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 19 +- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 35 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 324 +++++++++--------- 6 files changed, 299 insertions(+), 256 deletions(-) diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index 93a12ddf4b7e..0ee7afaa0e8e 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -62,12 +62,27 @@ hecc_ck: hecc_ck@32c { }; }; &cm_clocks { - ipss_ick: ipss_ick@a10 { - #clock-cells = <0>; - compatible = "ti,am35xx-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + ipss_ick: clock-ipss-ick { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clock-output-names = "ipss_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + uart4_ick_am35xx: clock-uart4-ick-am35xx { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick_am35xx"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; }; rmii_ck: rmii_ck { @@ -82,14 +97,6 @@ pclk_ck: pclk_ck { clock-frequency = <27000000>; }; - uart4_ick_am35xx: uart4_ick_am35xx@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; - clock@a00 { compatible = "ti,clksel"; reg = <0xa00>; diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 6509ae0b036c..984e1385723e 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -100,20 +100,43 @@ ssi_sst_fck: ssi_sst_fck_3430es1 { clock-div = <2>; }; - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; - }; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; - fac_ick: fac_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <8>; + hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es1"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + fac_ick: clock-fac-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "fac_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <8>; + }; + + ssi_ick: clock-ssi-ick-3430es1 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clock-output-names = "ssi_ick_3430es1"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; + + usb_l4_gate_ick: clock-usb-l4-gate-ick { + #clock-cells = <0>; + compatible = "ti,composite-interface-clock"; + clock-output-names = "usb_l4_gate_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <5>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -124,22 +147,6 @@ ssi_l4_ick: ssi_l4_ick { clock-div = <1>; }; - ssi_ick: ssi_ick_3430es1@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - - usb_l4_gate_ick: usb_l4_gate_ick@a10 { - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <5>; - reg = <0x0a10>; - }; - usb_l4_div_ick: usb_l4_div_ick@a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index 518eb7d60bcf..eca6b2513f41 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -93,36 +93,51 @@ security_l3_ick: security_l3_ick { clock-div = <1>; }; - icr_ick: icr_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <29>; - }; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; - des2_ick: des2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <26>; - }; + icr_ick: clock-icr-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "icr_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <29>; + }; - mspro_ick: mspro_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <23>; - }; + des2_ick: clock-des2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "des2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <26>; + }; - mailboxes_ick: mailboxes_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <7>; + mspro_ick: clock-mspro-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mspro_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <23>; + }; + + mailboxes_ick: clock-mailboxes-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mailboxes_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <7>; + }; + + sad2d_ick: clock-sad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -216,14 +231,6 @@ mspro_fck: clock-mspro-fck { ti,bit-shift = <23>; }; }; - sad2d_ick: sad2d_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <3>; - }; - mad2d_ick: mad2d_ick@a18 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index d698b05b742d..f8583bb66796 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -141,12 +141,19 @@ usbtll_ick: usbtll_ick@a18 { ti,bit-shift = <2>; }; - mmchs3_ick: mmchs3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <30>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + mmchs3_ick: clock-mmchs3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <30>; + }; }; clock@a00 { diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 247236326da5..c74566ff1f22 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -43,12 +43,27 @@ ssi_sst_fck: ssi_sst_fck_3430es2 { clock-div = <2>; }; - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-hsotgusb-interface-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <4>; + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + hsotgusb_ick_3430es2: clock-hsotgusb-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-hsotgusb-interface-clock"; + clock-output-names = "hsotgusb_ick_3430es2"; + clocks = <&core_l3_ick>; + ti,bit-shift = <4>; + }; + + ssi_ick: clock-ssi-ick-3430es2 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clock-output-names = "ssi_ick_3430es2"; + clocks = <&ssi_l4_ick>; + ti,bit-shift = <0>; + }; }; ssi_l4_ick: ssi_l4_ick { @@ -59,14 +74,6 @@ ssi_l4_ick: ssi_l4_ick { clock-div = <1>; }; - ssi_ick: ssi_ick_3430es2@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-ssi-interface-clock"; - clocks = <&ssi_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <0>; - }; - usim_gate_fck: usim_gate_fck@c00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 20b855959f1a..60e603127a0c 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -799,12 +799,172 @@ core_l3_ick: core_l3_ick { clock-div = <1>; }; - sdrc_ick: sdrc_ick@a10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&core_l3_ick>; - reg = <0x0a10>; - ti,bit-shift = <1>; + /* CM_ICLKEN1_CORE */ + clock@a10 { + compatible = "ti,clksel"; + reg = <0xa10>; + #clock-cells = <2>; + #address-cells = <0>; + + sdrc_ick: clock-sdrc-ick { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sdrc_ick"; + clocks = <&core_l3_ick>; + ti,bit-shift = <1>; + }; + + mmchs2_ick: clock-mmchs2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <25>; + }; + + mmchs1_ick: clock-mmchs1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mmchs1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <24>; + }; + + hdq_ick: clock-hdq-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "hdq_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <22>; + }; + + mcspi4_ick: clock-mcspi4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi4_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <21>; + }; + + mcspi3_ick: clock-mcspi3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <20>; + }; + + mcspi2_ick: clock-mcspi2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <19>; + }; + + mcspi1_ick: clock-mcspi1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcspi1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <18>; + }; + + i2c3_ick: clock-i2c3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c3_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <17>; + }; + + i2c2_ick: clock-i2c2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <16>; + }; + + i2c1_ick: clock-i2c1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "i2c1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <15>; + }; + + uart2_ick: clock-uart2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <14>; + }; + + uart1_ick: clock-uart1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <13>; + }; + + gpt11_ick: clock-gpt11-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt11_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <12>; + }; + + gpt10_ick: clock-gpt10-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt10_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <11>; + }; + + mcbsp5_ick: clock-mcbsp5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp5_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <10>; + }; + + mcbsp1_ick: clock-mcbsp1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp1_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <9>; + }; + + omapctrl_ick: clock-omapctrl-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omapctrl_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <6>; + }; + + aes2_ick: clock-aes2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "aes2_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <28>; + }; + + sha12_ick: clock-sha12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "sha12_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <27>; + }; }; gpmc_fck: gpmc_fck { @@ -823,142 +983,6 @@ core_l4_ick: core_l4_ick { clock-div = <1>; }; - mmchs2_ick: mmchs2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <25>; - }; - - mmchs1_ick: mmchs1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <24>; - }; - - hdq_ick: hdq_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <22>; - }; - - mcspi4_ick: mcspi4_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <21>; - }; - - mcspi3_ick: mcspi3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <20>; - }; - - mcspi2_ick: mcspi2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <19>; - }; - - mcspi1_ick: mcspi1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <18>; - }; - - i2c3_ick: i2c3_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <17>; - }; - - i2c2_ick: i2c2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <16>; - }; - - i2c1_ick: i2c1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <15>; - }; - - uart2_ick: uart2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <14>; - }; - - uart1_ick: uart1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <13>; - }; - - gpt11_ick: gpt11_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <12>; - }; - - gpt10_ick: gpt10_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <11>; - }; - - mcbsp5_ick: mcbsp5_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <10>; - }; - - mcbsp1_ick: mcbsp1_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <9>; - }; - - omapctrl_ick: omapctrl_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <6>; - }; - dss_tv_fck: dss_tv_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; @@ -1010,14 +1034,6 @@ gpt1_fck: gpt1_fck { clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; }; - aes2_ick: aes2_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - ti,bit-shift = <28>; - reg = <0x0a10>; - }; - wkup_32k_fck: wkup_32k_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1034,14 +1050,6 @@ gpio1_dbck: gpio1_dbck@c00 { ti,bit-shift = <3>; }; - sha12_ick: sha12_ick@a10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a10>; - ti,bit-shift = <27>; - }; - wdt2_fck: wdt2_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; From 4e28ab96e311e4cf07f064f3bbe78e92ef013b15 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 11/26] ARM: dts: Group omap3 CM_ICLKEN3_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 21 +++++++++++++------ ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 20 ++++++++++++------ 2 files changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index eca6b2513f41..b6316be894ce 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -231,12 +231,21 @@ mspro_fck: clock-mspro-fck { ti,bit-shift = <23>; }; }; - mad2d_ick: mad2d_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&l3_ick>; - reg = <0x0a18>; - ti,bit-shift = <3>; + + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + mad2d_ick: clock-mad2d-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mad2d_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <3>; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index f8583bb66796..1c41530cc16a 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -133,12 +133,20 @@ usbtll_fck: usbtll_fck@a08 { ti,bit-shift = <2>; }; - usbtll_ick: usbtll_ick@a18 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&core_l4_ick>; - reg = <0x0a18>; - ti,bit-shift = <2>; + /* CM_ICLKEN3_CORE */ + clock@a18 { + compatible = "ti,clksel"; + reg = <0xa18>; + #clock-cells = <2>; + #address-cells = <0>; + + usbtll_ick: clock-usbtll-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usbtll_ick"; + clocks = <&core_l4_ick>; + ti,bit-shift = <2>; + }; }; clock@a10 { From b0985e02787759d99a8e921215b6dee0a2980c8c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 12/26] ARM: dts: Group omap3 CM_CLKSEL_CORE clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 41 ++++++----- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 21 ++++-- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 72 ++++++++++--------- 3 files changed, 78 insertions(+), 56 deletions(-) diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 984e1385723e..7dbab6eb2e6d 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -77,13 +77,30 @@ ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 { }; }; - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es1"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + usb_l4_div_ick: clock-usb-l4-div-ick { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "usb_l4_div_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <4>; + ti,max-div = <1>; + ti,index-starts-at-one; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es1 { @@ -147,16 +164,6 @@ ssi_l4_ick: ssi_l4_ick { clock-div = <1>; }; - usb_l4_div_ick: usb_l4_div_ick@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <4>; - ti,max-div = <1>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; - usb_l4_ick: usb_l4_ick { #clock-cells = <0>; compatible = "ti,composite-clock"; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index c74566ff1f22..c6ab51a36f39 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -20,13 +20,20 @@ ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 { }; }; - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clocks = <&corex2_fck>; - ti,bit-shift = <8>; - reg = <0x0a40>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; + + ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clock-output-names = "ssi_ssr_div_fck_3430es2"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; }; ssi_ssr_fck: ssi_ssr_fck_3430es2 { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 60e603127a0c..430dca208dc8 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -574,23 +574,47 @@ emu_mpu_alwon_ck: emu_mpu_alwon_ck { clock-div = <1>; }; - l3_ick: l3_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&core_ck>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; - }; + /* CM_CLKSEL_CORE */ + clock@a40 { + compatible = "ti,clksel"; + reg = <0xa40>; + #clock-cells = <2>; + #address-cells = <0>; - l4_ick: l4_ick@a40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,bit-shift = <2>; - ti,max-div = <3>; - reg = <0x0a40>; - ti,index-starts-at-one; + l3_ick: clock-l3-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l3_ick"; + clocks = <&core_ck>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + l4_ick: clock-l4-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "l4_ick"; + clocks = <&l3_ick>; + ti,bit-shift = <2>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt10_mux_fck: clock-gpt10-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt10_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt11_mux_fck: clock-gpt11-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt11_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; }; rm_ick: rm_ick@c40 { @@ -739,28 +763,12 @@ hdq_fck: clock-hdq-fck { }; }; - gpt10_mux_fck: gpt10_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0a40>; - }; - gpt10_fck: gpt10_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_mux_fck: gpt11_mux_fck@a40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x0a40>; - }; - gpt11_fck: gpt11_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 05891b43bee70e026bcf11028936cabd3cc1eb08 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 13/26] ARM: dts: Group omap3 CM_FCLKEN_WKUP clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 33 +++++++----- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 19 ++++--- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 52 +++++++++++-------- 3 files changed, 63 insertions(+), 41 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index b6316be894ce..edc28654d158 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -148,20 +148,27 @@ ssi_l4_ick: ssi_l4_ick { clock-div = <1>; }; - sr1_fck: sr1_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <6>; - }; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; - sr2_fck: sr2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&sys_ck>; - reg = <0x0c00>; - ti,bit-shift = <7>; + sr1_fck: clock-sr1-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr1_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + sr2_fck: clock-sr2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "sr2_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; }; sr_l4_ick: sr_l4_ick { diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index c6ab51a36f39..7c25739d5612 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -81,12 +81,19 @@ ssi_l4_ick: ssi_l4_ick { clock-div = <1>; }; - usim_gate_fck: usim_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&omap_96m_fck>; - ti,bit-shift = <9>; - reg = <0x0c00>; + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_gate_fck: clock-usim-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "usim_gate_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <9>; + }; }; sys_d2_ck: sys_d2_ck { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 430dca208dc8..2cb77eb15eae 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1021,12 +1021,36 @@ dummy_ck: dummy_ck { clock-frequency = <0>; }; - gpt1_gate_fck: gpt1_gate_fck@c00 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <0>; - reg = <0x0c00>; + /* CM_FCLKEN_WKUP */ + clock@c00 { + compatible = "ti,clksel"; + reg = <0xc00>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt1_gate_fck: clock-gpt1-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt1_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + }; + + gpio1_dbck: clock-gpio1-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio1_dbck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <3>; + }; + + wdt2_fck: clock-wdt2-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt2_fck"; + clocks = <&wkup_32k_fck>; + ti,bit-shift = <5>; + }; }; gpt1_mux_fck: gpt1_mux_fck@c40 { @@ -1050,22 +1074,6 @@ wkup_32k_fck: wkup_32k_fck { clock-div = <1>; }; - gpio1_dbck: gpio1_dbck@c00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <3>; - }; - - wdt2_fck: wdt2_fck@c00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&wkup_32k_fck>; - reg = <0x0c00>; - ti,bit-shift = <5>; - }; - wdt2_ick: wdt2_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; From 23347c90e2329b88fab5b8fad6bfe94471ca1514 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 14/26] ARM: dts: Group omap3 CM_ICLKEN_WKUP clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 19 ++-- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 90 ++++++++++--------- 2 files changed, 62 insertions(+), 47 deletions(-) diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 7c25739d5612..b177eebcbae6 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -183,12 +183,19 @@ usim_fck: usim_fck { clocks = <&usim_gate_fck>, <&usim_mux_fck>; }; - usim_ick: usim_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <9>; + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_ick: clock-usim-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "usim_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <9>; + }; }; }; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 2cb77eb15eae..5d8fff6d37fb 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1074,52 +1074,60 @@ wkup_32k_fck: wkup_32k_fck { clock-div = <1>; }; - wdt2_ick: wdt2_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <5>; - }; + /* CM_ICLKEN_WKUP */ + clock@c10 { + compatible = "ti,clksel"; + reg = <0xc10>; + #clock-cells = <2>; + #address-cells = <0>; - wdt1_ick: wdt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <4>; - }; + wdt2_ick: clock-wdt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt2_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <5>; + }; - gpio1_ick: gpio1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <3>; - }; + wdt1_ick: clock-wdt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <4>; + }; - omap_32ksync_ick: omap_32ksync_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <2>; - }; + gpio1_ick: clock-gpio1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <3>; + }; - gpt12_ick: gpt12_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <1>; - }; + omap_32ksync_ick: clock-omap-32ksync-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "omap_32ksync_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <2>; + }; - gpt1_ick: gpt1_ick@c10 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&wkup_l4_ick>; - reg = <0x0c10>; - ti,bit-shift = <0>; + gpt12_ick: clock-gpt12-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt12_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <1>; + }; + + gpt1_ick: clock-gpt1-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt1_ick"; + clocks = <&wkup_l4_ick>; + ti,bit-shift = <0>; + }; }; per_96m_fck: per_96m_fck { From 2f7c426df6f63447a65af770a07539051bc8c868 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 15/26] ARM: dts: Group omap3 CM_CLKSEL_WKUP clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../dts/omap36xx-omap3430es2plus-clocks.dtsi | 21 ++++++---- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 38 +++++++++++-------- 2 files changed, 37 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index b177eebcbae6..c94eb86d3da7 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -168,13 +168,20 @@ dpll5_m2_d20_ck: dpll5_m2_d20_ck { clock-div = <20>; }; - usim_mux_fck: usim_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; - ti,bit-shift = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + usim_mux_fck: clock-usim-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "usim_mux_fck"; + clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; + ti,bit-shift = <3>; + ti,index-starts-at-one; + }; }; usim_fck: usim_fck { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 5d8fff6d37fb..80e63f185427 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -617,14 +617,29 @@ gpt11_mux_fck: clock-gpt11-mux-fck { }; }; - rm_ick: rm_ick@c40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l4_ick>; - ti,bit-shift = <1>; - ti,max-div = <3>; - reg = <0x0c40>; - ti,index-starts-at-one; + /* CM_CLKSEL_WKUP */ + clock@c40 { + compatible = "ti,clksel"; + reg = <0xc40>; + #clock-cells = <2>; + #address-cells = <0>; + + rm_ick: clock-rm-ick { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "rm_ick"; + clocks = <&l4_ick>; + ti,bit-shift = <1>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + gpt1_mux_fck: clock-gpt1-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt1_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; }; /* CM_FCLKEN1_CORE */ @@ -1053,13 +1068,6 @@ wdt2_fck: clock-wdt2-fck { }; }; - gpt1_mux_fck: gpt1_mux_fck@c40 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - reg = <0x0c40>; - }; - gpt1_fck: gpt1_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 173e215b7f8632c62db2dc713e51a998038bb8ac Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 16/26] ARM: dts: Group omap3 CM_CLKSEL1_PLL clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 72 ++++++++++++++------------ 1 file changed, 40 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 80e63f185427..d101f0a40502 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -301,16 +301,6 @@ mcbsp_clks: mcbsp_clks { clock-frequency = <0x0>; }; - dpll3_m2_ck: dpll3_m2_ck@d40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <27>; - ti,max-div = <31>; - reg = <0x0d40>; - ti,index-starts-at-one; - }; - core_ck: core_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -361,12 +351,46 @@ cm_96m_fck: cm_96m_fck { clock-div = <1>; }; - omap_96m_fck: omap_96m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x0d40>; + /* CM_CLKSEL1_PLL */ + clock@d40 { + compatible = "ti,clksel"; + reg = <0xd40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m2_ck: clock-dpll3-m2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m2_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <27>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + omap_96m_fck: clock-omap-96m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_96m_fck"; + clocks = <&cm_96m_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + omap_54m_fck: clock-omap-54m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_54m_fck"; + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; + ti,bit-shift = <5>; + }; + + omap_48m_fck: clock-omap-48m-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "omap_48m_fck"; + clocks = <&cm_96m_d2_fck>, <&sys_altclk>; + ti,bit-shift = <3>; + }; }; dpll4_m3_ck: dpll4_m3_ck@e40 { @@ -396,14 +420,6 @@ dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { ti,set-bit-to-disable; }; - omap_54m_fck: omap_54m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; - ti,bit-shift = <5>; - reg = <0x0d40>; - }; - cm_96m_d2_fck: cm_96m_d2_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -412,14 +428,6 @@ cm_96m_d2_fck: cm_96m_d2_fck { clock-div = <2>; }; - omap_48m_fck: omap_48m_fck@d40 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&cm_96m_d2_fck>, <&sys_altclk>; - ti,bit-shift = <3>; - reg = <0x0d40>; - }; - omap_12m_fck: omap_12m_fck { #clock-cells = <0>; compatible = "fixed-factor-clock"; From 0019a9543a71995304bf2c2aa493d8242f387587 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 17/26] ARM: dts: Group omap3 CM_CLKOUT_CTRL clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 52 +++++++++++++++----------- 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index d101f0a40502..01c4b312c89a 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -527,19 +527,37 @@ emu_per_alwon_ck: emu_per_alwon_ck { clock-div = <1>; }; - clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clocks = <&core_ck>; - ti,bit-shift = <7>; - reg = <0x0d70>; - }; + /* CM_CLKOUT_CTRL */ + clock@d70 { + compatible = "ti,clksel"; + reg = <0xd70>; + #clock-cells = <2>; + #address-cells = <0>; - clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; - reg = <0x0d70>; + clkout2_src_gate_ck: clock-clkout2-src-gate { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clock-output-names = "clkout2_src_gate_ck"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + }; + + clkout2_src_mux_ck: clock-clkout2-src-mux { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "clkout2_src_mux_ck"; + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; + }; + + sys_clkout2: clock-sys-clkout2 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "sys_clkout2"; + clocks = <&clkout2_src_ck>; + ti,bit-shift = <3>; + ti,max-div = <64>; + ti,index-power-of-two; + }; }; clkout2_src_ck: clkout2_src_ck { @@ -548,16 +566,6 @@ clkout2_src_ck: clkout2_src_ck { clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; }; - sys_clkout2: sys_clkout2@d70 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout2_src_ck>; - ti,bit-shift = <3>; - ti,max-div = <64>; - reg = <0x0d70>; - ti,index-power-of-two; - }; - mpu_ck: mpu_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; From 89953638a83cb5b55193f720653de931fa92347c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 18/26] ARM: dts: Group omap3 CM_FCLKEN_DSS clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 21 +++++--- ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 21 +++++--- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 48 +++++++++++-------- 3 files changed, 56 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 7dbab6eb2e6d..24adfac26be0 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -170,13 +170,20 @@ usb_l4_ick: usb_l4_ick { clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es1"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es1@e10 { diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 1c41530cc16a..dcc5cfcd1fe6 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -179,13 +179,20 @@ mmchs3_fck: clock-mmchs3-fck { }; }; - dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { - #clock-cells = <0>; - compatible = "ti,dss-gate-clock"; - clocks = <&dpll4_m4x2_ck>; - ti,bit-shift = <0>; - reg = <0x0e00>; - ti,set-rate-parent; + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; + + dss1_alwon_fck: clock-dss1-alwon-fck-3430es2 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clock-output-names = "dss1_alwon_fck_3430es2"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; }; dss_ick: dss_ick_3430es2@e10 { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 01c4b312c89a..5a192fc149c0 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1022,28 +1022,36 @@ core_l4_ick: core_l4_ick { clock-div = <1>; }; - dss_tv_fck: dss_tv_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_54m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; + /* CM_FCLKEN_DSS */ + clock@e00 { + compatible = "ti,clksel"; + reg = <0xe00>; + #clock-cells = <2>; + #address-cells = <0>; - dss_96m_fck: dss_96m_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&omap_96m_fck>; - reg = <0x0e00>; - ti,bit-shift = <2>; - }; + dss_tv_fck: clock-dss-tv-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_tv_fck"; + clocks = <&omap_54m_fck>; + ti,bit-shift = <2>; + }; - dss2_alwon_fck: dss2_alwon_fck@e00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sys_ck>; - reg = <0x0e00>; - ti,bit-shift = <1>; + dss_96m_fck: clock-dss-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss_96m_fck"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <2>; + }; + + dss2_alwon_fck: clock-dss2-alwon-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "dss2_alwon_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <1>; + }; }; dummy_ck: dummy_ck { From 2d09a2a9d13163b9b401cc0d88c1166c6dd18b1c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 19/26] ARM: dts: Group omap3 CM_CLKSEL_DSS clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 42 +++++++++++++++----------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 5a192fc149c0..30f6847ef65e 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -393,14 +393,31 @@ omap_48m_fck: clock-omap-48m-fck { }; }; - dpll4_m3_ck: dpll4_m3_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <8>; - ti,max-div = <32>; - reg = <0x0e40>; - ti,index-starts-at-one; + /* CM_CLKSEL_DSS */ + clock@e40 { + compatible = "ti,clksel"; + reg = <0xe40>; + #clock-cells = <2>; + #address-cells = <0>; + + dpll4_m3_ck: clock-dpll4-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m3_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-starts-at-one; + }; + + dpll4_m4_ck: clock-dpll4-m4 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m4_ck"; + clocks = <&dpll4_ck>; + ti,max-div = <16>; + ti,index-starts-at-one; + }; }; dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { @@ -436,15 +453,6 @@ omap_12m_fck: omap_12m_fck { clock-div = <4>; }; - dpll4_m4_ck: dpll4_m4_ck@e40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,max-div = <16>; - reg = <0x0e40>; - ti,index-starts-at-one; - }; - dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; From 32169e7ef4be5cb3af7c2c32fde9e07171b4c80b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 20/26] ARM: dts: Group omap3 CM_FCLKEN_CAM clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- .../boot/dts/omap34xx-omap36xx-clocks.dtsi | 38 +++++++++++-------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index edc28654d158..8374532f20e2 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -60,13 +60,29 @@ pka_ick: clock-pka-ick { }; }; - cam_mclk: cam_mclk@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&dpll4_m5x2_ck>; - ti,bit-shift = <0>; - reg = <0x0f00>; - ti,set-rate-parent; + /* CM_FCLKEN_CAM */ + clock@f00 { + compatible = "ti,clksel"; + reg = <0xf00>; + #clock-cells = <2>; + #address-cells = <0>; + + cam_mclk: clock-cam-mclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "cam_mclk"; + clocks = <&dpll4_m5x2_ck>; + ti,bit-shift = <0>; + ti,set-rate-parent; + }; + + csi2_96m_fck: clock-csi2-96m-fck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "csi2_96m_fck"; + clocks = <&core_96m_fck>; + ti,bit-shift = <1>; + }; }; cam_ick: cam_ick@f10 { @@ -77,14 +93,6 @@ cam_ick: cam_ick@f10 { ti,bit-shift = <0>; }; - csi2_96m_fck: csi2_96m_fck@f00 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&core_96m_fck>; - reg = <0x0f00>; - ti,bit-shift = <1>; - }; - security_l3_ick: security_l3_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; From b508079bf2dca43995eb2cfa2aef5a4e7d82d2e6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 21/26] ARM: dts: Group omap3 CM_FCLKEN_PER clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap36xx-clocks.dtsi | 17 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 288 +++++++++++++------------ 2 files changed, 160 insertions(+), 145 deletions(-) diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 4e9cc9003594..c5fdb2bd765d 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -58,12 +58,19 @@ dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { ti,set-bit-to-disable; }; - uart4_fck: uart4_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - ti,bit-shift = <18>; + #clock-cells = <2>; + #address-cells = <0>; + + uart4_fck: clock-uart4-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart4_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <18>; + }; }; }; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 30f6847ef65e..fa5b5756545c 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1186,20 +1186,156 @@ per_48m_fck: per_48m_fck { clock-div = <1>; }; - uart3_fck: uart3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_48m_fck>; + /* CM_FCLKEN_PER */ + clock@1000 { + compatible = "ti,clksel"; reg = <0x1000>; - ti,bit-shift = <11>; - }; + #clock-cells = <2>; + #address-cells = <0>; - gpt2_gate_fck: gpt2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1000>; + uart3_fck: clock-uart3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "uart3_fck"; + clocks = <&per_48m_fck>; + ti,bit-shift = <11>; + }; + + gpt2_gate_fck: clock-gpt2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt2_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt3_gate_fck: clock-gpt3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt3_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt4_gate_fck: clock-gpt4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt4_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt5_gate_fck: clock-gpt5-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt5_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt6_gate_fck: clock-gpt6-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt6_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + }; + + gpt7_gate_fck: clock-gpt7-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt7_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <8>; + }; + + gpt8_gate_fck: clock-gpt8-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt8_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <9>; + }; + + gpt9_gate_fck: clock-gpt9-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "gpt9_gate_fck"; + clocks = <&sys_ck>; + ti,bit-shift = <10>; + }; + + gpio6_dbck: clock-gpio6-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio6_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <17>; + }; + + gpio5_dbck: clock-gpio5-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio5_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <16>; + }; + + gpio4_dbck: clock-gpio4-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio4_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <15>; + }; + + gpio3_dbck: clock-gpio3-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio3_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <14>; + }; + + gpio2_dbck: clock-gpio2-dbck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clock-output-names = "gpio2_dbck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <13>; + }; + + wdt3_fck: clock-wdt3-fck { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clock-output-names = "wdt3_fck"; + clocks = <&per_32k_alwon_fck>; + ti,bit-shift = <12>; + }; + + mcbsp2_gate_fck: clock-mcbsp2-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp2_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <0>; + }; + + mcbsp3_gate_fck: clock-mcbsp3-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp3_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <1>; + }; + + mcbsp4_gate_fck: clock-mcbsp4-gate-fck { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clock-output-names = "mcbsp4_gate_fck"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <2>; + }; }; gpt2_mux_fck: gpt2_mux_fck@1040 { @@ -1215,14 +1351,6 @@ gpt2_fck: gpt2_fck { clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_gate_fck: gpt3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1000>; - }; - gpt3_mux_fck: gpt3_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1237,14 +1365,6 @@ gpt3_fck: gpt3_fck { clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_gate_fck: gpt4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1000>; - }; - gpt4_mux_fck: gpt4_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1259,14 +1379,6 @@ gpt4_fck: gpt4_fck { clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_gate_fck: gpt5_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1000>; - }; - gpt5_mux_fck: gpt5_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1281,14 +1393,6 @@ gpt5_fck: gpt5_fck { clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_gate_fck: gpt6_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1000>; - }; - gpt6_mux_fck: gpt6_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1303,14 +1407,6 @@ gpt6_fck: gpt6_fck { clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_gate_fck: gpt7_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <8>; - reg = <0x1000>; - }; - gpt7_mux_fck: gpt7_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1325,14 +1421,6 @@ gpt7_fck: gpt7_fck { clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_gate_fck: gpt8_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <9>; - reg = <0x1000>; - }; - gpt8_mux_fck: gpt8_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1347,14 +1435,6 @@ gpt8_fck: gpt8_fck { clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_gate_fck: gpt9_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <10>; - reg = <0x1000>; - }; - gpt9_mux_fck: gpt9_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; @@ -1377,54 +1457,6 @@ per_32k_alwon_fck: per_32k_alwon_fck { clock-div = <1>; }; - gpio6_dbck: gpio6_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <17>; - }; - - gpio5_dbck: gpio5_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <16>; - }; - - gpio4_dbck: gpio4_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <15>; - }; - - gpio3_dbck: gpio3_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <14>; - }; - - gpio2_dbck: gpio2_dbck@1000 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <13>; - }; - - wdt3_fck: wdt3_fck@1000 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&per_32k_alwon_fck>; - reg = <0x1000>; - ti,bit-shift = <12>; - }; - per_l4_ick: per_l4_ick { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1585,30 +1617,6 @@ mcbsp4_ick: mcbsp4_ick@1010 { ti,bit-shift = <2>; }; - mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <0>; - reg = <0x1000>; - }; - - mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <1>; - reg = <0x1000>; - }; - - mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { - #clock-cells = <0>; - compatible = "ti,composite-gate-clock"; - clocks = <&mcbsp_clks>; - ti,bit-shift = <2>; - reg = <0x1000>; - }; - emu_src_mux_ck: emu_src_mux_ck@1140 { #clock-cells = <0>; compatible = "ti,mux-clock"; From cab3db1b8d15a4daccda72f94397192bc6e4d298 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 22/26] ARM: dts: Group omap3 CM_ICLKEN_PER clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 270 +++++++++++++------------ 1 file changed, 139 insertions(+), 131 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index fa5b5756545c..05e5d50fa022 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1465,156 +1465,164 @@ per_l4_ick: per_l4_ick { clock-div = <1>; }; - gpio6_ick: gpio6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; + /* CM_ICLKEN_PER */ + clock@1010 { + compatible = "ti,clksel"; reg = <0x1010>; - ti,bit-shift = <17>; - }; + #clock-cells = <2>; + #address-cells = <0>; - gpio5_ick: gpio5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <16>; - }; + gpio6_ick: clock-gpio6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <17>; + }; - gpio4_ick: gpio4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <15>; - }; + gpio5_ick: clock-gpio5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <16>; + }; - gpio3_ick: gpio3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <14>; - }; + gpio4_ick: clock-gpio4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <15>; + }; - gpio2_ick: gpio2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <13>; - }; + gpio3_ick: clock-gpio3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <14>; + }; - wdt3_ick: wdt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <12>; - }; + gpio2_ick: clock-gpio2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpio2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <13>; + }; - uart3_ick: uart3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <11>; - }; + wdt3_ick: clock-wdt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "wdt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <12>; + }; - uart4_ick: uart4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <18>; - }; + uart3_ick: clock-uart3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <11>; + }; - gpt9_ick: gpt9_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <10>; - }; + uart4_ick: clock-uart4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "uart4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <18>; + }; - gpt8_ick: gpt8_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <9>; - }; + gpt9_ick: clock-gpt9-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt9_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <10>; + }; - gpt7_ick: gpt7_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <8>; - }; + gpt8_ick: clock-gpt8-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt8_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <9>; + }; - gpt6_ick: gpt6_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <7>; - }; + gpt7_ick: clock-gpt7-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt7_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <8>; + }; - gpt5_ick: gpt5_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <6>; - }; + gpt6_ick: clock-gpt6-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt6_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <7>; + }; - gpt4_ick: gpt4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <5>; - }; + gpt5_ick: clock-gpt5-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt5_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <6>; + }; - gpt3_ick: gpt3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <4>; - }; + gpt4_ick: clock-gpt4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <5>; + }; - gpt2_ick: gpt2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <3>; - }; + gpt3_ick: clock-gpt3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <4>; + }; - mcbsp2_ick: mcbsp2_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <0>; - }; + gpt2_ick: clock-gpt2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "gpt2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <3>; + }; - mcbsp3_ick: mcbsp3_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <1>; - }; + mcbsp2_ick: clock-mcbsp2-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp2_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <0>; + }; - mcbsp4_ick: mcbsp4_ick@1010 { - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clocks = <&per_l4_ick>; - reg = <0x1010>; - ti,bit-shift = <2>; + mcbsp3_ick: clock-mcbsp3-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp3_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <1>; + }; + + mcbsp4_ick: clock-mcbsp4-ick { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clock-output-names = "mcbsp4_ick"; + clocks = <&per_l4_ick>; + ti,bit-shift = <2>; + }; }; emu_src_mux_ck: emu_src_mux_ck@1140 { From c22a3d8cad504f18efb437a6998f8948e7dc992f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 23/26] ARM: dts: Group omap3 CM_CLKSEL_PER clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 128 +++++++++++++------------ 1 file changed, 68 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 05e5d50fa022..8a16e49fdf24 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -1338,11 +1338,75 @@ mcbsp4_gate_fck: clock-mcbsp4-gate-fck { }; }; - gpt2_mux_fck: gpt2_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; + /* CM_CLKSEL_PER */ + clock@1040 { + compatible = "ti,clksel"; reg = <0x1040>; + #clock-cells = <2>; + #address-cells = <0>; + + gpt2_mux_fck: clock-gpt2-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt2_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + }; + + gpt3_mux_fck: clock-gpt3-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt3_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <1>; + }; + + gpt4_mux_fck: clock-gpt4-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt4_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <2>; + }; + + gpt5_mux_fck: clock-gpt5-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt5_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <3>; + }; + + gpt6_mux_fck: clock-gpt6-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt6_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <4>; + }; + + gpt7_mux_fck: clock-gpt7-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt7_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <5>; + }; + + gpt8_mux_fck: clock-gpt8-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt8_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + }; + + gpt9_mux_fck: clock-gpt9-mux-fck { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clock-output-names = "gpt9_mux_fck"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + }; }; gpt2_fck: gpt2_fck { @@ -1351,98 +1415,42 @@ gpt2_fck: gpt2_fck { clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_mux_fck: gpt3_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <1>; - reg = <0x1040>; - }; - gpt3_fck: gpt3_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_mux_fck: gpt4_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <2>; - reg = <0x1040>; - }; - gpt4_fck: gpt4_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_mux_fck: gpt5_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <3>; - reg = <0x1040>; - }; - gpt5_fck: gpt5_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_mux_fck: gpt6_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <4>; - reg = <0x1040>; - }; - gpt6_fck: gpt6_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_mux_fck: gpt7_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <5>; - reg = <0x1040>; - }; - gpt7_fck: gpt7_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_mux_fck: gpt8_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <6>; - reg = <0x1040>; - }; - gpt8_fck: gpt8_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_mux_fck: gpt9_mux_fck@1040 { - #clock-cells = <0>; - compatible = "ti,composite-mux-clock"; - clocks = <&omap_32k_fck>, <&sys_ck>; - ti,bit-shift = <7>; - reg = <0x1040>; - }; - gpt9_fck: gpt9_fck { #clock-cells = <0>; compatible = "ti,composite-clock"; From 29a5f5f0b08af1bac5c3d2c0948ed7f56ba4d255 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 29 Apr 2022 09:57:36 +0300 Subject: [PATCH 24/26] ARM: dts: Group omap3 CM_CLKSEL1_EMU clocks The clksel related registers on omap3 cause unique_unit_address and node_name_chars_strict warnings with the W=1 or W=2 make flags enabled. With the clock drivers updated, we can now avoid most of these warnings by grouping the TI component clocks using the TI clksel binding, and with the use of clock-output-names property to avoid non-standard node names for the clocks. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 152 +++++++++++++------------ 1 file changed, 80 insertions(+), 72 deletions(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 8a16e49fdf24..2e13ca11ceea 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -254,14 +254,87 @@ dpll3_ck: dpll3_ck@d00 { reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; }; - dpll3_m3_ck: dpll3_m3_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll3_ck>; - ti,bit-shift = <16>; - ti,max-div = <31>; + /* CM_CLKSEL1_EMU */ + clock@1140 { + compatible = "ti,clksel"; reg = <0x1140>; - ti,index-starts-at-one; + #clock-cells = <2>; + #address-cells = <0>; + + dpll3_m3_ck: clock-dpll3-m3 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll3_m3_ck"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + ti,index-starts-at-one; + }; + + dpll4_m6_ck: clock-dpll4-m6 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "dpll4_m6_ck"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + ti,index-starts-at-one; + }; + + emu_src_mux_ck: clock-emu-src-mux { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "emu_src_mux_ck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + }; + + pclk_fck: clock-pclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; + + pclkx2_fck: clock-pclkx2-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "pclkx2_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + atclk_fck: clock-atclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "atclk_fck"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: clock-traceclk-src-fck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clock-output-names = "traceclk_src_fck"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + }; + + traceclk_fck: clock-traceclk-fck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clock-output-names = "traceclk_fck"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + ti,index-starts-at-one; + }; }; dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { @@ -500,16 +573,6 @@ dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { ti,set-rate-parent; }; - dpll4_m6_ck: dpll4_m6_ck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll4_ck>; - ti,bit-shift = <24>; - ti,max-div = <63>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -1633,67 +1696,12 @@ mcbsp4_ick: clock-mcbsp4-ick { }; }; - emu_src_mux_ck: emu_src_mux_ck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - reg = <0x1140>; - }; - emu_src_ck: emu_src_ck { #clock-cells = <0>; compatible = "ti,clkdm-gate-clock"; clocks = <&emu_src_mux_ck>; }; - pclk_fck: pclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <8>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - pclkx2_fck: pclkx2_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <6>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - atclk_fck: atclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&emu_src_ck>; - ti,bit-shift = <4>; - ti,max-div = <3>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - - traceclk_src_fck: traceclk_src_fck@1140 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; - ti,bit-shift = <2>; - reg = <0x1140>; - }; - - traceclk_fck: traceclk_fck@1140 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&traceclk_src_fck>; - ti,bit-shift = <11>; - ti,max-div = <7>; - reg = <0x1140>; - ti,index-starts-at-one; - }; - secure_32k_fck: secure_32k_fck { #clock-cells = <0>; compatible = "fixed-clock"; From f960b54b6f195817f5a9c62257edfd602f026725 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2022 08:51:59 +0200 Subject: [PATCH 25/26] ARM: dts: am33xx: use new 'dma-channels/requests' properties The '#dma-channels' and '#dma-requests' properties were deprecated in favor of these defined by generic dma-common DT bindings. Add new properties while keeping old ones for backwards compatibility. Signed-off-by: Krzysztof Kozlowski Message-Id: <20220503065201.51818-5-krzysztof.kozlowski@linaro.org> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index f6ec85d58dd1..9a8698bd2852 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -461,8 +461,11 @@ cppi41dma: dma-controller@2000 { interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; From e4edfeaf6b585fac340071ea9845970ab528c6ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2022 08:52:01 +0200 Subject: [PATCH 26/26] ARM: dts: dm81xx: use new 'dma-channels/requests' properties The '#dma-channels' and '#dma-requests' properties were deprecated in favor of these defined by generic dma-common DT bindings. Add new properties while keeping old ones for backwards compatibility. Signed-off-by: Krzysztof Kozlowski Message-Id: <20220503065201.51818-7-krzysztof.kozlowski@linaro.org> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 3 +++ arch/arm/boot/dts/dm816x.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 7702e048e110..a92630113f57 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -167,8 +167,11 @@ cppi41dma: dma-controller@47402000 { interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; }; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index a9e7274806f4..eb0a95da94b2 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -655,8 +655,11 @@ cppi41dma: dma-controller@47402000 { interrupts = <17>; interrupt-names = "glue"; #dma-cells = <2>; + /* For backwards compatibility: */ #dma-channels = <30>; + dma-channels = <30>; #dma-requests = <256>; + dma-requests = <256>; }; };