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iio: dac: ad5758: Fix alignment for DMA safety

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ad5758_spi_reg_read() reads into st->d32[2] with spi_sync_transfer(),
but d32 is not marked __aligned(IIO_DMA_MINALIGN), so it can share a
cacheline with the fields before it. When DMA is not cache coherent,
the cache invalidation after the read can discard CPU writes to those
fields.

Mark d32 __aligned(IIO_DMA_MINALIGN). It is the last member of the
struct, so nothing comes after it.

Fixes: 28d1a7ac2a ("iio: dac: Add AD5758 support")
Signed-off-by: Arka Mondal <arka@arkamondal.net>
Reviewed-by: Nuno Sá <nuno.sa@analog.com>
Signed-off-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
This commit is contained in:
Arka Mondal 2026-09-18 21:20:28 +09:00 committed by Jonathan Cameron
parent 89bda80f66
commit 465bdce79a
1 changed files with 1 additions and 1 deletions
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drivers/iio/dac/ad5758.c
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@ -117,7 +117,7 @@ struct ad5758_state {
unsigned int dc_dc_ilim;
unsigned int slew_time;
bool pwr_down;
__be32 d32[3];
__be32 d32[3] __aligned(IIO_DMA_MINALIGN);
};
/*