From 465bdce79a9fe140a4b46b95f6bdfd880d197148 Mon Sep 17 00:00:00 2001 From: Arka Mondal Date: Fri, 18 Sep 2026 21:20:28 +0900 Subject: [PATCH] iio: dac: ad5758: Fix alignment for DMA safety MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ad5758_spi_reg_read() reads into st->d32[2] with spi_sync_transfer(), but d32 is not marked __aligned(IIO_DMA_MINALIGN), so it can share a cacheline with the fields before it. When DMA is not cache coherent, the cache invalidation after the read can discard CPU writes to those fields. Mark d32 __aligned(IIO_DMA_MINALIGN). It is the last member of the struct, so nothing comes after it. Fixes: 28d1a7ac2a0d ("iio: dac: Add AD5758 support") Signed-off-by: Arka Mondal Reviewed-by: Nuno Sá Signed-off-by: Jonathan Cameron --- drivers/iio/dac/ad5758.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/dac/ad5758.c b/drivers/iio/dac/ad5758.c index 44efa373cd80..ba381bd252d1 100644 --- a/drivers/iio/dac/ad5758.c +++ b/drivers/iio/dac/ad5758.c @@ -117,7 +117,7 @@ struct ad5758_state { unsigned int dc_dc_ilim; unsigned int slew_time; bool pwr_down; - __be32 d32[3]; + __be32 d32[3] __aligned(IIO_DMA_MINALIGN); }; /*