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clk: rockchip: px30: Add CLK_SET_RATE_PARENT for clk_i2s1_out_pre

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Change-Id: Ie01e78ecf49cbbc3101c7ff0fafff11d3428b271
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Wyon Bi 2019-08-13 10:34:52 +08:00 committed by Tao Huang
parent 2b1b3a5b70
commit 45e8903744
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-px30.c
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@ -629,7 +629,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
&px30_i2s1_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(10), 2, GFLAGS),
COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0,
COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(30), 15, 1, MFLAGS,
PX30_CLKGATE_CON(10), 3, GFLAGS),
GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,