From 45e89037444e6ddbbf912ba06fe6c5a9aa187d25 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Tue, 13 Aug 2019 10:34:52 +0800 Subject: [PATCH] clk: rockchip: px30: Add CLK_SET_RATE_PARENT for clk_i2s1_out_pre Change-Id: Ie01e78ecf49cbbc3101c7ff0fafff11d3428b271 Signed-off-by: Wyon Bi Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-px30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 55ee46bc50bb..b7cf171f5bd3 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -629,7 +629,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { &px30_i2s1_fracmux, PX30_FRAC_MAX_PRATE), GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(10), 2, GFLAGS), - COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, 0, + COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, CLK_SET_RATE_PARENT, PX30_CLKSEL_CON(30), 15, 1, MFLAGS, PX30_CLKGATE_CON(10), 3, GFLAGS), GATE(SCLK_I2S1_OUT, "clk_i2s1_out", "clk_i2s1_out_pre", CLK_SET_RATE_PARENT,