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RISC-V Devicetree fixes for v6.7-rc4

Browse Source 
Two fixes, both rather minor. The first fixes some dtbs_check warnings
 introduced after an update to the bindings, that returns the
 architecture to being clean of dtbs_check issues. The second relocates
 a soc-specific property to the appropriate location in $soc.dtsi, and
 hopefully avoids the same mistake being copy-pasted into more
 devicetrees.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Merge tag 'riscv-dt-fixes-for-v6.7-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes

RISC-V Devicetree fixes for v6.7-rc4

Two fixes, both rather minor. The first fixes some dtbs_check warnings
introduced after an update to the bindings, that returns the
architecture to being clean of dtbs_check issues. The second relocates
a soc-specific property to the appropriate location in $soc.dtsi, and
hopefully avoids the same mistake being copy-pasted into more
devicetrees.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-fixes-for-v6.7-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: microchip: move timebase-frequency to mpfs.dtsi
  riscv: dts: sophgo: remove address-cells from intc node

Link: https://lore.kernel.org/r/20231130-maternity-majestic-dd29f0170050@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-12-06 16:24:07 +01:00
commit 437c99c256
7 changed files with 1 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
View File

@ -8,9 +8,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
@ -29,10 +26,6 @@ chosen {
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
leds {
compatible = "gpio-leds";

7
arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts
View File

@ -10,9 +10,6 @@
#include "mpfs.dtsi"
#include "mpfs-m100pfs-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
model = "Aries Embedded M100PFEVPS";
compatible = "aries,m100pfsevp", "microchip,mpfs";
@ -33,10 +30,6 @@ chosen {
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;

7
arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
View File

@ -6,9 +6,6 @@
#include "mpfs.dtsi"
#include "mpfs-polarberry-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
model = "Sundance PolarBerry";
compatible = "sundance,polarberry", "microchip,mpfs";
@ -22,10 +19,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2e000000>;

7
arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts
View File

@ -6,9 +6,6 @@
#include "mpfs.dtsi"
#include "mpfs-sev-kit-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
@ -28,10 +25,6 @@ chosen {
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;

7
arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
View File

@ -11,9 +11,6 @@
#include "mpfs.dtsi"
#include "mpfs-tysom-m-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
model = "Aldec TySOM-M-MPFS250T-REV2";
compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
@ -34,10 +31,6 @@ chosen {
stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x30000000>;

1
arch/riscv/boot/dts/microchip/mpfs.dtsi
View File

@ -13,6 +13,7 @@ / {
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";

1
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
View File

@ -34,7 +34,6 @@ cpu0: cpu@0 {
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};