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MediaTek ARM64 DeviceTree fixes for v6.7

Browse Source 
Fixes for various MediaTek SoCs, including
 
 MT7986: - eMMC HS400 mode failures
         - Cooling trips for emergency system shutdown
         - BPI-R3 machine SFP power limit and active cooling
 
 MT8173: - EVB device tree unit_address_vs_reg warning
 
 MT8183: - unit_address_vs_reg and simple_bus_reg warnings
         - Kukui device tree nodes naming consistency and
           adhering to bindings
         - Jacuzzi device tree unnecessary cells removed as
           those were producing avoid_unnecessary_addr_size
 
 MT8186: - Power domains faults due to incorrect clocks
         - GPU speed bin nvmem cell name was wrong, producing
           issues with interpreting the speedbin with GPU OPPs
 
 MT8195: - Local Arbiter (and whole system) ability to suspend
         - Cherry device tree interrupts_property warning
 
 ...and another unit_address_vs_reg warning on MT7622.
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Merge tag 'mtk-dts64-fixes-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into arm/fixes

MediaTek ARM64 DeviceTree fixes for v6.7

Fixes for various MediaTek SoCs, including

MT7986: - eMMC HS400 mode failures
        - Cooling trips for emergency system shutdown
        - BPI-R3 machine SFP power limit and active cooling

MT8173: - EVB device tree unit_address_vs_reg warning

MT8183: - unit_address_vs_reg and simple_bus_reg warnings
        - Kukui device tree nodes naming consistency and
          adhering to bindings
        - Jacuzzi device tree unnecessary cells removed as
          those were producing avoid_unnecessary_addr_size

MT8186: - Power domains faults due to incorrect clocks
        - GPU speed bin nvmem cell name was wrong, producing
          issues with interpreting the speedbin with GPU OPPs

MT8195: - Local Arbiter (and whole system) ability to suspend
        - Cherry device tree interrupts_property warning

...and another unit_address_vs_reg warning on MT7622.

* tag 'mtk-dts64-fixes-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  arm64: dts: mediatek: cherry: Fix interrupt cells for MT6360 on I2C7
  arm64: dts: mediatek: mt8183-kukui-jacuzzi: fix dsi unnecessary cells properties
  arm64: dts: mediatek: mt7622: fix memory node warning check
  arm64: dts: mediatek: mt8186: fix clock names for power domains
  arm64: dts: mediatek: mt8186: Change gpu speedbin nvmem cell name
  arm64: dts: mt7986: change cooling trips
  arm64: dts: mt7986: define 3W max power to both SFP on BPI-R3
  arm64: dts: mt7986: fix emmc hs400 mode without uboot initialization
  arm64: dts: mt8183: kukui: Fix underscores in node names
  arm64: dts: mediatek: mt8183: Move thermal-zones to the root node
  arm64: dts: mediatek: mt8173-evb: Fix regulator-fixed node names
  arm64: dts: mediatek: mt8183-evb: Fix unit_address_vs_reg warning on ntc
  arm64: dts: mediatek: mt8183: Fix unit address for scp reserved memory
  arm64: dts: mediatek: mt8195: Fix PM suspend/resume with venc clocks

Link: https://lore.kernel.org/r/20231129113905.134732-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-12-06 16:23:10 +01:00
commit 1133ae113d
12 changed files with 241 additions and 205 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
View File

@ -73,7 +73,7 @@ led-1 {
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
};

2
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@ -55,7 +55,7 @@ key-wps {
};
};
memory {
memory@40000000 {
reg = <0 0x40000000 0 0x20000000>;
};

12
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
View File

@ -126,6 +126,7 @@ sfp1: sfp-1 {
compatible = "sff,sfp";
i2c-bus = <&i2c_sfp1>;
los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <3000>;
mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
@ -137,6 +138,7 @@ sfp2: sfp-2 {
i2c-bus = <&i2c_sfp2>;
los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <3000>;
tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
};
@ -150,16 +152,16 @@ cpu-active-high {
trip = <&cpu_trip_active_high>;
};
cpu-active-low {
cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_low>;
trip = <&cpu_trip_active_med>;
};
cpu-passive {
/* passive: set fan to cooling level 0 */
cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_passive>;
trip = <&cpu_trip_active_low>;
};
};
};

24
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@ -374,6 +374,10 @@ mmc0: mmc@11230000 {
reg = <0 0x11230000 0 0x1000>,
<0 0x11c20000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&topckgen CLK_TOP_EMMC_250M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
<&topckgen CLK_TOP_NET1PLL_D5_D2>;
clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
<&infracfg CLK_INFRA_MSDC_CK>,
@ -610,22 +614,34 @@ cpu_thermal: cpu-thermal {
thermal-sensors = <&thermal 0>;
trips {
cpu_trip_crit: crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
cpu_trip_hot: hot {
temperature = <120000>;
hysteresis = <2000>;
type = "hot";
};
cpu_trip_active_high: active-high {
temperature = <115000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_active_low: active-low {
cpu_trip_active_med: active-med {
temperature = <85000>;
hysteresis = <2000>;
type = "active";
};
cpu_trip_passive: passive {
temperature = <40000>;
cpu_trip_active_low: active-low {
temperature = <60000>;
hysteresis = <2000>;
type = "passive";
type = "active";
};
};
};

4
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View File

@ -44,7 +44,7 @@ extcon_usb: extcon_iddig {
id-gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
};
usb_p1_vbus: regulator@0 {
usb_p1_vbus: regulator-usb-p1 {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
@ -53,7 +53,7 @@ usb_p1_vbus: regulator@0 {
enable-active-high;
};
usb_p0_vbus: regulator@1 {
usb_p0_vbus: regulator-usb-p0 {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;

4
arch/arm64/boot/dts/mediatek/mt8183-evb.dts
View File

@ -31,14 +31,14 @@ reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
};
};
ntc@0 {
thermal-sensor {
compatible = "murata,ncp03wf104";
pullup-uv = <1800000>;
pullup-ohm = <390000>;

8
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi
View File

@ -91,6 +91,8 @@ cros_ec_pwm: pwm {
&dsi0 {
status = "okay";
/delete-property/#size-cells;
/delete-property/#address-cells;
/delete-node/panel@0;
ports {
port {
@ -441,20 +443,20 @@ pins2 {
};
touchscreen_pins: touchscreen-pins {
touch_int_odl {
touch-int-odl {
pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
input-enable;
bias-pull-up;
};
touch_rst_l {
touch-rst-l {
pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
output-high;
};
};
trackpad_pins: trackpad-pins {
trackpad_int {
trackpad-int {
pinmux = <PINMUX_GPIO7__FUNC_GPIO7>;
input-enable;
bias-disable; /* pulled externally */

96
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -116,7 +116,7 @@ reserved_memory: reserved-memory {
#size-cells = <2>;
ranges;
scp_mem_reserved: scp_mem_region {
scp_mem_reserved: memory@50000000 {
compatible = "shared-dma-pool";
reg = <0 0x50000000 0 0x2900000>;
no-map;
@ -460,7 +460,7 @@ &mt6358_vsram_gpu_reg {
&pio {
aud_pins_default: audiopins {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO97__FUNC_I2S2_MCK>,
<PINMUX_GPIO98__FUNC_I2S2_BCK>,
<PINMUX_GPIO101__FUNC_I2S2_LRCK>,
@ -482,7 +482,7 @@ pins_bus {
};
aud_pins_tdm_out_on: audiotdmouton {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_TDM_BCK_2ND>,
<PINMUX_GPIO170__FUNC_TDM_LRCK_2ND>,
<PINMUX_GPIO171__FUNC_TDM_DATA0_2ND>,
@ -494,7 +494,7 @@ pins_bus {
};
aud_pins_tdm_out_off: audiotdmoutoff {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO169__FUNC_GPIO169>,
<PINMUX_GPIO170__FUNC_GPIO170>,
<PINMUX_GPIO171__FUNC_GPIO171>,
@ -508,13 +508,13 @@ pins_bus {
};
bt_pins: bt-pins {
pins_bt_en {
pins-bt-en {
pinmux = <PINMUX_GPIO120__FUNC_GPIO120>;
output-low;
};
};
ec_ap_int_odl: ec_ap_int_odl {
ec_ap_int_odl: ec-ap-int-odl {
pins1 {
pinmux = <PINMUX_GPIO151__FUNC_GPIO151>;
input-enable;
@ -522,7 +522,7 @@ pins1 {
};
};
h1_int_od_l: h1_int_od_l {
h1_int_od_l: h1-int-od-l {
pins1 {
pinmux = <PINMUX_GPIO153__FUNC_GPIO153>;
input-enable;
@ -530,7 +530,7 @@ pins1 {
};
i2c0_pins: i2c0 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
<PINMUX_GPIO83__FUNC_SCL0>;
mediatek,pull-up-adv = <3>;
@ -539,7 +539,7 @@ pins_bus {
};
i2c1_pins: i2c1 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
<PINMUX_GPIO84__FUNC_SCL1>;
mediatek,pull-up-adv = <3>;
@ -548,7 +548,7 @@ pins_bus {
};
i2c2_pins: i2c2 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
<PINMUX_GPIO104__FUNC_SDA2>;
bias-disable;
@ -557,7 +557,7 @@ pins_bus {
};
i2c3_pins: i2c3 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-up-adv = <3>;
@ -566,7 +566,7 @@ pins_bus {
};
i2c4_pins: i2c4 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
<PINMUX_GPIO106__FUNC_SDA4>;
bias-disable;
@ -575,7 +575,7 @@ pins_bus {
};
i2c5_pins: i2c5 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
@ -584,7 +584,7 @@ pins_bus {
};
i2c6_pins: i2c6 {
pins_bus {
pins-bus {
pinmux = <PINMUX_GPIO11__FUNC_SCL6>,
<PINMUX_GPIO12__FUNC_SDA6>;
bias-disable;
@ -592,7 +592,7 @@ pins_bus {
};
mmc0_pins_default: mmc0-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -607,13 +607,13 @@ pins_cmd_dat {
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <01>;
@ -621,7 +621,7 @@ pins_rst {
};
mmc0_pins_uhs: mmc0-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
<PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
<PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
@ -636,19 +636,19 @@ pins_cmd_dat {
mediatek,pull-up-adv = <01>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_ds {
pins-ds {
pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-down-adv = <10>;
};
pins_rst {
pins-rst {
pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
drive-strength = <MTK_DRIVE_14mA>;
mediatek,pull-up-adv = <01>;
@ -656,7 +656,7 @@ pins_rst {
};
mmc1_pins_default: mmc1-pins-default {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -666,7 +666,7 @@ pins_cmd_dat {
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
input-enable;
mediatek,pull-down-adv = <10>;
@ -674,7 +674,7 @@ pins_clk {
};
mmc1_pins_uhs: mmc1-pins-uhs {
pins_cmd_dat {
pins-cmd-dat {
pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
<PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
<PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
@ -685,7 +685,7 @@ pins_cmd_dat {
mediatek,pull-up-adv = <10>;
};
pins_clk {
pins-clk {
pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
drive-strength = <MTK_DRIVE_8mA>;
mediatek,pull-down-adv = <10>;
@ -693,15 +693,15 @@ pins_clk {
};
};
panel_pins_default: panel_pins_default {
panel_reset {
panel_pins_default: panel-pins-default {
panel-reset {
pinmux = <PINMUX_GPIO45__FUNC_GPIO45>;
output-low;
bias-pull-up;
};
};
pwm0_pin_default: pwm0_pin_default {
pwm0_pin_default: pwm0-pin-default {
pins1 {
pinmux = <PINMUX_GPIO176__FUNC_GPIO176>;
output-high;
@ -713,14 +713,14 @@ pins2 {
};
scp_pins: scp {
pins_scp_uart {
pins-scp-uart {
pinmux = <PINMUX_GPIO110__FUNC_TP_URXD1_AO>,
<PINMUX_GPIO112__FUNC_TP_UTXD1_AO>;
};
};
spi0_pins: spi0 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
<PINMUX_GPIO86__FUNC_GPIO86>,
<PINMUX_GPIO87__FUNC_SPI0_MO>,
@ -730,7 +730,7 @@ pins_spi {
};
spi1_pins: spi1 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
<PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO163__FUNC_SPI1_A_MO>,
@ -740,20 +740,20 @@ pins_spi {
};
spi2_pins: spi2 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
<PINMUX_GPIO1__FUNC_SPI2_MO>,
<PINMUX_GPIO2__FUNC_SPI2_CLK>;
bias-disable;
};
pins_spi_mi {
pins-spi-mi {
pinmux = <PINMUX_GPIO94__FUNC_SPI2_MI>;
mediatek,pull-down-adv = <00>;
};
};
spi3_pins: spi3 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
<PINMUX_GPIO22__FUNC_SPI3_CSB>,
<PINMUX_GPIO23__FUNC_SPI3_MO>,
@ -763,7 +763,7 @@ pins_spi {
};
spi4_pins: spi4 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
<PINMUX_GPIO18__FUNC_SPI4_CSB>,
<PINMUX_GPIO19__FUNC_SPI4_MO>,
@ -773,7 +773,7 @@ pins_spi {
};
spi5_pins: spi5 {
pins_spi {
pins-spi {
pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
<PINMUX_GPIO14__FUNC_SPI5_CSB>,
<PINMUX_GPIO15__FUNC_SPI5_MO>,
@ -783,63 +783,63 @@ pins_spi {
};
uart0_pins_default: uart0-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO95__FUNC_URXD0>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO96__FUNC_UTXD0>;
};
};
uart1_pins_default: uart1-pins-default {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_URXD1>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
uart1_pins_sleep: uart1-pins-sleep {
pins_rx {
pins-rx {
pinmux = <PINMUX_GPIO121__FUNC_GPIO121>;
input-enable;
bias-pull-up;
};
pins_tx {
pins-tx {
pinmux = <PINMUX_GPIO115__FUNC_UTXD1>;
};
pins_rts {
pins-rts {
pinmux = <PINMUX_GPIO47__FUNC_URTS1>;
output-enable;
};
pins_cts {
pins-cts {
pinmux = <PINMUX_GPIO46__FUNC_UCTS1>;
input-enable;
};
};
wifi_pins_pwrseq: wifi-pins-pwrseq {
pins_wifi_enable {
pins-wifi-enable {
pinmux = <PINMUX_GPIO119__FUNC_GPIO119>;
output-low;
};
};
wifi_pins_wakeup: wifi-pins-wakeup {
pins_wifi_wakeup {
pins-wifi-wakeup {
pinmux = <PINMUX_GPIO113__FUNC_GPIO113>;
input-enable;
};

242
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1210,127 +1210,6 @@ thermal: thermal@1100b000 {
nvmem-cell-names = "calibration-data";
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@ -2105,4 +1984,125 @@ larb3: larb@1a002000 {
power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
};
};
thermal_zones: thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
thermal-sensors = <&thermal 0>;
sustainable-power = <5000>;
trips {
threshold: trip-point0 {
temperature = <68000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <80000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu-crit {
temperature = <115000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu1
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu2
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu3
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <3072>;
};
map1 {
trip = <&target>;
cooling-device = <&cpu4
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu5
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu6
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>,
<&cpu7
THERMAL_NO_LIMIT
THERMAL_NO_LIMIT>;
contribution = <1024>;
};
};
};
/* The tzts1 ~ tzts6 don't need to polling */
/* The tzts1 ~ tzts6 don't need to thermal throttle */
tzts1: tzts1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 1>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts2: tzts2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 2>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts3: tzts3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 3>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts4: tzts4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 4>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tzts5: tzts5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 5>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
tztsABB: tztsABB {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 6>;
sustainable-power = <5000>;
trips {};
cooling-maps {};
};
};
};

44
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@ -924,7 +924,8 @@ power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
clocks = <&topckgen CLK_TOP_SENINF>,
<&topckgen CLK_TOP_SENINF1>;
clock-names = "csirx_top0", "csirx_top1";
clock-names = "subsys-csirx-top0",
"subsys-csirx-top1";
#power-domain-cells = <0>;
};
@ -942,7 +943,8 @@ power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
clocks = <&topckgen CLK_TOP_AUDIODSP>,
<&topckgen CLK_TOP_ADSP_BUS>;
clock-names = "audioadsp", "adsp_bus";
clock-names = "audioadsp",
"subsys-adsp-bus";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
@ -975,8 +977,11 @@ power-domain@MT8186_POWER_DOMAIN_DIS {
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "disp", "mdp", "smi_infra", "smi_common",
"smi_gals", "smi_iommu";
clock-names = "disp", "mdp",
"subsys-smi-infra",
"subsys-smi-common",
"subsys-smi-gals",
"subsys-smi-iommu";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
@ -993,15 +998,17 @@ power-domain@MT8186_POWER_DOMAIN_VDEC {
power-domain@MT8186_POWER_DOMAIN_CAM {
reg = <MT8186_POWER_DOMAIN_CAM>;
clocks = <&topckgen CLK_TOP_CAM>,
<&topckgen CLK_TOP_SENINF>,
clocks = <&topckgen CLK_TOP_SENINF>,
<&topckgen CLK_TOP_SENINF1>,
<&topckgen CLK_TOP_SENINF2>,
<&topckgen CLK_TOP_SENINF3>,
<&camsys CLK_CAM2MM_GALS>,
<&topckgen CLK_TOP_CAMTM>,
<&camsys CLK_CAM2MM_GALS>;
clock-names = "cam-top", "cam0", "cam1", "cam2",
"cam3", "cam-tm", "gals";
<&topckgen CLK_TOP_CAM>;
clock-names = "cam0", "cam1", "cam2",
"cam3", "gals",
"subsys-cam-tm",
"subsys-cam-top";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
@ -1020,9 +1027,9 @@ power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
power-domain@MT8186_POWER_DOMAIN_IMG {
reg = <MT8186_POWER_DOMAIN_IMG>;
clocks = <&topckgen CLK_TOP_IMG1>,
<&imgsys1 CLK_IMG1_GALS_IMG1>;
clock-names = "img-top", "gals";
clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
<&topckgen CLK_TOP_IMG1>;
clock-names = "gals", "subsys-img-top";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
@ -1041,8 +1048,11 @@ power-domain@MT8186_POWER_DOMAIN_IPE {
<&ipesys CLK_IPE_LARB20>,
<&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_GALS_IPE>;
clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
"ipe-smi", "ipe-gals";
clock-names = "subsys-ipe-top",
"subsys-ipe-larb0",
"subsys-ipe-larb1",
"subsys-ipe-smi",
"subsys-ipe-gals";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -1061,7 +1071,9 @@ power-domain@MT8186_POWER_DOMAIN_WPE {
clocks = <&topckgen CLK_TOP_WPE>,
<&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
<&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
clock-names = "wpe0", "larb-ck", "larb-pclk";
clock-names = "wpe0",
"subsys-larb-ck",
"subsys-larb-pclk";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -1656,7 +1668,7 @@ efuse: efuse@11cb0000 {
#address-cells = <1>;
#size-cells = <1>;
gpu_speedbin: gpu-speed-bin@59c {
gpu_speedbin: gpu-speedbin@59c {
reg = <0x59c 0x4>;
bits = <0 3>;
};

2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -389,7 +389,7 @@ &i2c7 {
pinctrl-0 = <&i2c7_pins>;
pmic@34 {
#interrupt-cells = <1>;
#interrupt-cells = <2>;
compatible = "mediatek,mt6360";
reg = <0x34>;
interrupt-controller;

6
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -627,6 +627,8 @@ power-domain@MT8195_POWER_DOMAIN_VDEC1 {
power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>;
clock-names = "venc1-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -689,6 +691,8 @@ power-domain@MT8195_POWER_DOMAIN_VDEC2 {
power-domain@MT8195_POWER_DOMAIN_VENC {
reg = <MT8195_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_LARB>;
clock-names = "venc0-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
@ -2665,7 +2669,7 @@ larb20: larb@1b010000 {
reg = <0 0x1b010000 0 0x1000>;
mediatek,larb-id = <20>;
mediatek,smi = <&smi_common_vpp>;
clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
<&vencsys_core1 CLK_VENC_CORE1_GALS>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "apb", "smi", "gals";