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ASoC: rockchip: Reorder clock enable sequence
bui duc phuc <phucduc.bui@gmail.com> says:
This series reorders the runtime resume clock enable sequence in the
Rockchip SPDIF and PDM drivers to enable the bus clock before the
functional controller clock.
It also updates the SPDIF DT binding clock descriptions to match the
actual clock usage in the driver.
Additionally, this v2 adds two new patches addressing issues reported
by the Sashiko AI Review tool regarding regcache sync failure handling
and runtime PM resume status validation.
Testing:
- Patch 1: Verified (dt_binding_check passed).
- Patches 2 to 5: Compile tested only. Please help test if you have
the relevant Rockchip hardware.
Link: https://patch.msgid.link/20260602101608.45137-1-phucduc.bui@gmail.com
This commit is contained in:
commit
4263ed78c5
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@ -45,8 +45,8 @@ properties:
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clocks:
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items:
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- description: clock for SPDIF bus
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- description: clock for SPDIF controller
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- description: clock for SPDIF bus
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clock-names:
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items:
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@ -321,6 +321,7 @@ static int rockchip_pdm_set_fmt(struct snd_soc_dai *cpu_dai,
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{
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struct rk_pdm_dev *pdm = to_info(cpu_dai);
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unsigned int mask = 0, val = 0;
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int ret;
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mask = PDM_CKP_MSK;
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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@ -334,7 +335,10 @@ static int rockchip_pdm_set_fmt(struct snd_soc_dai *cpu_dai,
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return -EINVAL;
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}
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pm_runtime_get_sync(cpu_dai->dev);
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ret = pm_runtime_resume_and_get(cpu_dai->dev);
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if (ret)
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return ret;
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regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, mask, val);
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pm_runtime_put(cpu_dai->dev);
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@ -422,16 +426,16 @@ static int rockchip_pdm_runtime_resume(struct device *dev)
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struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(pdm->clk);
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ret = clk_prepare_enable(pdm->hclk);
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if (ret) {
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dev_err(pdm->dev, "clock enable failed %d\n", ret);
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dev_err(pdm->dev, "hclock enable failed %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(pdm->hclk);
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ret = clk_prepare_enable(pdm->clk);
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if (ret) {
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clk_disable_unprepare(pdm->clk);
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dev_err(pdm->dev, "hclock enable failed %d\n", ret);
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clk_disable_unprepare(pdm->hclk);
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dev_err(pdm->dev, "clock enable failed %d\n", ret);
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return ret;
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}
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@ -76,16 +76,16 @@ static int rk_spdif_runtime_resume(struct device *dev)
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struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(spdif->mclk);
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ret = clk_prepare_enable(spdif->hclk);
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if (ret) {
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dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
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dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(spdif->hclk);
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ret = clk_prepare_enable(spdif->mclk);
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if (ret) {
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clk_disable_unprepare(spdif->mclk);
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dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
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clk_disable_unprepare(spdif->hclk);
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dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
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return ret;
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}
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@ -94,6 +94,7 @@ static int rk_spdif_runtime_resume(struct device *dev)
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ret = regcache_sync(spdif->regmap);
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if (ret) {
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regcache_cache_only(spdif->regmap, true);
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clk_disable_unprepare(spdif->mclk);
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clk_disable_unprepare(spdif->hclk);
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}
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