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This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.18, please pull the following: - Krzysztof fixes a DTC warning for the ARM GIC in bcm2712.dtsi - Ivan adds the pin controller node(s), an additional GPIO controller, the second SDHCI controller node for SDIO Wi-Fi, and the UARTA for Bluetooth to the BCM2712 DTS (Raspberry Pi 5) - Stanimir adds the Ethernet DT node and enables it for the RP1 sister chip - Andrea deletes a number of redundant PCIe DT node enablement, updates a comment to describe the relationship between bcm2712 and RP1 and finally enables the USB controllers with RP1 -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmjBsLIACgkQh9CWnEQH BwTFFBAAzwb6T/eAb1eu2ut8Jn42SzqowKd1YLBkonVCQ55onTAIXaH9IyIsQ/gs tCOc6aTJaVZCjvTl4Qp1dCB/XLEtK2WtCed3Avu5JZLTWRZjjsYFW5dHTbScl4m/ AOoXGj1p9IDHB8LRzdd/5DSh0dIj1Y5npCEti1J9mFoL8zPEIHfEvSa+wXV49i2a 25xZKA8TwQOmfwtxYrLIKO0aEaOLPFGcbqc+9lDCwGzJj3Af5VpB2P6lGTjpLFdG AE3sUvtL6Hfs47XgHn/oRoQFvljuTClEU9tUWq+k6BUz9p6t13833jVwz8I6lZPl 9XoYRvuP3g2hELWRbX63PogePTNZp5Iqn5KG1YLlLigsxrHHN7TQnu2AP6l/R6Ti gm108ZmidXOFbc10ONkOUQv0MX/U8Mi9XW4xXTvDG85UkiftEMXaXcfozlNoWnrB rSwLotqsMVyfR5yu/kuxWODGsRdLteRFTv1T4Bzf2r4p/EbVRp4hcPQyQGAazGXZ gUKqn11FBAdKAEkgH8VpSfBh7Freet3Cgs/ttaTpmG7I0NDPJ4PBegdxMlB6TY9K ThhUv4qEWMXuggZxbgLp1v1tPtbheHN4REX62nYLxYrdaAXREukGFhcjrNZl4CVk E77Vl5sNjOgBJqrgaw2b3Nbs7VMymEdSoTnGrY+RCYlE/SEZ/L8= =1ROS -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIEWMACgkQmmx57+YA GNmhzA/8CjEyy71uETe/H5rPJwL34OR8SH3XNNHle14Ce5qlYS7n9sADz/n8Q4Vi JvDPZcZsH+2Bc7adaw9pvWRzTtnj0bkxPXe1Wp400UX8JLNIDfbRm5BWpIh2Gk2U ET/FqynAr7ppcxu1Py3qnCfFuZrIYrQFYk0nPvOuaYysjtXAIOJbjVdI1JjpqkM1 5LhAsV//0CT7OTfbww4P+Sga+weM0aB+3sZ/7dg8Uf6AXP3nfzwtf9vch5GBvnok rYB6SCKdD9ZVF/SpbF1ruvaCekzemNqVXITrEicCjnzjzUKP/fbxR0IddntQ1cYk ZuUDQ24H39qeXoirDDw8gQ3BFBOH6mOYB2hMCzL/hLMXc5ljevZtfThbPv9v6xmb 9qHVWfeu2yD0JA/dIva1OVTwQMzDSy+v4BfWnOzXxLZemwoL4Ly1o15tdzAsGXb7 BIYVMTe8h+PAvUoYC+yEbMJrf8ZW8knFvMLPBZTL/GVWaAIVLBYiXVkRVFHtSMVN MOGDLroW6iIKVnp/KSeTyeSy4V0gYRDLF8qWXUX2QKLwfJipCAo+dACWzbmA59Ex JjhgQ48lwybJB8P9TePzR1CyTyj2Jf03AvhV6rkULEFz6pQiXbwktgGgfsw9RgI2 g2AhRKLgoUghc2odjfbDFy9z5/WRn5m3Uv7raAUEnOT22TKg9NQ= =4ja6 -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt This pull request contains Broadcom ARM64-based SoCs Device Tree updates for 6.18, please pull the following: - Krzysztof fixes a DTC warning for the ARM GIC in bcm2712.dtsi - Ivan adds the pin controller node(s), an additional GPIO controller, the second SDHCI controller node for SDIO Wi-Fi, and the UARTA for Bluetooth to the BCM2712 DTS (Raspberry Pi 5) - Stanimir adds the Ethernet DT node and enables it for the RP1 sister chip - Andrea deletes a number of redundant PCIe DT node enablement, updates a comment to describe the relationship between bcm2712 and RP1 and finally enables the USB controllers with RP1 * tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: broadcom: Enable USB devicetree entries for Rpi5 arm64: dts: broadcom: rp1: Add USB nodes arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS arm64: dts: broadcom: delete redundant pcie enablement nodes arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5 arm64: dts: rp1: Add ethernet DT node dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller arm64: dts: broadcom: bcm2712: Add UARTA controller node arm64: dts: broadcom: bcm2712: Add second SDHCI controller node arm64: dts: broadcom: bcm2712: Add one more GPIO node arm64: dts: broadcom: bcm2712: Add pin controller nodes arm64: dts: broadcom: bcm2712: Add default GIC address cells Link: https://lore.kernel.org/r/20250910171910.666401-3-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
41d773149b
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@ -61,7 +61,7 @@ properties:
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description: Specifies that controller should use auto CMD12
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allOf:
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- $ref: mmc-controller.yaml#
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- $ref: sdhci-common.yaml#
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- if:
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properties:
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clock-names:
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|
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@ -2,6 +2,7 @@
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "bcm2712.dtsi"
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/ {
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@ -29,6 +30,20 @@ memory@0 {
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reg = <0 0 0 0x28000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_button_default>;
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status = "okay";
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power_button: power-button {
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label = "pwr_button";
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linux,code = <KEY_POWER>;
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gpios = <&gio 20 GPIO_ACTIVE_LOW>;
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debounce-interval = <50>;
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};
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};
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sd_io_1v8_reg: sd-io-1v8-reg {
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compatible = "regulator-gpio";
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regulator-name = "vdd-sd-io";
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@ -51,6 +66,90 @@ sd_vcc_reg: sd-vcc-reg {
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enable-active-high;
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gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>;
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};
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wl_on_reg: wl-on-reg {
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compatible = "regulator-fixed";
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regulator-name = "wl-on-regulator";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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pinctrl-0 = <&wl_on_default>;
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pinctrl-names = "default";
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gpio = <&gio 28 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <150000>;
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enable-active-high;
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};
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};
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&pinctrl {
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bt_shutdown_default: bt-shutdown-default-state {
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function = "gpio";
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pins = "gpio29";
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};
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emmc_sd_default: emmc-sd-default-state {
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pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3";
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bias-pull-up;
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};
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pwr_button_default: pwr-button-default-state {
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function = "gpio";
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pins = "gpio20";
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bias-pull-up;
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};
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sdio2_30_default: sdio2-30-default-state {
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clk-pins {
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function = "sd2";
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pins = "gpio30";
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bias-disable;
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};
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cmd-pins {
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function = "sd2";
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pins = "gpio31";
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bias-pull-up;
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};
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dat-pins {
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function = "sd2";
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pins = "gpio32", "gpio33", "gpio34", "gpio35";
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bias-pull-up;
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};
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};
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uarta_24_default: uarta-24-default-state {
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rts-pins {
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function = "uart0";
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pins = "gpio24";
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bias-disable;
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};
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cts-pins {
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function = "uart0";
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pins = "gpio25";
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bias-pull-up;
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};
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txd-pins {
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function = "uart0";
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pins = "gpio26";
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bias-disable;
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};
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rxd-pins {
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function = "uart0";
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pins = "gpio27";
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bias-pull-up;
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};
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};
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wl_on_default: wl-on-default-state {
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function = "gpio";
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pins = "gpio28";
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};
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};
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&pinctrl_aon {
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emmc_aon_cd_default: emmc-aon-cd-default-state {
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function = "sd_card_g";
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pins = "aon_gpio5";
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bias-pull-up;
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};
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};
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/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector
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@ -62,12 +161,32 @@ &uart10 {
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/* SDIO1 is used to drive the SD card */
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&sdio1 {
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pinctrl-0 = <&emmc_sd_default>, <&emmc_aon_cd_default>;
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pinctrl-names = "default";
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vqmmc-supply = <&sd_io_1v8_reg>;
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vmmc-supply = <&sd_vcc_reg>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-ddr50;
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sd-uhs-sdr104;
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cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>;
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};
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&sdio2 {
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pinctrl-0 = <&sdio2_30_default>;
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pinctrl-names = "default";
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bus-width = <4>;
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vmmc-supply = <&wl_on_reg>;
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sd-uhs-ddr50;
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non-removable;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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wifi: wifi@1 {
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reg = <1>;
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compatible = "brcm,bcm4329-fmac";
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};
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};
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&soc {
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@ -97,6 +216,20 @@ power: power {
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};
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};
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/* uarta communicates with the BT module */
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&uarta {
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uart-has-rtscts;
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pinctrl-0 = <&uarta_24_default &bt_shutdown_default>;
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pinctrl-names = "default";
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status = "okay";
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bluetooth: bluetooth {
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compatible = "brcm,bcm43438-bt";
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max-speed = <3000000>;
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shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>;
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};
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};
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&hvs {
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clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
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clock-names = "core", "disp";
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@ -4,8 +4,14 @@
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* the RP1 driver to load the RP1 dtb overlay at runtime, while
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* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
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* already contains RP1 node, so no overlay is loaded nor needed).
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* This file is not intended to be modified, nodes should be added
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* to the included bcm2712-rpi-5-b-ovl-rp1.dts.
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* This file is intended to host the override nodes for the RP1 peripherals,
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* e.g. to declare the phy of the ethernet interface or the custom pin setup
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* for several RP1 peripherals.
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* This in turn is due to the fact that there's no current generic
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* infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that
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* are not yet defined in the DT since they are loaded at runtime via overlay.
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* All other nodes that do not have anything to do with RP1 should be added
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* to the included bcm2712-rpi-5-b-ovl-rp1.dts instead.
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*/
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/dts-v1/;
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@ -16,10 +22,37 @@ &pcie2 {
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#include "rp1-nexus.dtsi"
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};
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&pcie1 {
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&rp1_eth {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <&phy1>;
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mdio {
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reg = <0x1>;
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reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>;
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reset-delay-us = <5000>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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};
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&rp1_gpio {
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usb_vbus_default_state: usb-vbus-default-state {
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function = "vbus1";
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groups = "vbus1";
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};
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};
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&rp1_usb0 {
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pinctrl-0 = <&usb_vbus_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pcie2 {
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&rp1_usb1 {
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status = "okay";
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};
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@ -38,6 +38,13 @@ clk_emmc2: clk-emmc2 {
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clock-frequency = <200000000>;
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clock-output-names = "emmc2-clock";
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};
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clk_sw_baud: clk-sw-baud {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <96000000>;
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clock-output-names = "sw-baud";
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};
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};
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cpus: cpus {
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@ -243,6 +250,39 @@ uart10: serial@7d001000 {
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status = "disabled";
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};
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pinctrl: pinctrl@7d504100 {
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compatible = "brcm,bcm2712c0-pinctrl";
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reg = <0x7d504100 0x30>;
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};
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gio: gpio@7d508500 {
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compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
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reg = <0x7d508500 0x40>;
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interrupt-parent = <&main_irq>;
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interrupts = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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brcm,gpio-bank-widths = <32 22>;
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};
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uarta: serial@7d50c000 {
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compatible = "brcm,bcm7271-uart";
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reg = <0x7d50c000 0x20>;
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reg-names = "uart";
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clocks = <&clk_sw_baud>;
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clock-names = "sw_baud";
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interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uart";
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status = "disabled";
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};
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pinctrl_aon: pinctrl@7d510700 {
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compatible = "brcm,bcm2712c0-aon-pinctrl";
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reg = <0x7d510700 0x20>;
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};
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interrupt-controller@7d517000 {
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compatible = "brcm,bcm7271-l2-intc";
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reg = <0x7d517000 0x10>;
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@ -263,6 +303,21 @@ gio_aon: gpio@7d517c00 {
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*/
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};
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sdio2: mmc@1100000 {
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compatible = "brcm,bcm2712-sdhci",
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"brcm,sdhci-brcmstb";
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reg = <0x01100000 0x260>,
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<0x01100400 0x200>;
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reg-names = "host", "cfg";
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interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_emmc2>;
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clock-names = "sw_sdio";
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sdhci-caps-mask = <0x0000C000 0x0>;
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sdhci-caps = <0x0 0x0>;
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mmc-ddr-3_3v;
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status = "disabled";
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};
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gicv2: interrupt-controller@7fff9000 {
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compatible = "arm,gic-400";
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reg = <0x7fff9000 0x1000>,
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|
|
@ -270,6 +325,7 @@ gicv2: interrupt-controller@7fff9000 {
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<0x7fffc000 0x2000>,
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<0x7fffe000 0x2000>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <3>;
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||||
};
|
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|
||||
|
|
|
|||
|
|
@ -39,4 +39,48 @@ rp1_gpio: pinctrl@400d0000 {
|
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<1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<2 IRQ_TYPE_LEVEL_HIGH>;
|
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};
|
||||
|
||||
rp1_eth: ethernet@40100000 {
|
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compatible = "raspberrypi,rp1-gem";
|
||||
reg = <0x00 0x40100000 0x0 0x4000>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rp1_clocks RP1_CLK_SYS>,
|
||||
<&rp1_clocks RP1_CLK_SYS>,
|
||||
<&rp1_clocks RP1_CLK_ETH>,
|
||||
<&rp1_clocks RP1_CLK_ETH_TSU>;
|
||||
clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
rp1_usb0: usb@40200000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x00 0x40200000 0x0 0x100000>;
|
||||
interrupts = <31 IRQ_TYPE_EDGE_RISING>;
|
||||
dr_mode = "host";
|
||||
usb3-lpm-capable;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
snps,parkmode-disable-hs-quirk;
|
||||
snps,parkmode-disable-ss-quirk;
|
||||
snps,tx-max-burst = /bits/ 8 <8>;
|
||||
snps,tx-thr-num-pkt = /bits/ 8 <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rp1_usb1: usb@40300000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x00 0x40300000 0x0 0x100000>;
|
||||
interrupts = <36 IRQ_TYPE_EDGE_RISING>;
|
||||
dr_mode = "host";
|
||||
usb3-lpm-capable;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
snps,parkmode-disable-hs-quirk;
|
||||
snps,parkmode-disable-ss-quirk;
|
||||
snps,tx-max-burst = /bits/ 8 <8>;
|
||||
snps,tx-thr-num-pkt = /bits/ 8 <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user