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clk: stm32: fix clock array size for STM32MP21

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STM32MP21_LAST_CLK is used as the number of entries of the onecell
clk_hw array allocated in stm32_rcc_clock_init(), and as the bound of
the clock IDs it can hold. It was wrongly set to CK_SCMI_KER_ETR (112),
which belongs to the SCMI clock ID range, whereas the RCC clock IDs
go up to CK_KER_STM (289).

As a result the array is too small, and registering a clock whose ID
is greater than 111 writes past the end of the allocated clk_hw array
(hws[cfg_clock->id] = hw), and consumers requesting such a clock
get rejected or read out of bounds.

Define STM32MP21_LAST_CLK as CK_KER_STM + 1 so that the array covers
all the RCC clock IDs.

No device tree node uses the STM32MP21 RCC driver yet, so there is no
need to backport this patch to stable kernels.

Fixes: 37ae8501cd ("clk: stm32: introduce clocks for STM32MP21 platform")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://patch.msgid.link/20261012131859.215240-1-gabriel.fernandez@foss.st.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Gabriel Fernandez 2026-10-12 15:18:59 +02:00 committed by Brian Masney
parent bb1d071a54
commit 40e5d379cc
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/stm32/clk-stm32mp21.c
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@ -17,8 +17,8 @@
#include <dt-bindings/clock/st,stm32mp21-rcc.h>
#include <dt-bindings/reset/st,stm32mp21-rcc.h>
/* Max clock binding value */
#define STM32MP21_LAST_CLK CK_SCMI_KER_ETR
/* Number of RCC clock bindings (highest RCC clock ID + 1) */
#define STM32MP21_LAST_CLK (CK_KER_STM + 1)
/* Clock security definition */
#define SECF_NONE -1