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m68knommu: updates and fixes for v7.2

Browse Source 
. update stmark board support
 . clock fixes for m5441x ColdFire
 . base hardware support for DAC block of m5441x ColdFire
 . select legacy gpiolib interface for mcfqspi
 . new defconfigs for more ColdFire based boards
 . unify ColdFire SoC register access
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Merge tag 'm68knommu-for-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu updates from Greg Ungerer:

 - an update and config refresh for the stmark board

 - fixes and preparatory work for supporting the DAC hardware block of
   the m5441x ColdFire SoC

 - forced configuration fix for legacy gpiolib when enabling the mcfqspi
   driver

 - new defconfigs for the M5329EVB, M54418EVB and NETtel boards to give
   better build test coverage For ColdFire parts

 - cleanup to register access code in the core init and setup code for
   ColdFire SoC be consistent, instead of a varied use of
   __raw_readX/__raw_write and straight readX/writeX.

   This is working towards fixing the non-standard endianess of the
   non-MMU m68k readX/writeX functions.

* tag 'm68knommu-for-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (22 commits)
  m68k: stmark2: enable DACs outputs
  m68k: stmark2: add mcf5441x DAC platform devices
  m68k: stmark2: use ioport.h macros for resources
  m68k: mcf5441x: add CCR MISCCR2 bitfields
  m68k: mcf5441x: add CCM registers
  m68k: add DAC modules base addresses
  m68k: mcf5441x: add clock for DAC channel 1
  m68k: mcf5441x: fix clocks numbering
  m68k: coldfire: use ColdFire specifc IO access in SoC code
  m68k: coldfire: use ColdFire specifc IO access in system code
  m68k: coldfire: rename timer register access defines
  m68k: coldfire: use ColdFire specifc IO access in timer code
  m68k: coldfire: use ColdFire specifc IO access in interrupt code
  m68k: coldfire: use ColdFire specific IO access in headers
  m68k: coldfire: create IO access functions for internal registers
  m68k: defconfig: update all ColdFire defconfigs
  m68k: defconfig: add config for SnapGear/NETtel board
  m68k: defconfig: add config for M54418EVB board
  m68k: defconfig: add config for M5329EVB board
  m68k: coldfire: select legacy gpiolib interface for mcfqspi
  ...
This commit is contained in:
Linus Torvalds 2026-06-17 11:34:05 -07:00
commit 407ce27e74
47 changed files with 676 additions and 400 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/m68k/Kconfig.cpu
View File

@ -30,6 +30,7 @@ config COLDFIRE
select CPU_HAS_NO_MULDIV64
select GENERIC_CSUM
select GPIOLIB
select GPIOLIB_LEGACY if SPI_COLDFIRE_QSPI
select HAVE_LEGACY_CLK
select HAVE_PAGE_SIZE_8KB if !MMU

8
arch/m68k/Kconfig.machine
View File

@ -277,16 +277,16 @@ config M5407C3
Support for the Motorola M5407C3 board.
config AMCORE
bool "Sysam AMCORE board support"
bool "Kernelspace AMCORE board support"
depends on M5307
help
Support for the Sysam AMCORE open-hardware generic board.
Support for the Kernelspace AMCORE open-hardware generic board.
config STMARK2
bool "Sysam stmark2 board support"
bool "Kernelspace stmark2 board support"
depends on M5441x
help
Support for the Sysam stmark2 open-hardware generic board.
Support for the Kernelspace stmark2 open-hardware generic board.
config FIREBEE
bool "FireBee board support"

4
arch/m68k/coldfire/amcore.c
View File

@ -1,7 +1,7 @@
/*
* amcore.c -- Support for Sysam AMCORE open board
* amcore.c -- Support for Kernelspace AMCORE open board
*
* (C) Copyright 2016, Angelo Dureghello <angelo@sysam.it>
* (C) Copyright 2026, Angelo Dureghello <angelo@kernel-space.org>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive

8
arch/m68k/coldfire/clk.c
View File

@ -42,12 +42,12 @@ void __clk_init_disabled(struct clk *clk)
static void __clk_enable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR0);
mcf_write8(clk->slot, MCFPM_PPMCR0);
}
static void __clk_disable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR0);
mcf_write8(clk->slot, MCFPM_PPMSR0);
}
struct clk_ops clk_ops0 = {
@ -58,12 +58,12 @@ struct clk_ops clk_ops0 = {
#ifdef MCFPM_PPMCR1
static void __clk_enable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR1);
mcf_write8(clk->slot, MCFPM_PPMCR1);
}
static void __clk_disable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR1);
mcf_write8(clk->slot, MCFPM_PPMSR1);
}
struct clk_ops clk_ops1 = {

8
arch/m68k/coldfire/device.c
View File

@ -669,13 +669,13 @@ static void __init mcf_uart_set_irq(void)
{
#ifdef MCFUART_UIVR
/* UART0 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
mcf_write8(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
mcf_write8(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
/* UART1 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
mcf_write8(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
mcf_write8(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
#endif
}

12
arch/m68k/coldfire/dma_timer.c
View File

@ -37,7 +37,7 @@
static u64 cf_dt_get_cycles(struct clocksource *cs)
{
return __raw_readl(DTCN0);
return mcf_read32(DTCN0);
}
static struct clocksource clocksource_cf_dt = {
@ -56,10 +56,10 @@ static int __init init_cf_dt_clocksource(void)
* get a ~213 ns resolution and the 32bit register will overflow almost
* every 15 minutes.
*/
__raw_writeb(0x00, DTXMR0);
__raw_writeb(0x00, DTER0);
__raw_writel(0x00000000, DTRR0);
__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
mcf_write8(0x00, DTXMR0);
mcf_write8(0x00, DTER0);
mcf_write32(0x00000000, DTRR0);
mcf_write16(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
}
@ -76,7 +76,7 @@ static unsigned long long cycles2ns(unsigned long cycl)
unsigned long long sched_clock(void)
{
unsigned long cycl = __raw_readl(DTCN0);
unsigned long cycl = mcf_read32(DTCN0);
return cycles2ns(cycl);
}

30
arch/m68k/coldfire/intc-2.c
View File

@ -61,8 +61,8 @@ static void intc_irq_mask(struct irq_data *d)
imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
imrbit = 0x1 << (irq & 0x1f);
val = __raw_readl(imraddr);
__raw_writel(val | imrbit, imraddr);
val = mcf_read32(imraddr);
mcf_write32(val | imrbit, imraddr);
}
static void intc_irq_unmask(struct irq_data *d)
@ -83,8 +83,8 @@ static void intc_irq_unmask(struct irq_data *d)
if ((irq & 0x20) == 0)
imrbit |= 0x1;
val = __raw_readl(imraddr);
__raw_writel(val & ~imrbit, imraddr);
val = mcf_read32(imraddr);
mcf_write32(val & ~imrbit, imraddr);
}
/*
@ -97,7 +97,7 @@ static void intc_irq_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
__raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
mcf_write8(0x1 << (irq - EINT0), MCFEPORT_EPFR);
}
/*
@ -120,8 +120,8 @@ static unsigned int intc_irq_startup(struct irq_data *d)
icraddr = MCFICM_INTC0;
#endif
icraddr += MCFINTC_ICR0 + (irq & 0x3f);
if (__raw_readb(icraddr) == 0)
__raw_writeb(intc_intpri--, icraddr);
if (mcf_read8(icraddr) == 0)
mcf_write8(intc_intpri--, icraddr);
irq = d->irq;
if ((irq >= EINT1) && (irq <= EINT7)) {
@ -130,12 +130,12 @@ static unsigned int intc_irq_startup(struct irq_data *d)
irq -= EINT0;
/* Set EPORT line as input */
v = __raw_readb(MCFEPORT_EPDDR);
__raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
v = mcf_read8(MCFEPORT_EPDDR);
mcf_write8(v & ~(0x1 << irq), MCFEPORT_EPDDR);
/* Set EPORT line as interrupt source */
v = __raw_readb(MCFEPORT_EPIER);
__raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
v = mcf_read8(MCFEPORT_EPIER);
mcf_write8(v | (0x1 << irq), MCFEPORT_EPIER);
}
intc_irq_unmask(d);
@ -167,9 +167,9 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
irq_set_handler(irq, handle_edge_irq);
irq -= EINT0;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = mcf_read16(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
__raw_writew(pa, MCFEPORT_EPPAR);
mcf_write16(pa, MCFEPORT_EPPAR);
return 0;
}
@ -195,9 +195,9 @@ void __init init_IRQ(void)
int irq;
/* Mask all interrupt sources */
__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
mcf_write32(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
#ifdef MCFICM_INTC1
__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
mcf_write32(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
#endif
for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {

10
arch/m68k/coldfire/intc-5249.c
View File

@ -20,22 +20,22 @@
static void intc2_irq_gpio_mask(struct irq_data *d)
{
u32 imr;
imr = readl(MCFSIM2_GPIOINTENABLE);
imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
writel(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_unmask(struct irq_data *d)
{
u32 imr;
imr = readl(MCFSIM2_GPIOINTENABLE);
imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
writel(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_ack(struct irq_data *d)
{
writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
mcf_write32(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
}
static struct irq_chip intc2_irq_gpio_chip = {

12
arch/m68k/coldfire/intc-525x.c
View File

@ -20,7 +20,7 @@
static void intc2_irq_gpio_mask(struct irq_data *d)
{
u32 imr = readl(MCFSIM2_GPIOINTENABLE);
u32 imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
u32 type = irqd_get_trigger_type(d);
int irq = d->irq - MCF_IRQ_GPIO0;
@ -28,12 +28,12 @@ static void intc2_irq_gpio_mask(struct irq_data *d)
imr &= ~(0x001 << irq);
if (type & IRQ_TYPE_EDGE_FALLING)
imr &= ~(0x100 << irq);
writel(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_unmask(struct irq_data *d)
{
u32 imr = readl(MCFSIM2_GPIOINTENABLE);
u32 imr = mcf_read32(MCFSIM2_GPIOINTENABLE);
u32 type = irqd_get_trigger_type(d);
int irq = d->irq - MCF_IRQ_GPIO0;
@ -41,7 +41,7 @@ static void intc2_irq_gpio_unmask(struct irq_data *d)
imr |= (0x001 << irq);
if (type & IRQ_TYPE_EDGE_FALLING)
imr |= (0x100 << irq);
writel(imr, MCFSIM2_GPIOINTENABLE);
mcf_write32(imr, MCFSIM2_GPIOINTENABLE);
}
static void intc2_irq_gpio_ack(struct irq_data *d)
@ -54,7 +54,7 @@ static void intc2_irq_gpio_ack(struct irq_data *d)
imr |= (0x001 << irq);
if (type & IRQ_TYPE_EDGE_FALLING)
imr |= (0x100 << irq);
writel(imr, MCFSIM2_GPIOINTCLEAR);
mcf_write32(imr, MCFSIM2_GPIOINTCLEAR);
}
static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
@ -77,7 +77,7 @@ static int __init mcf_intc2_init(void)
int irq;
/* set the interrupt base for the second interrupt controller */
writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
mcf_write32(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
/* GPIO interrupt sources */
for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {

20
arch/m68k/coldfire/intc-5272.c
View File

@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
u32 v;
irq -= MCFINT_VECBASE;
v = 0x8 << intc_irqmap[irq].index;
writel(v, intc_irqmap[irq].icr);
mcf_write32(v, intc_irqmap[irq].icr);
}
}
@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
u32 v;
irq -= MCFINT_VECBASE;
v = 0xd << intc_irqmap[irq].index;
writel(v, intc_irqmap[irq].icr);
mcf_write32(v, intc_irqmap[irq].icr);
}
}
@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = readl(intc_irqmap[irq].icr);
v = mcf_read32(intc_irqmap[irq].icr);
v &= (0x7 << intc_irqmap[irq].index);
v |= (0x8 << intc_irqmap[irq].index);
writel(v, intc_irqmap[irq].icr);
mcf_write32(v, intc_irqmap[irq].icr);
}
}
}
@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = readl(MCFSIM_PITR);
v = mcf_read32(MCFSIM_PITR);
if (type == IRQ_TYPE_EDGE_FALLING)
v &= ~(0x1 << (32 - irq));
else
v |= (0x1 << (32 - irq));
writel(v, MCFSIM_PITR);
mcf_write32(v, MCFSIM_PITR);
}
}
return 0;
@ -163,10 +163,10 @@ void __init init_IRQ(void)
int irq, edge;
/* Mask all interrupt sources */
writel(0x88888888, MCFSIM_ICR1);
writel(0x88888888, MCFSIM_ICR2);
writel(0x88888888, MCFSIM_ICR3);
writel(0x88888888, MCFSIM_ICR4);
mcf_write32(0x88888888, MCFSIM_ICR1);
mcf_write32(0x88888888, MCFSIM_ICR2);
mcf_write32(0x88888888, MCFSIM_ICR3);
mcf_write32(0x88888888, MCFSIM_ICR4);
for (irq = 0; (irq < NR_IRQS); irq++) {
irq_set_chip(irq, &intc_irq_chip);

38
arch/m68k/coldfire/intc-simr.c
View File

@ -69,11 +69,11 @@ static void intc_irq_mask(struct irq_data *d)
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC2_SIMR && (irq > 127))
__raw_writeb(irq - 128, MCFINTC2_SIMR);
mcf_write8(irq - 128, MCFINTC2_SIMR);
else if (MCFINTC1_SIMR && (irq > 63))
__raw_writeb(irq - 64, MCFINTC1_SIMR);
mcf_write8(irq - 64, MCFINTC1_SIMR);
else
__raw_writeb(irq, MCFINTC0_SIMR);
mcf_write8(irq, MCFINTC0_SIMR);
}
static void intc_irq_unmask(struct irq_data *d)
@ -81,18 +81,18 @@ static void intc_irq_unmask(struct irq_data *d)
unsigned int irq = d->irq - MCFINT_VECBASE;
if (MCFINTC2_CIMR && (irq > 127))
__raw_writeb(irq - 128, MCFINTC2_CIMR);
mcf_write8(irq - 128, MCFINTC2_CIMR);
else if (MCFINTC1_CIMR && (irq > 63))
__raw_writeb(irq - 64, MCFINTC1_CIMR);
mcf_write8(irq - 64, MCFINTC1_CIMR);
else
__raw_writeb(irq, MCFINTC0_CIMR);
mcf_write8(irq, MCFINTC0_CIMR);
}
static void intc_irq_ack(struct irq_data *d)
{
unsigned int ebit = irq2ebit(d->irq);
__raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
mcf_write8(0x1 << ebit, MCFEPORT_EPFR);
}
static unsigned int intc_irq_startup(struct irq_data *d)
@ -105,22 +105,22 @@ static unsigned int intc_irq_startup(struct irq_data *d)
#if defined(MCFEPORT_EPDDR)
/* Set EPORT line as input */
v = __raw_readb(MCFEPORT_EPDDR);
__raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
v = mcf_read8(MCFEPORT_EPDDR);
mcf_write8(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
#endif
/* Set EPORT line as interrupt source */
v = __raw_readb(MCFEPORT_EPIER);
__raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
v = mcf_read8(MCFEPORT_EPIER);
mcf_write8(v | (0x1 << ebit), MCFEPORT_EPIER);
}
irq -= MCFINT_VECBASE;
if (MCFINTC2_ICR0 && (irq > 127))
__raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
mcf_write8(5, MCFINTC2_ICR0 + irq - 128);
else if (MCFINTC1_ICR0 && (irq > 63))
__raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
mcf_write8(5, MCFINTC1_ICR0 + irq - 64);
else
__raw_writeb(5, MCFINTC0_ICR0 + irq);
mcf_write8(5, MCFINTC0_ICR0 + irq);
intc_irq_unmask(d);
return 0;
@ -151,9 +151,9 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
irq_set_handler(irq, handle_edge_irq);
ebit = irq2ebit(irq) * 2;
pa = __raw_readw(MCFEPORT_EPPAR);
pa = mcf_read16(MCFEPORT_EPPAR);
pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
__raw_writew(pa, MCFEPORT_EPPAR);
mcf_write16(pa, MCFEPORT_EPPAR);
return 0;
}
@ -179,11 +179,11 @@ void __init init_IRQ(void)
int irq, eirq;
/* Mask all interrupt sources */
__raw_writeb(0xff, MCFINTC0_SIMR);
mcf_write8(0xff, MCFINTC0_SIMR);
if (MCFINTC1_SIMR)
__raw_writeb(0xff, MCFINTC1_SIMR);
mcf_write8(0xff, MCFINTC1_SIMR);
if (MCFINTC2_SIMR)
__raw_writeb(0xff, MCFINTC2_SIMR);
mcf_write8(0xff, MCFINTC2_SIMR);
eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
(MCFINTC2_ICR0 ? 64 : 0);

28
arch/m68k/coldfire/intc.c
View File

@ -45,23 +45,23 @@ unsigned char mcf_irq2imr[NR_IRQS];
void mcf_setimr(int index)
{
u16 imr;
imr = __raw_readw(MCFSIM_IMR);
__raw_writew(imr | (0x1 << index), MCFSIM_IMR);
imr = mcf_read16(MCFSIM_IMR);
mcf_write16(imr | (0x1 << index), MCFSIM_IMR);
}
void mcf_clrimr(int index)
{
u16 imr;
imr = __raw_readw(MCFSIM_IMR);
__raw_writew(imr & ~(0x1 << index), MCFSIM_IMR);
imr = mcf_read16(MCFSIM_IMR);
mcf_write16(imr & ~(0x1 << index), MCFSIM_IMR);
}
static void mcf_maskimr(unsigned int mask)
{
u16 imr;
imr = __raw_readw(MCFSIM_IMR);
imr = mcf_read16(MCFSIM_IMR);
imr |= mask;
__raw_writew(imr, MCFSIM_IMR);
mcf_write16(imr, MCFSIM_IMR);
}
#else
@ -69,23 +69,23 @@ static void mcf_maskimr(unsigned int mask)
void mcf_setimr(int index)
{
u32 imr;
imr = __raw_readl(MCFSIM_IMR);
__raw_writel(imr | (0x1 << index), MCFSIM_IMR);
imr = mcf_read32(MCFSIM_IMR);
mcf_write32(imr | (0x1 << index), MCFSIM_IMR);
}
void mcf_clrimr(int index)
{
u32 imr;
imr = __raw_readl(MCFSIM_IMR);
__raw_writel(imr & ~(0x1 << index), MCFSIM_IMR);
imr = mcf_read32(MCFSIM_IMR);
mcf_write32(imr & ~(0x1 << index), MCFSIM_IMR);
}
static void mcf_maskimr(unsigned int mask)
{
u32 imr;
imr = __raw_readl(MCFSIM_IMR);
imr = mcf_read32(MCFSIM_IMR);
imr |= mask;
__raw_writel(imr, MCFSIM_IMR);
mcf_write32(imr, MCFSIM_IMR);
}
#endif
@ -104,9 +104,9 @@ void mcf_autovector(int irq)
#ifdef MCFSIM_AVR
if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
u8 avec;
avec = __raw_readb(MCFSIM_AVR);
avec = mcf_read8(MCFSIM_AVR);
avec |= (0x1 << (irq - EIRQ1 + 1));
__raw_writeb(avec, MCFSIM_AVR);
mcf_write8(avec, MCFSIM_AVR);
}
#endif
}

2
arch/m68k/coldfire/m5206.c
View File

@ -40,7 +40,7 @@ static struct clk_lookup m5206_clk_lookup[] = {
static void __init m5206_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */

26
arch/m68k/coldfire/m520x.c
View File

@ -125,11 +125,11 @@ static void __init m520x_qspi_init(void)
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
u16 par;
/* setup Port QS for QSPI with gpio CS control */
writeb(0x3f, MCF_GPIO_PAR_QSPI);
mcf_write8(0x3f, MCF_GPIO_PAR_QSPI);
/* make U1CTS and U2RTS gpio for cs_control */
par = readw(MCF_GPIO_PAR_UART);
par = mcf_read16(MCF_GPIO_PAR_UART);
par &= 0x00ff;
writew(par, MCF_GPIO_PAR_UART);
mcf_write16(par, MCF_GPIO_PAR_UART);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
@ -142,9 +142,9 @@ static void __init m520x_i2c_init(void)
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCF_GPIO_PAR_FECI2C);
par = mcf_read8(MCF_GPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCF_GPIO_PAR_FECI2C);
mcf_write8(par, MCF_GPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@ -156,17 +156,17 @@ static void __init m520x_uarts_init(void)
u8 par2;
/* UART0 and UART1 GPIO pin setup */
par = readw(MCF_GPIO_PAR_UART);
par = mcf_read16(MCF_GPIO_PAR_UART);
par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
writew(par, MCF_GPIO_PAR_UART);
mcf_write16(par, MCF_GPIO_PAR_UART);
/* UART1 GPIO pin setup */
par2 = readb(MCF_GPIO_PAR_FECI2C);
par2 = mcf_read8(MCF_GPIO_PAR_FECI2C);
par2 &= ~0x0F;
par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
writeb(par2, MCF_GPIO_PAR_FECI2C);
mcf_write8(par2, MCF_GPIO_PAR_FECI2C);
}
/***************************************************************************/
@ -176,11 +176,11 @@ static void __init m520x_fec_init(void)
u8 v;
/* Set multi-function pins to ethernet mode */
v = readb(MCF_GPIO_PAR_FEC);
writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
v = mcf_read8(MCF_GPIO_PAR_FEC);
mcf_write8(v | 0xf0, MCF_GPIO_PAR_FEC);
v = readb(MCF_GPIO_PAR_FECI2C);
writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
v = mcf_read8(MCF_GPIO_PAR_FECI2C);
mcf_write8(v | 0x0f, MCF_GPIO_PAR_FECI2C);
}
/***************************************************************************/

12
arch/m68k/coldfire/m523x.c
View File

@ -51,11 +51,11 @@ static void __init m523x_qspi_init(void)
u16 par;
/* setup QSPS pins for QSPI with gpio CS control */
writeb(0x1f, MCFGPIO_PAR_QSPI);
mcf_write8(0x1f, MCFGPIO_PAR_QSPI);
/* and CS2 & CS3 as gpio */
par = readw(MCFGPIO_PAR_TIMER);
par = mcf_read16(MCFGPIO_PAR_TIMER);
par &= 0x3f3f;
writew(par, MCFGPIO_PAR_TIMER);
mcf_write16(par, MCFGPIO_PAR_TIMER);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
@ -68,9 +68,9 @@ static void __init m523x_i2c_init(void)
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par = mcf_read8(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
mcf_write8(par, MCFGPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@ -79,7 +79,7 @@ static void __init m523x_i2c_init(void)
static void __init m523x_fec_init(void)
{
/* Set multi-function pins to ethernet use */
writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
mcf_write8(read8(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
}
/***************************************************************************/

16
arch/m68k/coldfire/m5249.c
View File

@ -75,7 +75,7 @@ static void __init m5249_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
@ -89,15 +89,15 @@ static void __init m5249_i2c_init(void)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r = mcf_read32(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
mcf_write32(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* CONFIG_I2C_IMX */
}
@ -110,11 +110,11 @@ static void __init m5249_smc91x_init(void)
u32 gpio;
/* Set the GPIO line as interrupt source for smc91x device */
gpio = readl(MCFSIM2_GPIOINTENABLE);
writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
gpio = mcf_read32(MCFSIM2_GPIOINTENABLE);
mcf_write32(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
gpio = readl(MCFINTC2_INTPRI5);
writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
gpio = mcf_read32(MCFINTC2_INTPRI5);
mcf_write32(gpio | 0x04000000, MCFINTC2_INTPRI5);
}
#endif /* CONFIG_M5249C3 */

12
arch/m68k/coldfire/m525x.c
View File

@ -44,12 +44,12 @@ static void __init m525x_qspi_init(void)
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* set the GPIO function for the qspi cs gpios */
/* FIXME: replace with pinmux/pinctl support */
u32 f = readl(MCFSIM2_GPIOFUNC);
u32 f = mcf_read32(MCFSIM2_GPIOFUNC);
f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
writel(f, MCFSIM2_GPIOFUNC);
mcf_write32(f, MCFSIM2_GPIOFUNC);
/* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
@ -61,15 +61,15 @@ static void __init m525x_i2c_init(void)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r = mcf_read32(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
mcf_write32(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}

16
arch/m68k/coldfire/m5272.c
View File

@ -55,13 +55,13 @@ static void __init m5272_uarts_init(void)
u32 v;
/* Enable the output lines for the serial ports */
v = readl(MCFSIM_PBCNT);
v = mcf_read32(MCFSIM_PBCNT);
v = (v & ~0x000000ff) | 0x00000055;
writel(v, MCFSIM_PBCNT);
mcf_write32(v, MCFSIM_PBCNT);
v = readl(MCFSIM_PDCNT);
v = mcf_read32(MCFSIM_PDCNT);
v = (v & ~0x000003fc) | 0x000002a8;
writel(v, MCFSIM_PDCNT);
mcf_write32(v, MCFSIM_PDCNT);
}
/***************************************************************************/
@ -70,9 +70,9 @@ static void m5272_cpu_reset(void)
{
local_irq_disable();
/* Set watchdog to reset, and enabled */
__raw_writew(0, MCFSIM_WIRR);
__raw_writew(1, MCFSIM_WRRR);
__raw_writew(0, MCFSIM_WCR);
mcf_write16(0, MCFSIM_WIRR);
mcf_write16(1, MCFSIM_WRRR);
mcf_write16(0, MCFSIM_WCR);
for (;;)
/* wait for watchdog to timeout */;
}
@ -83,7 +83,7 @@ void __init config_BSP(char *commandp, int size)
{
#if defined (CONFIG_MOD5272)
/* Set base of device vectors to be 64 */
writeb(0x40, MCFSIM_PIVR);
mcf_write8(0x40, MCFSIM_PIVR);
#endif
#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)

40
arch/m68k/coldfire/m527x.c
View File

@ -54,14 +54,14 @@ static void __init m527x_qspi_init(void)
u16 par;
/* setup QSPS pins for QSPI with gpio CS control */
writeb(0x1f, MCFGPIO_PAR_QSPI);
mcf_write8(0x1f, MCFGPIO_PAR_QSPI);
/* and CS2 & CS3 as gpio */
par = readw(MCFGPIO_PAR_TIMER);
par = mcf_read16(MCFGPIO_PAR_TIMER);
par &= 0x3f3f;
writew(par, MCFGPIO_PAR_TIMER);
mcf_write16(par, MCFGPIO_PAR_TIMER);
#elif defined(CONFIG_M5275)
/* setup QSPS pins for QSPI with gpio CS control */
writew(0x003e, MCFGPIO_PAR_QSPI);
mcf_write16(0x003e, MCFGPIO_PAR_QSPI);
#endif
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
@ -76,17 +76,17 @@ static void __init m527x_i2c_init(void)
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par = mcf_read8(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
mcf_write8(par, MCFGPIO_PAR_FECI2C);
#elif defined(CONFIG_M5275)
u16 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readw(MCFGPIO_PAR_FECI2C);
par = mcf_read16(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writew(par, MCFGPIO_PAR_FECI2C);
mcf_write16(par, MCFGPIO_PAR_FECI2C);
#endif
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@ -100,9 +100,9 @@ static void __init m527x_uarts_init(void)
/*
* External Pin Mask Setting & Enable External Pin for Interface
*/
sepmask = readw(MCFGPIO_PAR_UART);
sepmask = mcf_read16(MCFGPIO_PAR_UART);
sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
writew(sepmask, MCFGPIO_PAR_UART);
mcf_write16(sepmask, MCFGPIO_PAR_UART);
}
/***************************************************************************/
@ -113,21 +113,21 @@ static void __init m527x_fec_init(void)
/* Set multi-function pins to ethernet mode for fec0 */
#if defined(CONFIG_M5271)
v = readb(MCFGPIO_PAR_FECI2C);
writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
v = mcf_read8(MCFGPIO_PAR_FECI2C);
mcf_write8(v | 0xf0, MCFGPIO_PAR_FECI2C);
#else
u16 par;
par = readw(MCFGPIO_PAR_FECI2C);
writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC0HL);
writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
par = mcf_read16(MCFGPIO_PAR_FECI2C);
mcf_write16(par | 0xf00, MCFGPIO_PAR_FECI2C);
v = mcf_read8(MCFGPIO_PAR_FEC0HL);
mcf_write8(v | 0xc0, MCFGPIO_PAR_FEC0HL);
/* Set multi-function pins to ethernet mode for fec1 */
par = readw(MCFGPIO_PAR_FECI2C);
writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC1HL);
writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
par = mcf_read16(MCFGPIO_PAR_FECI2C);
mcf_write16(par | 0xa0, MCFGPIO_PAR_FECI2C);
v = mcf_read8(MCFGPIO_PAR_FEC1HL);
mcf_write8(v | 0xc0, MCFGPIO_PAR_FEC1HL);
#endif
}

28
arch/m68k/coldfire/m528x.c
View File

@ -51,7 +51,7 @@ static void __init m528x_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* setup Port QS for QSPI with gpio CS control */
__raw_writeb(0x07, MCFGPIO_PQSPAR);
mcf_write8(0x07, MCFGPIO_PQSPAR);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
@ -64,9 +64,9 @@ static void __init m528x_i2c_init(void)
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
paspar = readw(MCFGPIO_PASPAR);
paspar = mcf_read16(MCFGPIO_PASPAR);
paspar |= 0xF;
writew(paspar, MCFGPIO_PASPAR);
mcf_write16(paspar, MCFGPIO_PASPAR);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@ -77,9 +77,9 @@ static void __init m528x_uarts_init(void)
u8 port;
/* make sure PUAPAR is set for UART0 and UART1 */
port = readb(MCFGPIO_PUAPAR);
port = mcf_read8(MCFGPIO_PUAPAR);
port |= 0x03 | (0x03 << 2);
writeb(port, MCFGPIO_PUAPAR);
mcf_write8(port, MCFGPIO_PUAPAR);
}
/***************************************************************************/
@ -89,9 +89,9 @@ static void __init m528x_fec_init(void)
u16 v16;
/* Set multi-function pins to ethernet mode for fec0 */
v16 = readw(MCFGPIO_PASPAR);
writew(v16 | 0xf00, MCFGPIO_PASPAR);
writeb(0xc0, MCFGPIO_PEHLPAR);
v16 = mcf_read16(MCFGPIO_PASPAR);
mcf_write16(v16 | 0xf00, MCFGPIO_PASPAR);
mcf_write8(0xc0, MCFGPIO_PEHLPAR);
}
/***************************************************************************/
@ -99,8 +99,8 @@ static void __init m528x_fec_init(void)
#ifdef CONFIG_WILDFIRE
void wildfire_halt(void)
{
writeb(0, 0x30000007);
writeb(0x2, 0x30000007);
mcf_write8(0, 0x30000007);
mcf_write8(0x2, 0x30000007);
}
#endif
@ -110,14 +110,14 @@ void wildfiremod_halt(void)
printk(KERN_INFO "WildFireMod hibernating...\n");
/* Set portE.5 to Digital IO */
writew(readw(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
mcf_write16(read16(MCFGPIO_PEPAR) & ~(1 << (5 * 2)), MCFGPIO_PEPAR);
/* Make portE.5 an output */
writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
mcf_write8(read8(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E);
/* Now toggle portE.5 from low to high */
writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
mcf_write8(read8(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E);
mcf_write8(read8(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E);
printk(KERN_EMERG "Failed to hibernate. Halting!\n");
}

2
arch/m68k/coldfire/m5307.c
View File

@ -49,7 +49,7 @@ static struct clk_lookup m5307_clk_lookup[] = {
static void __init m5307_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */

122
arch/m68k/coldfire/m53xx.c
View File

@ -166,7 +166,7 @@ static void __init m53xx_qspi_init(void)
{
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
/* setup QSPS pins for QSPI with gpio CS control */
writew(0x01f0, MCFGPIO_PAR_QSPI);
mcf_write16(0x01f0, MCFGPIO_PAR_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
@ -177,9 +177,9 @@ static void __init m53xx_i2c_init(void)
#if IS_ENABLED(CONFIG_I2C_IMX)
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
u8 r = readb(MCFGPIO_PAR_FECI2C);
u8 r = mcf_read8(MCFGPIO_PAR_FECI2C);
r |= 0x0f;
writeb(r, MCFGPIO_PAR_FECI2C);
mcf_write8(r, MCFGPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@ -188,7 +188,7 @@ static void __init m53xx_i2c_init(void)
static void __init m53xx_uarts_init(void)
{
/* UART GPIO initialization */
writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
mcf_write16(mcf_read16(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
}
/***************************************************************************/
@ -198,14 +198,14 @@ static void __init m53xx_fec_init(void)
u8 v;
/* Set multi-function pins to ethernet mode for fec0 */
v = readb(MCFGPIO_PAR_FECI2C);
v = mcf_read8(MCFGPIO_PAR_FECI2C);
v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
writeb(v, MCFGPIO_PAR_FECI2C);
mcf_write8(v, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC);
v = mcf_read8(MCFGPIO_PAR_FEC);
v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
writeb(v, MCFGPIO_PAR_FEC);
mcf_write8(v, MCFGPIO_PAR_FEC);
}
/***************************************************************************/
@ -305,7 +305,7 @@ asmlinkage void __init sysinit(void)
void wtm_init(void)
{
/* Disable watchdog timer */
writew(0, MCF_WTM_WCR);
mcf_write16(0, MCF_WTM_WCR);
}
#define MCF_SCM_BCR_GBW (0x00000100)
@ -314,53 +314,53 @@ void wtm_init(void)
void scm_init(void)
{
/* All masters are trusted */
writel(0x77777777, MCF_SCM_MPR);
mcf_write32(0x77777777, MCF_SCM_MPR);
/* Allow supervisor/user, read/write, and trusted/untrusted
access to all slaves */
writel(0, MCF_SCM_PACRA);
writel(0, MCF_SCM_PACRB);
writel(0, MCF_SCM_PACRC);
writel(0, MCF_SCM_PACRD);
writel(0, MCF_SCM_PACRE);
writel(0, MCF_SCM_PACRF);
mcf_write32(0, MCF_SCM_PACRA);
mcf_write32(0, MCF_SCM_PACRB);
mcf_write32(0, MCF_SCM_PACRC);
mcf_write32(0, MCF_SCM_PACRD);
mcf_write32(0, MCF_SCM_PACRE);
mcf_write32(0, MCF_SCM_PACRF);
/* Enable bursts */
writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
mcf_write32(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
}
void fbcs_init(void)
{
writeb(0x3E, MCFGPIO_PAR_CS);
mcf_write8(0x3E, MCFGPIO_PAR_CS);
/* Latch chip select */
writel(0x10080000, MCF_FBCS1_CSAR);
mcf_write32(0x10080000, MCF_FBCS1_CSAR);
writel(0x002A3780, MCF_FBCS1_CSCR);
writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
mcf_write32(0x002A3780, MCF_FBCS1_CSCR);
mcf_write32(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Initialize latch to drive signals to inactive states */
writew(0xffff, 0x10080000);
mcf_write16(0xffff, 0x10080000);
/* External SRAM */
writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
writel(MCF_FBCS_CSCR_PS_16 |
mcf_write32(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
mcf_write32(MCF_FBCS_CSCR_PS_16 |
MCF_FBCS_CSCR_AA |
MCF_FBCS_CSCR_SBM |
MCF_FBCS_CSCR_WS(1),
MCF_FBCS1_CSCR);
writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
mcf_write32(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
/* Boot Flash connected to FBCS0 */
writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
writel(MCF_FBCS_CSCR_PS_16 |
mcf_write32(FLASH_ADDRESS, MCF_FBCS0_CSAR);
mcf_write32(MCF_FBCS_CSCR_PS_16 |
MCF_FBCS_CSCR_BEM |
MCF_FBCS_CSCR_AA |
MCF_FBCS_CSCR_SBM |
MCF_FBCS_CSCR_WS(7),
MCF_FBCS0_CSCR);
writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
mcf_write32(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
}
void sdramc_init(void)
@ -369,18 +369,18 @@ void sdramc_init(void)
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
if (!(mcf_read32(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
/* SDRAM chip select initialization */
/* Initialize SDRAM chip select */
writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
mcf_write32(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
MCF_SDRAMC_SDCS0);
/*
* Basic configuration and initialization
*/
writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
mcf_write32(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
@ -388,7 +388,7 @@ void sdramc_init(void)
MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
MCF_SDRAMC_SDCFG1_WTLAT(3),
MCF_SDRAMC_SDCFG1);
writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
mcf_write32(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
@ -398,7 +398,7 @@ void sdramc_init(void)
/*
* Precharge and enable write to SDMR
*/
writel(MCF_SDRAMC_SDCR_MODE_EN |
mcf_write32(MCF_SDRAMC_SDCR_MODE_EN |
MCF_SDRAMC_SDCR_CKE |
MCF_SDRAMC_SDCR_DDR |
MCF_SDRAMC_SDCR_MUX(1) |
@ -410,7 +410,7 @@ void sdramc_init(void)
/*
* Write extended mode register
*/
writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
mcf_write32(MCF_SDRAMC_SDMR_BNKAD_LEMR |
MCF_SDRAMC_SDMR_AD(0x0) |
MCF_SDRAMC_SDMR_CMD,
MCF_SDRAMC_SDMR);
@ -418,7 +418,7 @@ void sdramc_init(void)
/*
* Write mode register and reset DLL
*/
writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
mcf_write32(MCF_SDRAMC_SDMR_BNKAD_LMR |
MCF_SDRAMC_SDMR_AD(0x163) |
MCF_SDRAMC_SDMR_CMD,
MCF_SDRAMC_SDMR);
@ -426,18 +426,18 @@ void sdramc_init(void)
/*
* Execute a PALL command
*/
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
/*
* Perform two REF cycles
*/
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
/*
* Write mode register and clear reset DLL
*/
writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
mcf_write32(MCF_SDRAMC_SDMR_BNKAD_LMR |
MCF_SDRAMC_SDMR_AD(0x063) |
MCF_SDRAMC_SDMR_CMD,
MCF_SDRAMC_SDMR);
@ -445,9 +445,9 @@ void sdramc_init(void)
/*
* Enable auto refresh and lock SDMR
*/
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
MCF_SDRAMC_SDCR);
writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
mcf_write32(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
MCF_SDRAMC_SDCR);
}
}
@ -455,16 +455,16 @@ void sdramc_init(void)
void gpio_init(void)
{
/* Enable UART0 pins */
writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
mcf_write16(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
MCFGPIO_PAR_UART);
/*
* Initialize TIN3 as a GPIO output to enable the write
* half of the latch.
*/
writeb(0x00, MCFGPIO_PAR_TIMER);
writeb(0x08, MCFGPIO_PDDR_TIMER);
writeb(0x00, MCFGPIO_PCLRR_TIMER);
mcf_write8(0x00, MCFGPIO_PAR_TIMER);
mcf_write8(0x08, MCFGPIO_PDDR_TIMER);
mcf_write8(0x00, MCFGPIO_PCLRR_TIMER);
}
int clock_pll(int fsys, int flags)
@ -476,7 +476,7 @@ int clock_pll(int fsys, int flags)
if (fsys == 0) {
/* Return current PLL output */
mfd = readb(MCF_PLL_PFDR);
mfd = mcf_read8(MCF_PLL_PFDR);
return (fref * mfd / (BUSDIV * 4));
}
@ -502,9 +502,9 @@ int clock_pll(int fsys, int flags)
* If it has then the SDRAM needs to be put into self refresh
* mode before reprogramming the PLL.
*/
if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
if (mcf_read32(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
/* Put SDRAM into self refresh mode */
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/*
@ -516,10 +516,10 @@ int clock_pll(int fsys, int flags)
clock_limp(DEFAULT_LPD);
/* Reprogram PLL for desired fsys */
writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
mcf_write8(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
MCF_PLL_PODR);
writeb(mfd, MCF_PLL_PFDR);
mcf_write8(mfd, MCF_PLL_PFDR);
/* Exit LIMP mode */
clock_exit_limp();
@ -527,13 +527,13 @@ int clock_pll(int fsys, int flags)
/*
* Return the SDRAM to normal operation if it is in use.
*/
if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
if (mcf_read32(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
/* Exit self refresh mode */
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
mcf_write32(mcf_read32(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/* Errata - workaround for SDRAM operation after exiting LIMP mode */
writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
mcf_write32(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
/* wait for DQS logic to relock */
for (i = 0; i < 0x200; i++)
@ -554,12 +554,12 @@ int clock_limp(int div)
/* Save of the current value of the SSIDIV so we don't
overwrite the value*/
temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
temp = mcf_read16(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
/* Apply the divider to the system clock */
writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
mcf_write16(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
mcf_write16(mcf_read16(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
return (FREF/(3*(1 << div)));
}
@ -569,10 +569,10 @@ int clock_exit_limp(void)
int fout;
/* Exit LIMP mode */
writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
mcf_write16(mcf_read16(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
/* Wait for PLL to lock */
while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
while (!(mcf_read16(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
;
fout = get_sys_clock();
@ -585,10 +585,10 @@ int get_sys_clock(void)
int divider;
/* Test to see if device is in LIMP mode */
if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
if (mcf_read16(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
divider = mcf_read16(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
return (FREF/(2 << divider));
}
else
return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
return (FREF * mcf_read8(MCF_PLL_PFDR)) / (BUSDIV * 4);
}

2
arch/m68k/coldfire/m5407.c
View File

@ -40,7 +40,7 @@ static struct clk_lookup m5407_clk_lookup[] = {
static void __init m5407_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */

33
arch/m68k/coldfire/m5441x.c
View File

@ -41,9 +41,10 @@ DEFINE_CLK(0, "mcfpit.0", 32, MCF_BUSCLK);
DEFINE_CLK(0, "mcfpit.1", 33, MCF_BUSCLK);
DEFINE_CLK(0, "mcfpit.2", 34, MCF_BUSCLK);
DEFINE_CLK(0, "mcfpit.3", 35, MCF_BUSCLK);
DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
DEFINE_CLK(0, "mcfeport.0", 36, MCF_CLK);
DEFINE_CLK(0, "mcfadc.0", 37, MCF_CLK);
DEFINE_CLK(0, "mcfdac.0", 38, MCF_CLK);
DEFINE_CLK(0, "mcfdac.1", 39, MCF_CLK);
DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
@ -103,9 +104,10 @@ static struct clk_lookup m5411x_clk_lookup[] = {
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34),
CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfadc.0", NULL, &__clk_0_38),
CLKDEV_INIT("mcfdac.0", NULL, &__clk_0_39),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_36),
CLKDEV_INIT("mcfadc.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfdac.0", NULL, &__clk_0_38),
CLKDEV_INIT("mcfdac.1", NULL, &__clk_0_39),
CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
CLKDEV_INIT("mcfsim.0", NULL, &__clk_0_43),
CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
@ -156,7 +158,7 @@ static struct clk * const enable_clks[] __initconst = {
&__clk_0_27, /* uart3 */
&__clk_0_33, /* pit.1 */
&__clk_0_37, /* eport */
&__clk_0_36, /* eport */
&__clk_0_48, /* pll */
&__clk_0_51, /* esdhc */
@ -174,8 +176,9 @@ static struct clk * const disable_clks[] __initconst = {
&__clk_0_32, /* pit.0 */
&__clk_0_34, /* pit.2 */
&__clk_0_35, /* pit.3 */
&__clk_0_38, /* adc */
&__clk_0_39, /* dac */
&__clk_0_37, /* adc */
&__clk_0_38, /* dac.0 */
&__clk_0_39, /* dac.1 */
&__clk_0_44, /* usb otg */
&__clk_0_45, /* usb host */
&__clk_0_47, /* ssi.0 */
@ -201,12 +204,12 @@ static struct clk * const disable_clks[] __initconst = {
static void __clk_enable2(struct clk *clk)
{
__raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
mcf_write32(mcf_read32(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
}
static void __clk_disable2(struct clk *clk)
{
__raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
mcf_write32(mcf_read32(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
}
struct clk_ops clk_ops2 = {
@ -229,14 +232,14 @@ static void __init m5441x_clk_init(void)
static void __init m5441x_uarts_init(void)
{
__raw_writeb(0x0f, MCFGPIO_PAR_UART0);
__raw_writeb(0x00, MCFGPIO_PAR_UART1);
__raw_writeb(0x00, MCFGPIO_PAR_UART2);
mcf_write8(0x0f, MCFGPIO_PAR_UART0);
mcf_write8(0x00, MCFGPIO_PAR_UART1);
mcf_write8(0x00, MCFGPIO_PAR_UART2);
}
static void __init m5441x_fec_init(void)
{
__raw_writeb(0x03, MCFGPIO_PAR_FEC);
mcf_write8(0x03, MCFGPIO_PAR_FEC);
}
void __init config_BSP(char *commandp, int size)

18
arch/m68k/coldfire/m54xx.c
View File

@ -51,12 +51,12 @@ static struct clk_lookup m54xx_clk_lookup[] = {
static void __init m54xx_uarts_init(void)
{
/* enable io pins */
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
MCFGPIO_PAR_PSC1);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
mcf_write8(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
}
/***************************************************************************/
@ -67,9 +67,9 @@ static void __init m54xx_i2c_init(void)
u32 r;
/* set the fec/i2c/irq pin assignment register for i2c */
r = readl(MCF_PAR_FECI2CIRQ);
r = mcf_read32(MCF_PAR_FECI2CIRQ);
r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
writel(r, MCF_PAR_FECI2CIRQ);
mcf_write32(r, MCF_PAR_FECI2CIRQ);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
@ -79,9 +79,9 @@ static void mcf54xx_reset(void)
{
/* disable interrupts and enable the watchdog */
asm("movew #0x2700, %sr\n");
__raw_writel(0, MCF_GPT_GMS0);
__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
mcf_write32(0, MCF_GPT_GMS0);
mcf_write32(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
mcf_write32(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
MCF_GPT_GMS0);
}

16
arch/m68k/coldfire/nettel.c
View File

@ -106,10 +106,10 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha
if ((macp[0] == 0xffff) && (macp[1] == 0xffff) && (macp[2] == 0xffff))
macp = (u16 *) &nettel_macdefault[0];
writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
writew(macp[0], ioaddr + SMC91xx_BASEMAC);
writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
mcf_write16(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
mcf_write16(macp[0], ioaddr + SMC91xx_BASEMAC);
mcf_write16(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
mcf_write16(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
}
/***************************************************************************/
@ -122,14 +122,14 @@ static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flasha
static void __init nettel_smc91x_init(void)
{
writew(0x00ec, MCFSIM_PADDR);
mcf_write16(0x00ec, MCFSIM_PADDR);
mcf_setppdata(0, 0x0080);
writew(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
writew(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
mcf_write16(1, NETTEL_SMC0_ADDR + SMC91xx_BANKSELECT);
mcf_write16(0x0067, NETTEL_SMC0_ADDR + SMC91xx_BASEADDR);
mcf_setppdata(0x0080, 0);
/* Set correct chip select timing for SMC9196 accesses */
writew(0x1180, MCFSIM_CSCR3);
mcf_write16(0x1180, MCFSIM_CSCR3);
/* Set the SMC interrupts to be auto-vectored */
mcf_autovector(NETTEL_SMC0_IRQ);

56
arch/m68k/coldfire/pci.c
View File

@ -68,24 +68,24 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
}
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
mcf_write32(PCICAR_E | addr, PCICAR);
mcf_read32(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
case 1:
*value = __raw_readb(addr);
*value = mcf_read8(addr);
break;
case 2:
*value = le16_to_cpu(__raw_readw(addr));
*value = le16_to_cpu(mcf_read16(addr));
break;
default:
*value = le32_to_cpu(__raw_readl(addr));
*value = le32_to_cpu(mcf_read32(addr));
break;
}
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
mcf_write32(0, PCICAR);
mcf_read32(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
@ -100,24 +100,24 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
}
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
mcf_write32(PCICAR_E | addr, PCICAR);
mcf_read32(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
case 1:
__raw_writeb(value, addr);
mcf_write8(value, addr);
break;
case 2:
__raw_writew(cpu_to_le16(value), addr);
mcf_write16(cpu_to_le16(value), addr);
break;
default:
__raw_writel(cpu_to_le32(value), addr);
mcf_write32(cpu_to_le32(value), addr);
break;
}
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
mcf_write32(0, PCICAR);
mcf_read32(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
@ -175,44 +175,44 @@ static int __init mcf_pci_init(void)
pr_info("ColdFire: PCI bus initialization...\n");
/* Reset the external PCI bus */
__raw_writel(PCIGSCR_RESET, PCIGSCR);
__raw_writel(0, PCITCR);
mcf_write32(PCIGSCR_RESET, PCIGSCR);
mcf_write32(0, PCITCR);
request_resource(&iomem_resource, &mcf_pci_mem);
request_resource(&iomem_resource, &mcf_pci_io);
/* Configure PCI arbiter */
__raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
mcf_write32(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
PACR_EXTMINTE(0x1f), PACR);
/* Set required multi-function pins for PCI bus use */
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
mcf_write16(0x3ff, MCFGPIO_PAR_PCIBG);
mcf_write16(0x3ff, MCFGPIO_PAR_PCIBR);
/* Set up config space for local host bus controller */
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
mcf_write32(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_INVALIDATE, PCISCR);
__raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
__raw_writel(0, PCICR2);
mcf_write32(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
mcf_write32(0, PCICR2);
/*
* Set up the initiator windows for memory and IO mapping.
* These give the CPU bus access onto the PCI bus. One for each of
* PCI memory and IO address spaces.
*/
__raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
mcf_write32(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
PCIIW0BTAR);
__raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
mcf_write32(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
PCIIW1BTAR);
__raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
mcf_write32(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
/*
* Set up the target windows for access from the PCI bus back to the
* CPU bus. All we need is access to system RAM (for mastering).
*/
__raw_writel(CONFIG_RAMBASE, PCIBAR1);
__raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
mcf_write32(CONFIG_RAMBASE, PCIBAR1);
mcf_write32(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
/* Keep a virtual mapping to IO/config space active */
iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
@ -224,7 +224,7 @@ static int __init mcf_pci_init(void)
(u32) iospace);
/* Turn of PCI reset, and wait for devices to settle */
__raw_writel(0, PCIGSCR);
mcf_write32(0, PCIGSCR);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(200));

20
arch/m68k/coldfire/pit.c
View File

@ -45,9 +45,9 @@ static u32 pit_cnt;
static int cf_pit_set_periodic(struct clock_event_device *evt)
{
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
mcf_write16(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
mcf_write16(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
mcf_write16(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD |
MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
return 0;
@ -55,15 +55,15 @@ static int cf_pit_set_periodic(struct clock_event_device *evt)
static int cf_pit_set_oneshot(struct clock_event_device *evt)
{
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
mcf_write16(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
mcf_write16(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
return 0;
}
static int cf_pit_shutdown(struct clock_event_device *evt)
{
__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
mcf_write16(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
return 0;
}
@ -75,7 +75,7 @@ static int cf_pit_shutdown(struct clock_event_device *evt)
static int cf_pit_next_event(unsigned long delta,
struct clock_event_device *evt)
{
__raw_writew(delta, TA(MCFPIT_PMR));
mcf_write16(delta, TA(MCFPIT_PMR));
return 0;
}
@ -101,8 +101,8 @@ static irqreturn_t pit_tick(int irq, void *dummy)
u16 pcsr;
/* Reset the ColdFire timer */
pcsr = __raw_readw(TA(MCFPIT_PCSR));
__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
pcsr = mcf_read16(TA(MCFPIT_PCSR));
mcf_write16(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
pit_cnt += PIT_CYCLES_PER_JIFFY;
evt->event_handler(evt);
@ -118,7 +118,7 @@ static u64 pit_read_clk(struct clocksource *cs)
u16 pcntr;
local_irq_save(flags);
pcntr = __raw_readw(TA(MCFPIT_PCNTR));
pcntr = mcf_read16(TA(MCFPIT_PCNTR));
cycles = pit_cnt;
local_irq_restore(flags);

4
arch/m68k/coldfire/reset.c
View File

@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
{
local_irq_disable();
/* Set watchdog to soft reset, and enabled */
__raw_writeb(0xc0, MCFSIM_SYPCR);
mcf_write8(0xc0, MCFSIM_SYPCR);
for (;;)
/* wait for watchdog to timeout */;
}
@ -37,7 +37,7 @@ static void mcf_cpu_reset(void)
static void mcf_cpu_reset(void)
{
local_irq_disable();
__raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
mcf_write8(MCF_RCR_SWRESET, MCF_RCR);
}
#endif

18
arch/m68k/coldfire/sltimers.c
View File

@ -44,7 +44,7 @@
irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
{
/* Reset Slice Timer 1 */
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
mcf_write32(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
if (current->pid)
profile_tick(CPU_PROFILING);
return IRQ_HANDLED;
@ -65,8 +65,8 @@ void mcfslt_profile_init(void)
}
/* Set up TIMER 2 as high speed profile clock */
__raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
mcf_write32(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
mcf_write32(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
PA(MCFSLT_SCR));
}
@ -86,7 +86,7 @@ static u32 mcfslt_cnt;
static irqreturn_t mcfslt_tick(int irq, void *dummy)
{
/* Reset Slice Timer 0 */
__raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
mcf_write32(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
mcfslt_cnt += mcfslt_cycles_per_jiffy;
legacy_timer_tick(1);
return IRQ_HANDLED;
@ -98,11 +98,11 @@ static u64 mcfslt_read_clk(struct clocksource *cs)
u32 cycles, scnt;
local_irq_save(flags);
scnt = __raw_readl(TA(MCFSLT_SCNT));
scnt = mcf_read32(TA(MCFSLT_SCNT));
cycles = mcfslt_cnt;
if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
if (mcf_read32(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
cycles += mcfslt_cycles_per_jiffy;
scnt = __raw_readl(TA(MCFSLT_SCNT));
scnt = mcf_read32(TA(MCFSLT_SCNT));
}
local_irq_restore(flags);
@ -129,8 +129,8 @@ void hw_timer_init(void)
* STCNT + 1 steps for 1 tick, not STCNT. So if you want
* n cycles, initialize STCNT with n - 1.
*/
__raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
__raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
mcf_write32(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
mcf_write32(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
TA(MCFSLT_SCR));
/* initialize mcfslt_cnt knowing that slice timers count down */
mcfslt_cnt = mcfslt_cycles_per_jiffy;

63
arch/m68k/coldfire/stmark2.c
View File

@ -1,13 +1,14 @@
/*
* stmark2.c -- Support for Sysam AMCORE open board
* stmark2.c -- Support for Kernelspace AMCORE open board
*
* (C) Copyright 2017, Angelo Dureghello <angelo@sysam.it>
* (C) Copyright 2026, Angelo Dureghello <angelo@kernel-space.org>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
@ -62,21 +63,10 @@ static struct fsl_dspi_platform_data dspi_spi0_info = {
};
static struct resource dspi_spi0_resource[] = {
[0] = {
.start = MCFDSPI_BASE0,
.end = MCFDSPI_BASE0 + 0xFF,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 12,
.end = 13,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = MCF_IRQ_DSPI0,
.end = MCF_IRQ_DSPI0,
.flags = IORESOURCE_IRQ,
},
DEFINE_RES_MEM(MCFDSPI_BASE0, 0x100),
DEFINE_RES_IRQ(MCF_IRQ_DSPI0),
DEFINE_RES_DMA(12),
DEFINE_RES_DMA(13),
};
static u64 stmark2_dspi_mask = DMA_BIT_MASK(32);
@ -94,8 +84,28 @@ static struct platform_device dspi_spi0_device = {
},
};
static struct resource dac0_resource = DEFINE_RES_MEM(MCFDAC_BASE0, 0x100);
static struct platform_device dac0_device = {
.name = "mcfdac",
.id = 0,
.num_resources = 1,
.resource = &dac0_resource,
};
static struct resource dac1_resource = DEFINE_RES_MEM(MCFDAC_BASE1, 0x100);
static struct platform_device dac1_device = {
.name = "mcfdac",
.id = 1,
.num_resources = 1,
.resource = &dac1_resource,
};
static struct platform_device *stmark2_devices[] __initdata = {
&dspi_spi0_device,
&dac0_device,
&dac1_device,
};
/*
@ -103,17 +113,24 @@ static struct platform_device *stmark2_devices[] __initdata = {
*/
static int __init init_stmark2(void)
{
u16 val;
/* DSPI0, all pins as DSPI, and using CS1 */
__raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
__raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
mcf_write8(0x80, MCFGPIO_PAR_DSPIOWL);
mcf_write8(0xfc, MCFGPIO_PAR_DSPIOWH);
/* Board gpio setup */
__raw_writeb(0x00, MCFGPIO_PAR_BE);
__raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
__raw_writeb(0x00, MCFGPIO_PAR_CS);
mcf_write8(0x00, MCFGPIO_PAR_BE);
mcf_write8(0x00, MCFGPIO_PAR_FBCTL);
mcf_write8(0x00, MCFGPIO_PAR_CS);
/* CAN pads */
__raw_writeb(0x50, MCFGPIO_PAR_CANI2C);
mcf_write8(0x50, MCFGPIO_PAR_CANI2C);
val = mcf_read16(MCF_CCM_MISCCR2);
val &= ~(MCF_CCM_MISCCR2_ADC3_EN | MCF_CCM_MISCCR2_ADC7_EN);
val |= MCF_CCM_MISCCR2_DAC0_SEL | MCF_CCM_MISCCR2_DAC1_SEL;
mcf_write16(val, MCF_CCM_MISCCR2);
platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));

30
arch/m68k/coldfire/timers.c
View File

@ -38,11 +38,11 @@
void coldfire_profile_init(void);
#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#define __raw_readtrr __raw_readl
#define __raw_writetrr __raw_writel
#define mcf_readtrr mcf_read32
#define mcf_writetrr mcf_write32
#else
#define __raw_readtrr __raw_readw
#define __raw_writetrr __raw_writew
#define mcf_readtrr mcf_read16
#define mcf_writetrr mcf_write16
#endif
static u32 mcftmr_cycles_per_jiffy;
@ -54,13 +54,13 @@ static void init_timer_irq(void)
{
#ifdef MCFSIM_ICR_AUTOVEC
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCFSIM_TIMER1ICR);
mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
mcf_write8(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCFSIM_TIMER2ICR);
mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
#endif
@ -72,7 +72,7 @@ static void init_timer_irq(void)
static irqreturn_t mcftmr_tick(int irq, void *dummy)
{
/* Reset the ColdFire timer */
__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
mcf_write8(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
mcftmr_cnt += mcftmr_cycles_per_jiffy;
legacy_timer_tick(1);
@ -88,7 +88,7 @@ static u64 mcftmr_read_clk(struct clocksource *cs)
u16 tcn;
local_irq_save(flags);
tcn = __raw_readw(TA(MCFTIMER_TCN));
tcn = mcf_read16(TA(MCFTIMER_TCN));
cycles = mcftmr_cnt;
local_irq_restore(flags);
@ -111,7 +111,7 @@ void hw_timer_init(void)
{
int r;
__raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
mcf_write16(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
mcftmr_cycles_per_jiffy = FREQ / HZ;
/*
* The coldfire timer runs from 0 to TRR included, then 0
@ -119,8 +119,8 @@ void hw_timer_init(void)
* for 1 tick, not TRR. So if you want n cycles,
* initialize TRR with n - 1.
*/
__raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
mcf_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
mcf_write16(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
clocksource_register_hz(&mcftmr_clk, FREQ);
@ -158,7 +158,7 @@ void hw_timer_init(void)
irqreturn_t coldfire_profile_tick(int irq, void *dummy)
{
/* Reset ColdFire timer2 */
__raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
mcf_write8(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
if (current->pid)
profile_tick(CPU_PROFILING);
return IRQ_HANDLED;
@ -174,10 +174,10 @@ void coldfire_profile_init(void)
PROFILEHZ);
/* Set up TIMER 2 as high speed profile clock */
__raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
mcf_write16(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
__raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
__raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
mcf_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
mcf_write16(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
ret = request_irq(MCF_IRQ_PROFILER, coldfire_profile_tick, IRQF_TIMER,

9
arch/m68k/configs/m5208evb_defconfig
View File

@ -1,22 +1,23 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
# CONFIG_4KSTACKS is not set
CONFIG_RAMBASE=0x40000000
CONFIG_RAMSIZE=0x2000000
CONFIG_VECTORBASE=0x40000000
CONFIG_KERNELBASE=0x40020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y

9
arch/m68k/configs/m5249evb_defconfig
View File

@ -1,15 +1,12 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
CONFIG_M5249=y
CONFIG_M5249C3=y
@ -17,7 +14,10 @@ CONFIG_RAMBASE=0x00000000
CONFIG_RAMSIZE=0x00800000
CONFIG_VECTORBASE=0x00000000
CONFIG_KERNELBASE=0x00020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -45,5 +45,6 @@ CONFIG_EXT2_FS=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_BOOTPARAM=y
CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"

9
arch/m68k/configs/m5272c3_defconfig
View File

@ -1,15 +1,12 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
CONFIG_M5272=y
CONFIG_M5272C3=y
@ -17,7 +14,10 @@ CONFIG_RAMBASE=0x00000000
CONFIG_RAMSIZE=0x00800000
CONFIG_VECTORBASE=0x00000000
CONFIG_KERNELBASE=0x00020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -46,5 +46,6 @@ CONFIG_EXT2_FS=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_BOOTPARAM=y
CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"

9
arch/m68k/configs/m5275evb_defconfig
View File

@ -1,15 +1,12 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
CONFIG_M5275=y
# CONFIG_4KSTACKS is not set
@ -17,7 +14,10 @@ CONFIG_RAMBASE=0x00000000
CONFIG_RAMSIZE=0x00000000
CONFIG_VECTORBASE=0x00000000
CONFIG_KERNELBASE=0x00020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -47,5 +47,6 @@ CONFIG_EXT2_FS=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_BOOTPARAM=y
CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"

10
arch/m68k/configs/m5307c3_defconfig
View File

@ -1,15 +1,12 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
CONFIG_M5307=y
CONFIG_M5307C3=y
@ -17,7 +14,10 @@ CONFIG_RAMBASE=0x00000000
CONFIG_RAMSIZE=0x00800000
CONFIG_VECTORBASE=0x00000000
CONFIG_KERNELBASE=0x00020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -34,7 +34,6 @@ CONFIG_NETDEVICES=y
CONFIG_PPP=y
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
@ -50,6 +49,7 @@ CONFIG_EXT2_FS=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_BOOTPARAM=y
CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"
CONFIG_FULLDEBUG=y

61
arch/m68k/configs/m5329evb_defconfig Normal file
View File

@ -0,0 +1,61 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_SYSCALL=y
CONFIG_EXPERT=y
# CONFIG_FHANDLE is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
CONFIG_M532x=y
CONFIG_CLOCK_FREQ=240000000
CONFIG_RAMBASE=0x40000000
CONFIG_RAMSIZE=0x02000000
CONFIG_VECTORBASE=0x40000000
CONFIG_KERNELBASE=0x40020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAM=y
CONFIG_MTD_UCLINUX=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
CONFIG_FEC=y
# CONFIG_WLAN is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT_CONSOLE is not set
# CONFIG_UNIX98_PTYS is not set
CONFIG_SERIAL_MCF=y
CONFIG_SERIAL_MCF_BAUDRATE=115200
CONFIG_SERIAL_MCF_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_COLDFIRE_QSPI=y
# CONFIG_PTP_1588_CLOCK is not set
# CONFIG_HWMON is not set
CONFIG_EXT2_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_JFFS2_FS=m
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_FULLDEBUG=y

9
arch/m68k/configs/m5407c3_defconfig
View File

@ -1,16 +1,12 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
CONFIG_M5407=y
CONFIG_M5407C3=y
@ -18,7 +14,10 @@ CONFIG_RAMBASE=0x00000000
CONFIG_RAMSIZE=0x00000000
CONFIG_VECTORBASE=0x00000000
CONFIG_KERNELBASE=0x00020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y

70
arch/m68k/configs/m54418evb_defconfig Normal file
View File

@ -0,0 +1,70 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_SYSCALL=y
CONFIG_EXPERT=y
# CONFIG_FHANDLE is not set
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_KALLSYMS is not set
CONFIG_COLDFIRE=y
CONFIG_M5441x=y
CONFIG_CLOCK_FREQ=250000000
# CONFIG_4KSTACKS is not set
CONFIG_RAMBASE=0x40000000
CONFIG_RAMSIZE=0x02000000
CONFIG_VECTORBASE=0x40000000
CONFIG_KERNELBASE=0x40020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_BFQ is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAM=y
CONFIG_MTD_UCLINUX=y
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
CONFIG_PPP=y
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
CONFIG_SERIAL_MCF=y
CONFIG_SERIAL_MCF_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
CONFIG_SPI_FSL_DSPI=y
# CONFIG_PTP_1588_CLOCK is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_MCF=y
CONFIG_DMADEVICES=y
CONFIG_MCF_EDMA=y
# CONFIG_NVMEM is not set
CONFIG_VALIDATE_FS_PARSER=y
CONFIG_EXT2_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_NULL=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_SHA256=y
CONFIG_FRAME_WARN=1024

12
arch/m68k/configs/m5475evb_defconfig
View File

@ -1,6 +1,5 @@
# CONFIG_SWAP is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_KALLSYMS is not set
CONFIG_EXPERT=y
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
@ -8,9 +7,7 @@ CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EVENTFD is not set
# CONFIG_SHMEM is not set
# CONFIG_AIO is not set
CONFIG_EXPERT=y
CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_KALLSYMS is not set
CONFIG_COLDFIRE=y
# CONFIG_4KSTACKS is not set
CONFIG_RAMBASE=0x0
@ -18,8 +15,11 @@ CONFIG_RAMSIZE=0x2000000
CONFIG_VECTORBASE=0x0
CONFIG_MBAR=0xff000000
CONFIG_KERNELBASE=0x20000
CONFIG_PCI=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_SWAP is not set
CONFIG_PCI=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y

56
arch/m68k/configs/nettel_defconfig Normal file
View File

@ -0,0 +1,56 @@
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
# CONFIG_FUTEX is not set
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_AIO is not set
# CONFIG_KALLSYMS is not set
# CONFIG_MMU is not set
CONFIG_M5307=y
CONFIG_NETtel=y
CONFIG_RAMBASE=0x00000000
CONFIG_RAMSIZE=0x00800000
CONFIG_VECTORBASE=0x00000000
CONFIG_KERNELBASE=0x00020000
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_BINFMT_FLAT=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAM=y
CONFIG_MTD_UCLINUX=y
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
CONFIG_SMC91X=y
CONFIG_PPP=y
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_MCF=y
CONFIG_SERIAL_MCF_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_MTD=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_SLUB_DEBUG is not set
CONFIG_BOOTPARAM=y
CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"
CONFIG_FULLDEBUG=y

33
arch/m68k/configs/stmark2_defconfig
View File

@ -2,16 +2,20 @@ CONFIG_LOCALVERSION="stmark2-001"
CONFIG_DEFAULT_HOSTNAME="stmark2"
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
# CONFIG_RD_ZSTD is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EXPERT=y
# CONFIG_FHANDLE is not set
# CONFIG_AIO is not set
# CONFIG_ADVISE_SYSCALLS is not set
# CONFIG_MEMBARRIER is not set
CONFIG_EXPERT=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_KALLSYMS is not set
CONFIG_COLDFIRE=y
CONFIG_M5441x=y
CONFIG_CLOCK_FREQ=240000000
@ -21,10 +25,12 @@ CONFIG_RAMBASE=0x40000000
CONFIG_RAMSIZE=0x8000000
CONFIG_VECTORBASE=0x40000000
CONFIG_KERNELBASE=0x40001000
# CONFIG_BLK_DEV_BSG is not set
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y
CONFIG_BINFMT_MISC=y
# CONFIG_COREDUMP is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
@ -47,11 +53,11 @@ CONFIG_MTD_SPI_NOR=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_UNIX98_PTYS is not set
# CONFIG_DEVMEM is not set
CONFIG_SERIAL_MCF=y
CONFIG_SERIAL_MCF_BAUDRATE=115200
CONFIG_SERIAL_MCF_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_DEVMEM is not set
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_FSL_DSPI=y
@ -59,7 +65,7 @@ CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC_PLATFORM=y
# CONFIG_HWMON is not set
# CONFIG_HID is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
@ -68,6 +74,8 @@ CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_MCF=y
CONFIG_DMADEVICES=y
CONFIG_MCF_EDMA=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
@ -79,14 +87,13 @@ CONFIG_EXT4_FS_SECURITY=y
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_OVERLAY_FS=y
CONFIG_FSCACHE=y
# CONFIG_PROC_SYSCTL is not set
CONFIG_CRAMFS=y
CONFIG_SQUASHFS=y
CONFIG_ROMFS_FS=y
# CONFIG_CRYPTO_HW is not set
CONFIG_XZ_DEC=y
CONFIG_PRINTK_TIME=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DYNAMIC_DEBUG_CORE=y
# CONFIG_DEBUG_MISC is not set
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_SLUB_DEBUG_ON=y
# CONFIG_SLUB_DEBUG is not set
CONFIG_PANIC_ON_OOPS=y
# CONFIG_RUNTIME_TESTING_MENU is not set

16
arch/m68k/include/asm/io_no.h
View File

@ -107,6 +107,22 @@ static inline void writel(u32 value, volatile void __iomem *addr)
#endif /* IOMEMBASE */
#if defined(CONFIG_COLDFIRE)
/*
* The ColdFire internal peripheral registers are big-endian, so you
* cannot use the conventional little-endian readb/readw/readl and
* writeb/writew/writel access functions. Define a family of access
* functions to give correct endian access that can be used by all
* architecture code.
*/
#define mcf_read8 __raw_readb
#define mcf_read16 __raw_readw
#define mcf_read32 __raw_readl
#define mcf_write8 __raw_writeb
#define mcf_write16 __raw_writew
#define mcf_write32 __raw_writel
#endif /* CONFIG_COLDFIRE */
#if defined(CONFIG_PCI)
/*
* Support for PCI bus access uses the asm-generic access functions.

42
arch/m68k/include/asm/m5441xsim.h
View File

@ -8,6 +8,8 @@
#ifndef m5441xsim_h
#define m5441xsim_h
#include <linux/bits.h>
#define CPU_NAME "COLDFIRE(m5441x)"
#define CPU_INSTR_PER_JIFFY 2
#define MCF_BUSCLK (MCF_CLK / 2)
@ -125,6 +127,41 @@
#define MCFPM_PPMHR1 0xfc040038
#define MCFPM_PPMLR1 0xfc04003c
#define MCFPM_LPCR 0xec090007
/*
* Chip Configuration Module (CCM).
*/
#define MCF_CCM_CCR 0xec090004
#define MCF_CCM_RCON 0xec090008
#define MCF_CCM_CIR 0xec09000a
#define MCF_CCM_MISCCR 0xec09000e
#define MCF_CCM_CDRH 0xec090010
#define MCF_CCM_CDRL 0xec090012
#define MCF_CCM_UOCSR 0xec090014
#define MCF_CCM_UHCSR 0xec090016
#define MCF_CCM_MISCCR3 0xec090018
#define MCF_CCM_MISCCR2 0xec09001a
#define MCF_CCM_ADCTSR 0xec09001c
#define MCF_CCM_DACTSR 0xec09001e
#define MCF_CCM_SBFSR 0xec090020
#define MCF_CCM_SBFCR 0xec090022
#define MCF_CCM_FNACR 0xec090024
/* Bit definitions and macros for MCF_CCM_MISCCR2 */
#define MCF_CCM_MISCCR2_ULPI BIT(0)
#define MCF_CCM_MISCCR2_FB_HALF BIT(1)
#define MCF_CCM_MISCCR2_ADC3_EN BIT(2)
#define MCF_CCM_MISCCR2_ADC7_EN BIT(3)
#define MCF_CCM_MISCCR2_ADC_EN BIT(4)
#define MCF_CCM_MISCCR2_DAC0_SEL BIT(5)
#define MCF_CCM_MISCCR2_DAC1_SEL BIT(6)
#define MCF_CCM_MISCCR2_DCC_BYP BIT(7)
#define MCF_CCM_MISCCR2_PLL_MODE GENMASK(10, 8)
#define MCF_CCM_MISCCR2_SWT_SCR BIT(12)
#define MCF_CCM_MISCCR2_RGPIO_HALF BIT(13)
#define MCF_CCM_MISCCR2_DDR2_CLK BIT(14)
#define MCF_CCM_MISCCR2_EXTCLK_BYP BIT(15)
/*
* UART module.
*/
@ -191,6 +228,11 @@
#define MCFEPORT_EPPAR 0xfc090000
#define MCFEPORT_EPIER 0xfc090003
#define MCFEPORT_EPFR 0xfc090006
/*
* DAC Modules.
*/
#define MCFDAC_BASE0 0xfc098000
#define MCFDAC_BASE1 0xfc09c000
/*
* RTC Module.
*/

12
arch/m68k/include/asm/mcfgpio.h
View File

@ -95,8 +95,8 @@ static inline void gpio_free(unsigned gpio)
#define MCFGPIO_PORTTYPE u8
#define MCFGPIO_PORTSIZE 8
#define mcfgpio_read(port) __raw_readb(port)
#define mcfgpio_write(data, port) __raw_writeb(data, port)
#define mcfgpio_read(port) mcf_read8(port)
#define mcfgpio_write(data, port) mcf_write8(data, port)
#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
@ -104,8 +104,8 @@ static inline void gpio_free(unsigned gpio)
#define MCFGPIO_PORTTYPE u16
#define MCFGPIO_PORTSIZE 16
#define mcfgpio_read(port) __raw_readw(port)
#define mcfgpio_write(data, port) __raw_writew(data, port)
#define mcfgpio_read(port) mcf_read16(port)
#define mcfgpio_write(data, port) mcf_write16(data, port)
#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
@ -113,8 +113,8 @@ static inline void gpio_free(unsigned gpio)
#define MCFGPIO_PORTTYPE u32
#define MCFGPIO_PORTSIZE 32
#define mcfgpio_read(port) __raw_readl(port)
#define mcfgpio_write(data, port) __raw_writel(data, port)
#define mcfgpio_read(port) mcf_read32(port)
#define mcfgpio_write(data, port) mcf_write32(data, port)
#endif

4
arch/m68k/include/asm/nettel.h
View File

@ -87,12 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
*/
static __inline__ unsigned int mcf_getppdata(void)
{
return readw(MCFSIM_PBDAT);
return mcf_read16(MCFSIM_PBDAT);
}
static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
{
writew((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
mcf_write16((mcf_read16(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
}
#endif