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soc: arm code changes for 7.2

Browse Source 
The largest addition here is the revived support for the ZTE ZX
 SoC platform, though this mostly documentation.
 
 The other changes are code cleanups that deal with continued
 conversion of the GPIO library away from GPIO numbers to
 descriptors and a few minor bugfixes.
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Merge tag 'soc-arm-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull arm SoC code updates from Arnd Bergmann:
 "The largest addition here is the revived support for the ZTE ZX SoC
  platform, though this mostly documentation.

  The other changes are code cleanups that deal with continued
  conversion of the GPIO library away from GPIO numbers to descriptors
  and a few minor bugfixes"

* tag 'soc-arm-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  MAINTAINERS: Add Axiado reviewer and Maintainers
  ARM: remove the last few uses of do_bad_IRQ()
  ARM: imx31: Fix IIM mapping leak in revision check
  ARM: imx3: Fix CCM node reference leak
  ARM: orion5x: update board check in mss2_pci_init() to use the DT
  arm: mvebu_v5_defconfig: remove stale MACH_LINKSTATION_LSCHL reference
  ARM: mvebu: simplify of_node_put calls
  ARM: mvebu: drop unnecessary NULL check
  arm: boot: ep93xx: don't rely on machine_is_*() for removed board files
  ARM: zte: clean up zx297520v3 doc. warnings
  arm64: Kconfig: drop unneeded dependency on OF_GPIO for ARCH_MVEBU
  firmware: imx: sm-misc: Make scmi_imx_misc_ctrl_nb variable static
  ARM: zte: Add zx297520v3 platform support
  ARM: pxa: pxa27x: attach software node to its target GPIO controller
  ARM: pxa: pxa25x: attach software node to its target GPIO controller
  ARM: pxa: spitz: attach software nodes to their target GPIO controllers
  ARM: pxa: statify platform device definitions in spitz board file
  ARM: omap2: simplify allocation for omap_device
  ARM: select legacy gpiolib interfaces where used
  ARM: s3c: use gpio lookup table for LEDs
This commit is contained in:
Linus Torvalds 2026-06-17 11:28:10 -07:00
commit 6505114e82
32 changed files with 320 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/arch/arm/index.rst
View File

@ -75,3 +75,5 @@ SoC-specific documents
sti/overview
vfp/release-notes
zte/index

10
Documentation/arch/arm/zte/index.rst Normal file
View File

@ -0,0 +1,10 @@
.. SPDX-License-Identifier: GPL-2.0-only
=======
ZTE SoC
=======
.. toctree::
:maxdepth: 1
zx297520v3

166
Documentation/arch/arm/zte/zx297520v3.rst Normal file
View File

@ -0,0 +1,166 @@
.. SPDX-License-Identifier: GPL-2.0-only
====================================
Booting Linux on ZTE zx297520v3 SoCs
====================================
Author: Stefan Dösinger
Date : 27 Jan 2026
1. Hardware description
---------------------------
Zx297520v3 SoCs use a 64-bit capable Cortex-A53 CPU and GICv3, although they
run in arm32 mode only. The CPU has support EL3, but no hypervisor (EL2) and
it seems to lack VFP and NEON.
The SoC is used in a number of cheap LTE to WiFi routers, both battery powered
MiFis and stationary CPEs. In addition to the CPU these devices usually have
64 MB Ram (although some is shared with the LTE chip), 128 MB NAND flash, an
SDIO connected RTL8192-type Wifi chip limited to 2.4 ghz operation, USB 2,
and buttons. Devices with as low as 32 MB or as high as 128 MB ram exist, as
do devices with 8 or 16 MB of NOR flash.
Some devices, especially the stationary ones, have 100 mbit Ethernet and an
Ethernet switch.
Usually the devices have LEDs for status indication, although some have SPI or
I2C connected displays.
Some have an SD card slot. If it exists, it is a better choice for the root
file system because it easily outperforms the built-in NAND.
The LTE interface runs on a separate DSP called ZSP880. It is probably derived
from LSI ZSPs and has an undocumented instruction set. The ZSP communicates
with the main CPU via SRAM and DRAM and a mailbox hardware that can generate
IRQs on either ends.
There is also a Cortex M0 CPU, which is responsible for early HW initialization
and starting the Cortex A53 CPU. It does not have any essential purpose once
U-Boot is started. An SRAM-based handover protocol exists to run custom code on
this CPU.
2. Booting via USB
---------------------------
The Boot ROM has support for booting custom code via USB. This mode can be
entered by connecting a Boot PIN to GND or by modifying the third byte on NAND
(set it to anything other than 0x5A aka 'Z'). A free software tool to start
custom U-Boot and kernels can be found here:
https://github.com/zx297520v3-mainline/zx297520v3-loader
If USB download mode is entered but no boot commands are sent through USB, the
device will proceed to boot normally after a few seconds. It is therefore
possible to enable USB boot permanently and still leave the default boot files
in place.
https://github.com/zx297520v3-mainline/u-boot-mainline
Contains an U-Boot version that can be used with the USB loader and sets up the
CPU and interrupt controller to comply with Linux's booting requirements.
3. Building for built-in U-Boot
-------------------------------
The devices come with an ancient U-Boot that loads legacy uImages from NAND and
boots them without a chance for the user to interrupt. The images are stored in
files ap_cpuap.bin and ap_recovery.bin on a jffs2 partition named imagefs,
usually mtd4. A file named "fotaflag" switches between the two modes.
In addition to the uImage header, those files have a 384-byte signature header,
which is used for authenticating the images on some devices. Most devices have
this authentication disabled and it is enough to pad the uImage files with 384
zero bytes.
Builtin U-Boot also poorly sets up the CPU. Read the next section for details
on this. It has no support for loading DTBs, so CONFIG_ARM_APPENDED_DTB is
needed.
So to build an image that boots from NAND the following steps are necessary:
1) Patch the assembly code from section 3 into arch/arm/kernel/head.S.
2) make zx29_defconfig
3) make [-j x]
4) cat arch/arm/boot/zImage arch/arm/boot/dts/zte/[device].dtb > kernel+dtb
5) mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -d kernel+dtb uimg
6) dd if=/dev/zero bs=1 count=384 of=ap_recovery.bin
7) cat uimg >> ap_recovery.bin
8) Place this file onto imagefs on the device. Delete ap_cpuap.bin if the
free space is not enough.
9) Create the file fotaflag: echo -n FOTA-RECOVERY > fotaflag
For development, booting ap_recovery.bin is recommended because the normal boot
mode arms the watchdog before starting the kernel.
4. CPU and GIC Setup
---------------------------
Generally CPU and GICv3 need to be set up according to the requirements spelled
out in Documentation/arch/arm64/booting.rst. For zx297520v3 this means:
1. GICD_CTLR.DS=1 to disable GIC security
2. Enable access to ICC_SRE
3. Disable trapping IRQs into monitor mode
4. Configure EL2 and below to run in insecure mode.
5. Configure timer PPIs to active-low.
The kernel sources provided by ZTE do not boot either (interrupts do not work
at all). They are incomplete in other aspects too, so it is assumed that there
is some workaround similar to the one described in this document somewhere in
the binary blobs.
The assembly code below is given as an example of how to achieve this:
::
#include <linux/irqchip/arm-gic-v3.h>
#include <asm/assembler.h>
#include <asm/cp15.h>
@ Detect sane bootloaders and skip the hack
ldr r3, =0xf2000000
ldr r3, [r3]
ldr r4, =(GICD_CTLR_ARE_NS | GICD_CTLR_DS)
cmp r3, r4
beq skip_zx_hack
@ This allows EL1 to handle ints hat are normally handled by EL2/3.
ldr r3, =0xf2000000
str r4, [r3]
cps #MON_MODE
@ Work in non-secure physical address space: SCR_EL3.NS = 1. At least the UART
@ seems to respond only to non-secure addresses. I have taken insipiration from
@ Raspberry pi's armstub7.S here.
mov r3, #0x131 @ non-secure, Make F, A bits in CPSR writeable
@ Allow hypervisor call.
mcr p15, 0, r3, c1, c1, 0
@ AP_PPI_MODE_REG: Configure timer PPIs (10, 11, 13, 14) to active-low.
ldr r3, =0xF22020a8
ldr r4, =0x50
str r4, [r3]
ldr r3, =0xF22020ac
ldr r4, =0x14
str r4, [r3]
@ Enable EL2 access to ICC_SRE (bit 3, ICC_SRE_EL3.Enable). Enable system reg
@ access to GICv3 registers (bit 0, ICC_SRE_EL3.SRE) for EL1 and EL3.
mrc p15, 6, r3, c12, c12, 5 @ ICC_SRE_EL3
orr r3, #0x9 @ FIXME: No defines for SRE_EL3 values?
mcr p15, 6, r3, c12, c12, 5
mrc p15, 0, r3, c12, c12, 5 @ ICC_SRE_EL1
orr r3, #(ICC_SRE_EL1_SRE)
mcr p15, 0, r3, c12, c12, 5
@ Like ICC_SRE_EL3, enable EL1 access to ICC_SRE and system register access
@ for EL2.
mrc p15, 4, r3, c12, c9, 5 @ ICC_SRE_EL2 aka ICC_HSRE
orr r3, r3, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
mcr p15, 4, r3, c12, c9, 5
isb
@ Back to SVC mode
cps #SVC_MODE
skip_zx_hack:

13
MAINTAINERS
View File

@ -2643,7 +2643,9 @@ F: arch/arm64/boot/dts/aspeed/
N: aspeed
ARM/AXIADO ARCHITECTURE
M: Harshit Shah <hshah@axiado.com>
M: Prasad Bolisetty <pbolisetty@axiado.com>
M: Tzu-Hao Wei <twei@axiado.com>
M: Karthikeyan Mitran <kmitran@axiado.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/axiado.yaml
@ -3817,6 +3819,15 @@ F: drivers/video/fbdev/vt8500lcdfb.*
F: drivers/video/fbdev/wm8505fb*
F: drivers/video/fbdev/wmt_ge_rops.*
ARM/ZTE ZX29 SOC SUPPORT
M: Stefan Dösinger <stefandoesinger@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Odd fixes
F: Documentation/arch/arm/zte/
F: Documentation/devicetree/bindings/arm/zte.yaml
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@amd.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

2
arch/arm/Kconfig
View File

@ -465,6 +465,8 @@ source "arch/arm/mach-versatile/Kconfig"
source "arch/arm/mach-vt8500/Kconfig"
source "arch/arm/mach-zte/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
# ARMv7-M architecture

1
arch/arm/Makefile
View File

@ -223,6 +223,7 @@ machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += ux500
machine-$(CONFIG_ARCH_VT8500) += vt8500
machine-$(CONFIG_ARCH_ZTE) += zte
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_VERSATILE) += versatile
machine-$(CONFIG_PLAT_SPEAR) += spear

20
arch/arm/boot/compressed/misc-ep93xx.h
View File

@ -3,7 +3,22 @@
* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
*/
#include <asm/mach-types.h>
/*
* These machine IDs are no longer used by the kernel since EP93xx was converted
* to DT booting, but they are still passed in by bootloaders, so we use our own
* local definitions of the relevant macros.
*/
#define machine_is_bk3() (__machine_arch_type == 1880)
#define machine_is_edb9301() (__machine_arch_type == 462)
#define machine_is_edb9302a() (__machine_arch_type == 1127)
#define machine_is_edb9302() (__machine_arch_type == 538)
#define machine_is_edb9307a() (__machine_arch_type == 1128)
#define machine_is_edb9307() (__machine_arch_type == 607)
#define machine_is_edb9312() (__machine_arch_type == 451)
#define machine_is_edb9315a() (__machine_arch_type == 772)
#define machine_is_edb9315() (__machine_arch_type == 463)
#define machine_is_ts72xx() (__machine_arch_type == 673)
#define machine_is_vision_ep9307() (__machine_arch_type == 1578)
static inline unsigned int __raw_readl(unsigned int ptr)
{
@ -60,14 +75,11 @@ static inline void ep93xx_decomp_setup(void)
if (machine_is_edb9301() ||
machine_is_edb9302() ||
machine_is_edb9302a() ||
machine_is_edb9302a() ||
machine_is_edb9307() ||
machine_is_edb9307a() ||
machine_is_edb9307a() ||
machine_is_edb9312() ||
machine_is_edb9315() ||
machine_is_edb9315a() ||
machine_is_edb9315a() ||
machine_is_ts72xx() ||
machine_is_bk3() ||
machine_is_vision_ep9307())

2
arch/arm/common/sa1111.c
View File

@ -221,7 +221,7 @@ static void sa1111_irq_handler(struct irq_desc *desc)
writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
if (stat0 == 0 && stat1 == 0) {
do_bad_IRQ(desc);
handle_bad_irq(desc);
return;
}

1
arch/arm/configs/mvebu_v5_defconfig
View File

@ -15,7 +15,6 @@ CONFIG_MACH_DNS323=y
CONFIG_MACH_TS209=y
CONFIG_MACH_TERASTATION_PRO2=y
CONFIG_MACH_LINKSTATION_PRO=y
CONFIG_MACH_LINKSTATION_LSCHL=y
CONFIG_MACH_LINKSTATION_MINI=y
CONFIG_MACH_TS409=y
CONFIG_MACH_TS78XX=y

10
arch/arm/include/asm/mach/irq.h
View File

@ -17,14 +17,4 @@ struct seq_file;
extern void init_FIQ(int);
extern int show_fiq_list(struct seq_file *, int);
/*
* This is for easy migration, but should be changed in the source
*/
#define do_bad_IRQ(desc) \
do { \
raw_spin_lock(&desc->lock); \
handle_bad_irq(desc); \
raw_spin_unlock(&desc->lock); \
} while(0)
#endif

2
arch/arm/mach-footbridge/isa-irq.c
View File

@ -89,7 +89,7 @@ static void isa_irq_handler(struct irq_desc *desc)
unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
do_bad_IRQ(desc);
handle_bad_irq(desc);
return;
}

9
arch/arm/mach-imx/cpu-imx31.c
View File

@ -36,6 +36,7 @@ static int mx31_read_cpu_rev(void)
void __iomem *iim_base;
struct device_node *np;
u32 i, srev;
int rev = IMX_CHIP_REVISION_UNKNOWN;
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
iim_base = of_iomap(np, 0);
@ -48,13 +49,17 @@ static int mx31_read_cpu_rev(void)
for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
if (srev == mx31_cpu_type[i].srev) {
rev = mx31_cpu_type[i].rev;
imx_print_silicon_rev(mx31_cpu_type[i].name,
mx31_cpu_type[i].rev);
return mx31_cpu_type[i].rev;
goto out;
}
imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
return IMX_CHIP_REVISION_UNKNOWN;
out:
iounmap(iim_base);
return rev;
}
int mx31_revision(void)

2
arch/arm/mach-imx/mm-imx3.c
View File

@ -106,6 +106,7 @@ void __init imx31_init_early(void)
arm_pm_idle = imx31_idle;
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
mx3_ccm_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!mx3_ccm_base);
}
#endif /* ifdef CONFIG_SOC_IMX31 */
@ -143,6 +144,7 @@ void __init imx35_init_early(void)
arch_ioremap_caller = imx3_ioremap_caller;
np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm");
mx3_ccm_base = of_iomap(np, 0);
of_node_put(np);
BUG_ON(!mx3_ccm_base);
}
#endif /* ifdef CONFIG_SOC_IMX35 */

1
arch/arm/mach-mv78xx0/Kconfig
View File

@ -6,6 +6,7 @@ menuconfig ARCH_MV78XX0
depends on ATAGS
select CPU_FEROCEON
select GPIOLIB
select GPIOLIB_LEGACY
select MVEBU_MBUS
select FORCE_PCI
select PLAT_ORION_LEGACY

9
arch/arm/mach-mvebu/coherency.c
View File

@ -133,16 +133,11 @@ static void __init armada_370_coherency_init(struct device_node *np)
cpu_config_np = of_find_compatible_node(NULL, NULL,
"marvell,armada-xp-cpu-config");
if (!cpu_config_np)
goto exit;
cpu_config_base = of_iomap(cpu_config_np, 0);
if (!cpu_config_base) {
of_node_put(cpu_config_np);
goto exit;
}
of_node_put(cpu_config_np);
if (!cpu_config_base)
goto exit;
cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_COHERENCY,
"arm/mvebu/coherency:starting",

29
arch/arm/mach-omap2/omap_device.c
View File

@ -307,35 +307,27 @@ static struct omap_device *omap_device_alloc(struct platform_device *pdev,
int ret = -ENOMEM;
struct omap_device *od;
int i;
struct omap_hwmod **hwmods;
struct omap_hwmod *hwmod;
od = kzalloc_obj(struct omap_device);
if (!od)
goto oda_exit1;
od = kzalloc_flex(*od, hwmods, oh_cnt);
if (!od) {
dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
return ERR_PTR(ret);
}
od->hwmods_cnt = oh_cnt;
memcpy(od->hwmods, ohs, oh_cnt * sizeof(*od->hwmods));
hwmods = kmemdup_array(ohs, oh_cnt, sizeof(*hwmods), GFP_KERNEL);
if (!hwmods)
goto oda_exit2;
od->hwmods = hwmods;
od->pdev = pdev;
pdev->archdata.od = od;
for (i = 0; i < oh_cnt; i++) {
hwmods[i]->od = od;
_add_hwmod_clocks_clkdev(od, hwmods[i]);
hwmod = od->hwmods[i];
hwmod->od = od;
_add_hwmod_clocks_clkdev(od, hwmod);
}
return od;
oda_exit2:
kfree(od);
oda_exit1:
dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
return ERR_PTR(ret);
}
static void omap_device_delete(struct omap_device *od)
@ -344,7 +336,6 @@ static void omap_device_delete(struct omap_device *od)
return;
od->pdev->archdata.od = NULL;
kfree(od->hwmods);
kfree(od);
}

4
arch/arm/mach-omap2/omap_device.h
View File

@ -37,11 +37,11 @@
/**
* struct omap_device - omap_device wrapper for platform_devices
* @pdev: platform_device
* @hwmods: (one .. many per omap_device)
* @hwmods_cnt: ARRAY_SIZE() of @hwmods
* @_state: one of OMAP_DEVICE_STATE_* (see above)
* @flags: device flags
* @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
* @hwmods: (one .. many per omap_device)
*
* Integrates omap_hwmod data into Linux platform_device.
*
@ -51,11 +51,11 @@
*/
struct omap_device {
struct platform_device *pdev;
struct omap_hwmod **hwmods;
unsigned long _driver_status;
u8 hwmods_cnt;
u8 _state;
u8 flags;
struct omap_hwmod *hwmods[] __counted_by(hwmods_cnt);
};
/* Device driver interface (call via platform_data fn ptrs) */

1
arch/arm/mach-orion5x/Kconfig
View File

@ -5,6 +5,7 @@ menuconfig ARCH_ORION5X
depends on CPU_LITTLE_ENDIAN
select CPU_FEROCEON
select GPIOLIB
select GPIOLIB_LEGACY
select MVEBU_MBUS
select FORCE_PCI
select PCI_QUIRKS

4
arch/arm/mach-orion5x/board-mss2.c
View File

@ -10,7 +10,7 @@
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <linux/of.h>
#include <asm/mach/arch.h>
#include <asm/mach/pci.h>
#include "orion5x.h"
@ -47,7 +47,7 @@ static struct hw_pci mss2_pci __initdata = {
static int __init mss2_pci_init(void)
{
if (machine_is_mss2())
if (of_machine_is_compatible("maxtor,shared-storage-2"))
pci_common_init(&mss2_pci);
return 0;

1
arch/arm/mach-pxa/Kconfig
View File

@ -10,6 +10,7 @@ menuconfig ARCH_PXA
select CPU_XSCALE if !CPU_XSC3
select GPIO_PXA
select GPIOLIB
select GPIOLIB_LEGACY
select PLAT_PXA
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.

3
arch/arm/mach-pxa/pxa25x.c
View File

@ -240,6 +240,9 @@ static int __init pxa25x_init(void)
if (!of_have_populated_dt()) {
software_node_register(&pxa2xx_gpiochip_node);
pxa25x_device_gpio.dev.fwnode = software_node_fwnode(
&pxa2xx_gpiochip_node);
pxa2xx_set_dmac_info(&pxa25x_dma_pdata);
ret = platform_add_devices(pxa25x_devices,
ARRAY_SIZE(pxa25x_devices));

3
arch/arm/mach-pxa/pxa27x.c
View File

@ -349,6 +349,9 @@ static int __init pxa27x_init(void)
if (!of_have_populated_dt()) {
software_node_register(&pxa2xx_gpiochip_node);
pxa27x_device_gpio.dev.fwnode = software_node_fwnode(
&pxa2xx_gpiochip_node);
pxa2xx_set_dmac_info(&pxa27x_dma_pdata);
ret = platform_add_devices(devices,
ARRAY_SIZE(devices));

11
arch/arm/mach-pxa/spitz.c
View File

@ -165,7 +165,7 @@ static struct scoop_config spitz_scoop_1_setup = {
.gpio_base = SPITZ_SCP_GPIO_BASE,
};
struct platform_device spitz_scoop_1_device = {
static struct platform_device spitz_scoop_1_device = {
.name = "sharp-scoop",
.id = 0,
.dev = {
@ -192,7 +192,7 @@ static struct scoop_config spitz_scoop_2_setup = {
.gpio_base = SPITZ_SCP2_GPIO_BASE,
};
struct platform_device spitz_scoop_2_device = {
static struct platform_device spitz_scoop_2_device = {
.name = "sharp-scoop",
.id = 1,
.dev = {
@ -204,11 +204,15 @@ struct platform_device spitz_scoop_2_device = {
static void __init spitz_scoop_init(void)
{
spitz_scoop_1_device.dev.fwnode = software_node_fwnode(&spitz_scoop_1_gpiochip_node);
platform_device_register(&spitz_scoop_1_device);
/* Akita doesn't have the second SCOOP chip */
if (!machine_is_akita())
if (!machine_is_akita()) {
spitz_scoop_2_device.dev.fwnode = software_node_fwnode(
&spitz_scoop_2_gpiochip_node);
platform_device_register(&spitz_scoop_2_device);
}
}
/* Power control is shared with between one of the CF slots and SD */
@ -988,6 +992,7 @@ static struct i2c_board_info spitz_i2c_devs[] = {
.type = "max7310",
.addr = 0x18,
.platform_data = &akita_pca953x_pdata,
.swnode = &akita_max7310_gpiochip_node,
},
};

1
arch/arm/mach-s3c/Kconfig.s3c64xx
View File

@ -101,6 +101,7 @@ config MACH_WLF_CRAGG_6410
depends on ATAGS
depends on I2C=y
select CPU_S3C6410
select GPIOLIB_LEGACY
select LEDS_GPIO_REGISTER
select S3C64XX_DEV_SPI0
select S3C64XX_SETUP_FB_24BPP

24
arch/arm/mach-s3c/mach-crag6410.c
View File

@ -779,46 +779,53 @@ static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
static const struct gpio_led gpio_leds[] = {
{
.name = "d13:green:",
.gpio = MMGPIO_GPIO_BASE + 0,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d14:green:",
.gpio = MMGPIO_GPIO_BASE + 1,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d15:green:",
.gpio = MMGPIO_GPIO_BASE + 2,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d16:green:",
.gpio = MMGPIO_GPIO_BASE + 3,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d17:green:",
.gpio = MMGPIO_GPIO_BASE + 4,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d18:green:",
.gpio = MMGPIO_GPIO_BASE + 5,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d19:green:",
.gpio = MMGPIO_GPIO_BASE + 6,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "d20:green:",
.gpio = MMGPIO_GPIO_BASE + 7,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
};
static struct gpiod_lookup_table crag_leds_table = {
.dev_id = "leds-gpio",
.table = {
GPIO_LOOKUP_IDX("basic-mmio-gpio", 0, "cs", 0, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("basic-mmio-gpio", 1, "cs", 1, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("basic-mmio-gpio", 2, "cs", 2, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("basic-mmio-gpio", 3, "cs", 3, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("basic-mmio-gpio", 4, "cs", 4, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("basic-mmio-gpio", 5, "cs", 5, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("basic-mmio-gpio", 6, "cs", 6, GPIO_ACTIVE_LOW),
GPIO_LOOKUP_IDX("basic-mmio-gpio", 7, "cs", 7, GPIO_ACTIVE_LOW),
{ },
},
};
static const struct gpio_led_platform_data gpio_leds_pdata = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
@ -875,6 +882,7 @@ static void __init crag6410_machine_init(void)
platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
platform_device_register_full(&crag6410_mmgpio_devinfo);
gpiod_add_lookup_table(&crag_leds_table);
gpio_led_register_device(-1, &gpio_leds_pdata);
regulator_has_full_constraints();

1
arch/arm/mach-sa1100/Kconfig
View File

@ -13,6 +13,7 @@ menuconfig ARCH_SA1100
select CPU_FREQ
select CPU_SA1100
select GPIOLIB
select GPIOLIB_LEGACY
select IRQ_DOMAIN
select ISA
select NEED_MACH_MEMORY_H

29
arch/arm/mach-zte/Kconfig Normal file
View File

@ -0,0 +1,29 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_ZTE
bool "ZTE zx family"
depends on ARCH_MULTI_V7
help
Support for ZTE zx-based family of processors.
if ARCH_ZTE
config SOC_ZX297520V3
bool "zx297520v3 SoC"
default y
select ARM_GIC_V3
# This board does not have PSCI firmware, but ARM_GIC_V3 depends on
# ARM_PSCI_FW being enabled.
select ARM_PSCI_FW
select ARM_AMBA
select HAVE_ARM_ARCH_TIMER
select PM_GENERIC_DOMAINS if PM
help
Support for ZTE zx297520v3 SoC. It is a single core SoC used in cheap
LTE to WiFi routers. These devices can be identified by the occurrence
of the string "zx297520v3" in the boot output and /proc/cpuinfo of
their stock firmware.
Please read Documentation/arch/arm/zte/zx297520v3.rst on how to boot
the kernel.
endif

2
arch/arm/mach-zte/Makefile Normal file
View File

@ -0,0 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_SOC_ZX297520V3) += zx297520v3.o

16
arch/arm/mach-zte/zx297520v3.c Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2026 Stefan Dösinger
*/
#include <asm/mach/arch.h>
#include <linux/init.h>
static const char *const zx297520v3_dt_compat[] __initconst = {
"zte,zx297520v3",
NULL,
};
DT_MACHINE_START(ZX, "ZTE zx297520v3 (Device Tree)")
.dt_compat = zx297520v3_dt_compat,
MACHINE_END

1
arch/arm64/Kconfig.platforms
View File

@ -249,7 +249,6 @@ config ARCH_MVEBU
select MVEBU_ODMI
select MVEBU_PIC
select MVEBU_SEI
select OF_GPIO
select PINCTRL
select PINCTRL_ARMADA_37XX
select PINCTRL_ARMADA_AP806

2
drivers/firmware/imx/sm-misc.c
View File

@ -16,7 +16,7 @@
static const struct scmi_imx_misc_proto_ops *imx_misc_ctrl_ops;
static struct scmi_protocol_handle *ph;
struct notifier_block scmi_imx_misc_ctrl_nb;
static struct notifier_block scmi_imx_misc_ctrl_nb;
static const char * const rst_imx95[] = {
"cm33_lockup", "cm33_swreq", "cm7_lockup", "cm7_swreq", "fccu",

2
drivers/irqchip/irq-versatile-fpga.c
View File

@ -89,7 +89,7 @@ static void fpga_irq_handle(struct irq_desc *desc)
status = readl(f->base + IRQ_STATUS);
if (status == 0) {
do_bad_IRQ(desc);
handle_bad_irq(desc);
goto out;
}