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net: stmmac: rk: remove need for ->set_speed() method
As we can detect whether the SoC provides the parameters necessary for rk_set_reg_speed(), we don't need to have explicit calls to this. Instead, we can move the contents of this function to rk_set_clk_tx_rate(). This remsoves all the .set_speed() implementations that merely go on to invoke rk_set_reg_speed(). Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vmqnM-00000007VD8-1xWo@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
Jakub Kicinski
parent
33c5c9473a
commit
3cf4dfa7b0
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@ -167,37 +167,6 @@ static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
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return regmap_write(regmap, bsp_priv->clock_grf_reg, val);
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}
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static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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unsigned int val;
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int ret;
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if (phy_interface_mode_is_rgmii(interface)) {
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ret = rk_gmac_rgmii_clk_div(speed);
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if (ret < 0)
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return ret;
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val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
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} else if (interface == PHY_INTERFACE_MODE_RMII) {
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val = rk_encode_wm16(speed == SPEED_100,
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bsp_priv->clock.mac_speed_mask) |
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rk_encode_wm16(speed == SPEED_100,
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bsp_priv->clock.rmii_clk_sel_mask);
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} else {
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/* This should never happen, as .get_interfaces() limits
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* the interface modes that are supported to RGMII and/or
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* RMII.
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*/
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return -EINVAL;
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}
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rk_write_clock_grf_reg(bsp_priv, val);
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return 0;
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}
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static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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@ -368,16 +337,9 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3128_ops = {
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.set_to_rgmii = rk3128_set_to_rgmii,
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.set_to_rmii = rk3128_set_to_rmii,
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.set_speed = rk3128_set_speed,
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.gmac_grf_reg = RK3128_GRF_MAC_CON1,
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.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
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@ -426,12 +388,6 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
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}
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static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
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{
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regmap_write(priv->grf, RK3228_GRF_CON_MUX,
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@ -443,7 +399,6 @@ static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
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static const struct rk_gmac_ops rk3228_ops = {
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.set_to_rgmii = rk3228_set_to_rgmii,
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.set_to_rmii = rk3228_set_to_rmii,
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.set_speed = rk3228_set_speed,
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.integrated_phy_powerup = rk3228_integrated_phy_powerup,
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.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
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@ -485,16 +440,9 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3288_ops = {
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.set_to_rgmii = rk3288_set_to_rgmii,
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.set_to_rmii = rk3288_set_to_rmii,
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.set_speed = rk3288_set_speed,
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.gmac_grf_reg = RK3288_GRF_SOC_CON1,
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.gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
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@ -516,15 +464,8 @@ static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3308_ops = {
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.set_to_rmii = rk3308_set_to_rmii,
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.set_speed = rk3308_set_speed,
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.gmac_grf_reg = RK3308_GRF_MAC_CON0,
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.gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
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@ -586,12 +527,6 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
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{
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regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
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@ -604,7 +539,6 @@ static const struct rk_gmac_ops rk3328_ops = {
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.init = rk3328_init,
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.set_to_rgmii = rk3328_set_to_rgmii,
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.set_to_rmii = rk3328_set_to_rmii,
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.set_speed = rk3328_set_speed,
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.integrated_phy_powerup = rk3328_integrated_phy_powerup,
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.integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
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@ -650,16 +584,9 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3366_ops = {
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.set_to_rgmii = rk3366_set_to_rgmii,
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.set_to_rmii = rk3366_set_to_rmii,
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.set_speed = rk3366_set_speed,
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.gmac_grf_reg = RK3366_GRF_SOC_CON6,
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.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
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@ -699,16 +626,9 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3368_ops = {
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.set_to_rgmii = rk3368_set_to_rgmii,
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.set_to_rmii = rk3368_set_to_rmii,
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.set_speed = rk3368_set_speed,
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.gmac_grf_reg = RK3368_GRF_SOC_CON15,
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.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
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@ -748,16 +668,9 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3399_ops = {
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.set_to_rgmii = rk3399_set_to_rgmii,
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.set_to_rmii = rk3399_set_to_rmii,
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.set_speed = rk3399_set_speed,
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.gmac_grf_reg = RK3399_GRF_SOC_CON5,
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.gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
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@ -804,12 +717,6 @@ static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
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regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
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}
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static int rk3506_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
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bool input, bool enable)
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{
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@ -827,7 +734,6 @@ static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
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static const struct rk_gmac_ops rk3506_ops = {
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.init = rk3506_init,
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.set_to_rmii = rk3506_set_to_rmii,
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.set_speed = rk3506_set_speed,
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.set_clock_selection = rk3506_set_clock_selection,
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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@ -909,12 +815,6 @@ static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
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RK3528_GMAC0_PHY_INTF_SEL_RMII);
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}
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static int rk3528_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
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bool input, bool enable)
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{
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@ -947,7 +847,6 @@ static const struct rk_gmac_ops rk3528_ops = {
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.init = rk3528_init,
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.set_to_rgmii = rk3528_set_to_rgmii,
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.set_to_rmii = rk3528_set_to_rmii,
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.set_speed = rk3528_set_speed,
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.set_clock_selection = rk3528_set_clock_selection,
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.integrated_phy_powerup = rk3528_integrated_phy_powerup,
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.integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
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@ -1100,12 +999,6 @@ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
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bool enable)
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{
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@ -1126,7 +1019,6 @@ static const struct rk_gmac_ops rk3576_ops = {
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.init = rk3576_init,
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.set_to_rgmii = rk3576_set_to_rgmii,
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.set_to_rmii = rk3576_set_to_rmii,
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.set_speed = rk3576_set_gmac_speed,
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.set_clock_selection = rk3576_set_clock_selection,
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.gmac_rmii_mode_mask = BIT_U16(3),
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@ -1215,12 +1107,6 @@ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
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RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
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}
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static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
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bool enable)
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{
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@ -1237,7 +1123,6 @@ static const struct rk_gmac_ops rk3588_ops = {
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.init = rk3588_init,
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.set_to_rgmii = rk3588_set_to_rgmii,
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.set_to_rmii = rk3588_set_to_rmii,
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.set_speed = rk3588_set_gmac_speed,
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.set_clock_selection = rk3588_set_clock_selection,
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.gmac_grf_reg_in_php = true,
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@ -1265,15 +1150,8 @@ static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rv1108_ops = {
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.set_to_rmii = rv1108_set_to_rmii,
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.set_speed = rv1108_set_speed,
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.gmac_grf_reg = RV1108_GRF_GMAC_CON0,
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.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
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@ -1705,11 +1583,37 @@ static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i,
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phy_interface_t interface, int speed)
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{
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struct rk_priv_data *bsp_priv = bsp_priv_;
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int ret = -EINVAL;
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bool is_100m;
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u32 val;
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if (bsp_priv->ops->set_speed)
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return bsp_priv->ops->set_speed(bsp_priv, interface, speed);
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if (bsp_priv->ops->set_speed) {
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ret = bsp_priv->ops->set_speed(bsp_priv, interface, speed);
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if (ret < 0)
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return ret;
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}
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return -EINVAL;
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if (phy_interface_mode_is_rgmii(interface) &&
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bsp_priv->clock.gmii_clk_sel_mask) {
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ret = rk_gmac_rgmii_clk_div(speed);
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if (ret < 0)
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return ret;
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val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
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ret = rk_write_clock_grf_reg(bsp_priv, val);
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} else if (interface == PHY_INTERFACE_MODE_RMII &&
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(bsp_priv->clock.rmii_clk_sel_mask ||
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bsp_priv->clock.mac_speed_mask)) {
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is_100m = speed == SPEED_100;
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val = rk_encode_wm16(is_100m, bsp_priv->clock.mac_speed_mask) |
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rk_encode_wm16(is_100m,
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bsp_priv->clock.rmii_clk_sel_mask);
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ret = rk_write_clock_grf_reg(bsp_priv, val);
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}
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return ret;
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}
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static int rk_gmac_suspend(struct device *dev, void *bsp_priv_)
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