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net: stmmac: rk: use rk_encode_wm16() for RMII clock
The RMII clock is a single bit, which is set for 100M and clear for 10M. Move this out of struct rk_reg_speed_data (which gets rid of this structure) into the struct rk_clock_fields as the bitmask for this bit. This gets rid of the per-SoC variability in the calls to rk_set_reg_speed(). Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vmqnH-00000007VCz-1WmP@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle)
Jakub Kicinski
parent
4dc66f93b4
commit
33c5c9473a
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@ -28,14 +28,10 @@ struct rk_priv_data;
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struct rk_clock_fields {
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u16 gmii_clk_sel_mask;
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u16 rmii_clk_sel_mask;
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u16 mac_speed_mask;
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};
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struct rk_reg_speed_data {
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unsigned int rmii_10;
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unsigned int rmii_100;
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};
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struct rk_gmac_ops {
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int (*init)(struct rk_priv_data *bsp_priv);
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void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
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@ -172,7 +168,6 @@ static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
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}
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static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
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const struct rk_reg_speed_data *rsd,
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phy_interface_t interface, int speed)
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{
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unsigned int val;
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@ -186,17 +181,9 @@ static int rk_set_reg_speed(struct rk_priv_data *bsp_priv,
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val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
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} else if (interface == PHY_INTERFACE_MODE_RMII) {
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val = rk_encode_wm16(speed == SPEED_100,
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bsp_priv->clock.mac_speed_mask);
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if (speed == SPEED_10) {
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val |= rsd->rmii_10;
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} else if (speed == SPEED_100) {
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val |= rsd->rmii_100;
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} else {
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/* Phylink will not allow inappropriate speeds for
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* interface modes, so this should never happen.
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*/
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return -EINVAL;
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}
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bsp_priv->clock.mac_speed_mask) |
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rk_encode_wm16(speed == SPEED_100,
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bsp_priv->clock.rmii_clk_sel_mask);
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} else {
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/* This should never happen, as .get_interfaces() limits
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* the interface modes that are supported to RGMII and/or
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@ -367,8 +354,6 @@ static const struct rk_gmac_ops px30_ops = {
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/* RK3128_GRF_MAC_CON1 */
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#define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
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#define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
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#define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
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#define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
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static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
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int tx_delay, int rx_delay)
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@ -383,16 +368,10 @@ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_reg_speed_data rk3128_reg_speed_data = {
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.rmii_10 = RK3128_GMAC_RMII_CLK_2_5M,
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.rmii_100 = RK3128_GMAC_RMII_CLK_25M,
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};
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static int rk3128_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3128_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3128_ops = {
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@ -406,6 +385,7 @@ static const struct rk_gmac_ops rk3128_ops = {
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.clock_grf_reg = RK3128_GRF_MAC_CON1,
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.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
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.clock.rmii_clk_sel_mask = BIT_U16(11),
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.clock.mac_speed_mask = BIT_U16(10),
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};
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@ -421,8 +401,6 @@ static const struct rk_gmac_ops rk3128_ops = {
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/* RK3228_GRF_MAC_CON1 */
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#define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
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#define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
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#define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
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#define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
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#define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
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#define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
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#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
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@ -448,16 +426,10 @@ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
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regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
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}
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static const struct rk_reg_speed_data rk3228_reg_speed_data = {
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.rmii_10 = RK3228_GMAC_RMII_CLK_2_5M,
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.rmii_100 = RK3228_GMAC_RMII_CLK_25M,
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};
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static int rk3228_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3228_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
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@ -481,6 +453,7 @@ static const struct rk_gmac_ops rk3228_ops = {
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.clock_grf_reg = RK3228_GRF_MAC_CON1,
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.clock.gmii_clk_sel_mask = GENMASK_U16(9, 8),
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.clock.rmii_clk_sel_mask = BIT_U16(7),
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.clock.mac_speed_mask = BIT_U16(2),
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};
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@ -490,8 +463,6 @@ static const struct rk_gmac_ops rk3228_ops = {
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/*RK3288_GRF_SOC_CON1*/
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#define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
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#define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
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#define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
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#define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
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/*RK3288_GRF_SOC_CON3*/
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#define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
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@ -514,16 +485,10 @@ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_reg_speed_data rk3288_reg_speed_data = {
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.rmii_10 = RK3288_GMAC_RMII_CLK_2_5M,
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.rmii_100 = RK3288_GMAC_RMII_CLK_25M,
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};
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static int rk3288_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3288_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3288_ops = {
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@ -537,6 +502,7 @@ static const struct rk_gmac_ops rk3288_ops = {
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.clock_grf_reg = RK3288_GRF_SOC_CON1,
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.clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
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.clock.rmii_clk_sel_mask = BIT_U16(11),
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.clock.mac_speed_mask = BIT_U16(10),
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};
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@ -550,14 +516,10 @@ static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_reg_speed_data rk3308_reg_speed_data = {
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};
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static int rk3308_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3308_ops = {
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@ -583,8 +545,6 @@ static const struct rk_gmac_ops rk3308_ops = {
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/* RK3328_GRF_MAC_CON1 */
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#define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
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#define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
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#define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
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#define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
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#define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
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#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
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@ -626,16 +586,10 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_reg_speed_data rk3328_reg_speed_data = {
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.rmii_10 = RK3328_GMAC_RMII_CLK_2_5M,
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.rmii_100 = RK3328_GMAC_RMII_CLK_25M,
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};
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static int rk3328_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3328_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
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@ -657,6 +611,7 @@ static const struct rk_gmac_ops rk3328_ops = {
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.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
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.gmac_rmii_mode_mask = BIT_U16(9),
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.clock.rmii_clk_sel_mask = BIT_U16(7),
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.clock.mac_speed_mask = BIT_U16(2),
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.regs_valid = true,
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@ -673,8 +628,6 @@ static const struct rk_gmac_ops rk3328_ops = {
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/* RK3366_GRF_SOC_CON6 */
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#define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
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#define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
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#define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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/* RK3366_GRF_SOC_CON7 */
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#define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
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@ -697,16 +650,10 @@ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_reg_speed_data rk3366_reg_speed_data = {
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.rmii_10 = RK3366_GMAC_RMII_CLK_2_5M,
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.rmii_100 = RK3366_GMAC_RMII_CLK_25M,
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};
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static int rk3366_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3366_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3366_ops = {
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@ -720,6 +667,7 @@ static const struct rk_gmac_ops rk3366_ops = {
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.clock_grf_reg = RK3366_GRF_SOC_CON6,
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.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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.clock.mac_speed_mask = BIT_U16(7),
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};
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@ -729,8 +677,6 @@ static const struct rk_gmac_ops rk3366_ops = {
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/* RK3368_GRF_SOC_CON15 */
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#define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
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#define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
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#define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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/* RK3368_GRF_SOC_CON16 */
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#define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
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@ -753,16 +699,10 @@ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_reg_speed_data rk3368_reg_speed_data = {
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.rmii_10 = RK3368_GMAC_RMII_CLK_2_5M,
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.rmii_100 = RK3368_GMAC_RMII_CLK_25M,
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};
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static int rk3368_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3368_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3368_ops = {
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@ -776,6 +716,7 @@ static const struct rk_gmac_ops rk3368_ops = {
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.clock_grf_reg = RK3368_GRF_SOC_CON15,
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.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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.clock.mac_speed_mask = BIT_U16(7),
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};
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@ -785,8 +726,6 @@ static const struct rk_gmac_ops rk3368_ops = {
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/* RK3399_GRF_SOC_CON5 */
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#define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
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#define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
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#define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
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#define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
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/* RK3399_GRF_SOC_CON6 */
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#define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
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@ -809,16 +748,10 @@ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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}
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static const struct rk_reg_speed_data rk3399_reg_speed_data = {
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.rmii_10 = RK3399_GMAC_RMII_CLK_2_5M,
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.rmii_100 = RK3399_GMAC_RMII_CLK_25M,
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};
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static int rk3399_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3399_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static const struct rk_gmac_ops rk3399_ops = {
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@ -832,6 +765,7 @@ static const struct rk_gmac_ops rk3399_ops = {
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.clock_grf_reg = RK3399_GRF_SOC_CON5,
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.clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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.clock.mac_speed_mask = BIT_U16(7),
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};
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@ -840,9 +774,6 @@ static const struct rk_gmac_ops rk3399_ops = {
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#define RK3506_GMAC_RMII_MODE GRF_BIT(1)
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#define RK3506_GMAC_CLK_RMII_DIV2 GRF_BIT(3)
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#define RK3506_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(3)
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#define RK3506_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(5)
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#define RK3506_GMAC_CLK_SELECT_IO GRF_BIT(5)
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@ -873,16 +804,10 @@ static void rk3506_set_to_rmii(struct rk_priv_data *bsp_priv)
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regmap_write(bsp_priv->grf, offset, RK3506_GMAC_RMII_MODE);
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}
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static const struct rk_reg_speed_data rk3506_reg_speed_data = {
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.rmii_10 = RK3506_GMAC_CLK_RMII_DIV20,
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.rmii_100 = RK3506_GMAC_CLK_RMII_DIV2,
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};
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static int rk3506_set_speed(struct rk_priv_data *bsp_priv,
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phy_interface_t interface, int speed)
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{
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return rk_set_reg_speed(bsp_priv, &rk3506_reg_speed_data,
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interface, speed);
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return rk_set_reg_speed(bsp_priv, interface, speed);
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}
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static void rk3506_set_clock_selection(struct rk_priv_data *bsp_priv,
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@ -904,6 +829,9 @@ static const struct rk_gmac_ops rk3506_ops = {
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.set_to_rmii = rk3506_set_to_rmii,
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.set_speed = rk3506_set_speed,
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.set_clock_selection = rk3506_set_clock_selection,
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.clock.rmii_clk_sel_mask = BIT_U16(3),
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.regs_valid = true,
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.regs = {
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0xff4c8000, /* gmac0 */
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|
|
@ -933,11 +861,6 @@ static const struct rk_gmac_ops rk3506_ops = {
|
|||
#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
|
||||
#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
|
||||
|
||||
#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
|
||||
#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
|
||||
#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
|
||||
#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
|
||||
|
||||
#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
|
||||
#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
|
||||
#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
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||||
|
|
@ -948,11 +871,13 @@ static int rk3528_init(struct rk_priv_data *bsp_priv)
|
|||
switch (bsp_priv->id) {
|
||||
case 0:
|
||||
bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
|
||||
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
|
||||
return 0;
|
||||
|
||||
case 1:
|
||||
bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5;
|
||||
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
|
||||
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10);
|
||||
return 0;
|
||||
|
||||
default:
|
||||
|
|
@ -984,27 +909,10 @@ static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|||
RK3528_GMAC0_PHY_INTF_SEL_RMII);
|
||||
}
|
||||
|
||||
static const struct rk_reg_speed_data rk3528_gmac0_reg_speed_data = {
|
||||
.rmii_10 = RK3528_GMAC0_CLK_RMII_DIV20,
|
||||
.rmii_100 = RK3528_GMAC0_CLK_RMII_DIV2,
|
||||
};
|
||||
|
||||
static const struct rk_reg_speed_data rk3528_gmac1_reg_speed_data = {
|
||||
.rmii_10 = RK3528_GMAC1_CLK_RMII_DIV20,
|
||||
.rmii_100 = RK3528_GMAC1_CLK_RMII_DIV2,
|
||||
};
|
||||
|
||||
static int rk3528_set_speed(struct rk_priv_data *bsp_priv,
|
||||
phy_interface_t interface, int speed)
|
||||
{
|
||||
const struct rk_reg_speed_data *rsd;
|
||||
|
||||
if (bsp_priv->id == 1)
|
||||
rsd = &rk3528_gmac1_reg_speed_data;
|
||||
else
|
||||
rsd = &rk3528_gmac0_reg_speed_data;
|
||||
|
||||
return rk_set_reg_speed(bsp_priv, rsd, interface, speed);
|
||||
return rk_set_reg_speed(bsp_priv, interface, speed);
|
||||
}
|
||||
|
||||
static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
|
||||
|
|
@ -1144,9 +1052,6 @@ static const struct rk_gmac_ops rk3568_ops = {
|
|||
#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
|
||||
#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
|
||||
|
||||
#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
|
||||
#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
|
||||
|
||||
#define RK3576_GMAC_CLK_RMII_GATE GRF_BIT(4)
|
||||
#define RK3576_GMAC_CLK_RMII_NOGATE GRF_CLR_BIT(4)
|
||||
|
||||
|
|
@ -1195,16 +1100,10 @@ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|||
{
|
||||
}
|
||||
|
||||
static const struct rk_reg_speed_data rk3578_reg_speed_data = {
|
||||
.rmii_10 = RK3576_GMAC_CLK_RMII_DIV20,
|
||||
.rmii_100 = RK3576_GMAC_CLK_RMII_DIV2,
|
||||
};
|
||||
|
||||
static int rk3576_set_gmac_speed(struct rk_priv_data *bsp_priv,
|
||||
phy_interface_t interface, int speed)
|
||||
{
|
||||
return rk_set_reg_speed(bsp_priv, &rk3578_reg_speed_data,
|
||||
interface, speed);
|
||||
return rk_set_reg_speed(bsp_priv, interface, speed);
|
||||
}
|
||||
|
||||
static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
|
||||
|
|
@ -1233,6 +1132,7 @@ static const struct rk_gmac_ops rk3576_ops = {
|
|||
.gmac_rmii_mode_mask = BIT_U16(3),
|
||||
|
||||
.clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
|
||||
.clock.rmii_clk_sel_mask = BIT_U16(5),
|
||||
|
||||
.php_grf_required = true,
|
||||
.regs_valid = true,
|
||||
|
|
@ -1266,9 +1166,6 @@ static const struct rk_gmac_ops rk3576_ops = {
|
|||
#define RK3588_GMAC_CLK_SELECT_CRU(id) GRF_BIT(5 * (id) + 4)
|
||||
#define RK3588_GMAC_CLK_SELECT_IO(id) GRF_CLR_BIT(5 * (id) + 4)
|
||||
|
||||
#define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2)
|
||||
#define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2)
|
||||
|
||||
#define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1)
|
||||
#define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1)
|
||||
|
||||
|
|
@ -1278,11 +1175,13 @@ static int rk3588_init(struct rk_priv_data *bsp_priv)
|
|||
case 0:
|
||||
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
|
||||
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
|
||||
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
|
||||
return 0;
|
||||
|
||||
case 1:
|
||||
bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
|
||||
bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
|
||||
bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7);
|
||||
return 0;
|
||||
|
||||
default:
|
||||
|
|
@ -1316,27 +1215,10 @@ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
|
|||
RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id));
|
||||
}
|
||||
|
||||
static const struct rk_reg_speed_data rk3588_gmac0_speed_data = {
|
||||
.rmii_10 = RK3588_GMA_CLK_RMII_DIV20(0),
|
||||
.rmii_100 = RK3588_GMA_CLK_RMII_DIV2(0),
|
||||
};
|
||||
|
||||
static const struct rk_reg_speed_data rk3588_gmac1_speed_data = {
|
||||
.rmii_10 = RK3588_GMA_CLK_RMII_DIV20(1),
|
||||
.rmii_100 = RK3588_GMA_CLK_RMII_DIV2(1),
|
||||
};
|
||||
|
||||
static int rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv,
|
||||
phy_interface_t interface, int speed)
|
||||
{
|
||||
const struct rk_reg_speed_data *rsd;
|
||||
|
||||
if (bsp_priv->id == 0)
|
||||
rsd = &rk3588_gmac0_speed_data;
|
||||
else
|
||||
rsd = &rk3588_gmac1_speed_data;
|
||||
|
||||
return rk_set_reg_speed(bsp_priv, rsd, interface, speed);
|
||||
return rk_set_reg_speed(bsp_priv, interface, speed);
|
||||
}
|
||||
|
||||
static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input,
|
||||
|
|
@ -1378,23 +1260,15 @@ static const struct rk_gmac_ops rk3588_ops = {
|
|||
/* RV1108_GRF_GMAC_CON0 */
|
||||
#define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
|
||||
#define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
|
||||
#define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
|
||||
#define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
|
||||
|
||||
static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
|
||||
{
|
||||
}
|
||||
|
||||
static const struct rk_reg_speed_data rv1108_reg_speed_data = {
|
||||
.rmii_10 = RV1108_GMAC_RMII_CLK_2_5M,
|
||||
.rmii_100 = RV1108_GMAC_RMII_CLK_25M,
|
||||
};
|
||||
|
||||
static int rv1108_set_speed(struct rk_priv_data *bsp_priv,
|
||||
phy_interface_t interface, int speed)
|
||||
{
|
||||
return rk_set_reg_speed(bsp_priv, &rv1108_reg_speed_data,
|
||||
interface, speed);
|
||||
return rk_set_reg_speed(bsp_priv, interface, speed);
|
||||
}
|
||||
|
||||
static const struct rk_gmac_ops rv1108_ops = {
|
||||
|
|
@ -1405,6 +1279,7 @@ static const struct rk_gmac_ops rv1108_ops = {
|
|||
.gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
|
||||
|
||||
.clock_grf_reg = RV1108_GRF_GMAC_CON0,
|
||||
.clock.rmii_clk_sel_mask = BIT_U16(7),
|
||||
.clock.mac_speed_mask = BIT_U16(2),
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user