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wifi: rtw89: debug: add PMAC counter in bb_info
PMAC (Pseudo MAC) is a circuit within the baseband that can report various packet-related counters through registers, such as TX ON, TX EN, CCA, FA, CRC, etc. The driver periodically collects per PHY PMAC counters in track_work and exposes them through the bb_info debugfs for easier debugging. The output of PMAC counter: == PMAC TX [CCK_TXEN, CCK_TXON, OFDM_TXEN, OFDM_TXON]: [0, 0, 17, 17] CRC [CCK, OFDM, HT, VHT, HE, EHT, ALL, MPDU] ok: [0, 301, 0, 0, 5, 0, 306, 5] err: [0, 4, 0, 0, 0, 0, 4, 0] CCA [CCK, OFDM]: [0, 353] FA [CCK, OFDM]: [0, 39] CCA spoofing [CCK, OFDM]: [0, 0] CCK SFD: 0, SIG_GG: 0 OFDM Parity: 4, Rate: 2, LSIG_BRK_S: 0, LSIG_BRK_L: 7, SBD: 5 AMPDU miss: 0 Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20260429132625.1659182-5-pkshih@realtek.com
This commit is contained in:
Kuan-Chung Chen
Ping-Ke Shih
parent
523d012f47
commit
3b851f36c3
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@ -4487,6 +4487,54 @@ struct rtw89_edcca_regs {
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u32 tx_collision_t2r_st_mask;
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};
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struct rtw89_pmac_regs {
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struct rtw89_reg_def cck_txon;
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struct rtw89_reg_def cck_txen;
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struct rtw89_reg_def cck_cca;
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struct rtw89_reg_def cck_sfd_gg;
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struct rtw89_reg_def cck_sig_gg;
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struct rtw89_reg_def cck_spoofing;
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struct rtw89_reg_def cck_brk;
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struct rtw89_reg_def brk;
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struct rtw89_reg_def brk_option;
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struct rtw89_reg_def search_fail;
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struct rtw89_reg_def lsig_brk_s_th;
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struct rtw89_reg_def lsig_brk_l_th;
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struct rtw89_reg_def rxl_err_parity;
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struct rtw89_reg_def rxl_err_rate;
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struct rtw89_reg_def ofdm_cca;
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struct rtw89_reg_def cca_spoofing;
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struct rtw89_reg_def ampdu_miss;
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struct rtw89_reg_def r1b_rx_rpt_rst;
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struct rtw89_reg_def r1b_rr_sel;
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struct rtw89_reg_def enable_all_cnt;
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struct rtw89_reg_def rst_all_cnt;
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u32 cck_crc32;
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u32 cck_crc32_ok_mask;
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u32 cck_crc32_fail_mask;
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u32 ofdm_txon;
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u32 ofdm_txon_mask;
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u32 ofdm_txen_mask;
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u32 l_crc;
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u32 l_crc_ok_mask;
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u32 l_crc_err_mask;
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u32 ht_crc;
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u32 ht_crc_ok_mask;
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u32 ht_crc_err_mask;
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u32 vht_crc;
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u32 vht_crc_ok_mask;
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u32 vht_crc_err_mask;
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u32 he_crc;
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u32 he_crc_ok_mask;
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u32 he_crc_err_mask;
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u32 eht_crc;
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u32 eht_crc_ok_mask;
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u32 eht_crc_err_mask;
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u32 ampdu_crc;
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u32 ampdu_crc_ok_mask;
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u32 ampdu_crc_err_mask;
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};
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struct rtw89_phy_ul_tb_info {
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bool dyn_tb_tri_en;
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u8 def_if_bandedge;
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@ -4682,6 +4730,7 @@ struct rtw89_chip_info {
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struct rtw89_sb_regs btc_sb;
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u32 dma_ch_mask;
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const struct rtw89_edcca_regs *edcca_regs;
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const struct rtw89_pmac_regs *pmac_regs;
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const struct wiphy_wowlan_support *wowlan_stub;
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const struct rtw89_xtal_info *xtal_info;
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unsigned long default_quirks; /* bitmap of rtw89_quirks */
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@ -5505,6 +5554,43 @@ struct rtw89_phy_ch_info {
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u8 is_noisy;
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};
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struct rtw89_pmac_stat_info {
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u32 cck_phy_txon;
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u32 cck_mac_txen;
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u32 ofdm_mac_txen;
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u32 ofdm_phy_txon;
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u32 cnt_ofdm_cca;
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u32 cnt_cck_cca;
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u32 cnt_cck_spoofing;
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u32 cnt_ofdm_spoofing;
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u32 cnt_ampdu_miss;
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u32 cnt_ampdu_crc_error;
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u32 cnt_ampdu_crc_ok;
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u32 cnt_cck_crc32_error;
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u32 cnt_cck_crc32_ok;
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u32 cnt_ofdm_crc32_error;
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u32 cnt_ofdm_crc32_ok;
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u32 cnt_ht_crc32_error;
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u32 cnt_ht_crc32_ok;
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u32 cnt_vht_crc32_error;
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u32 cnt_vht_crc32_ok;
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u32 cnt_he_crc32_ok;
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u32 cnt_he_crc32_error;
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u32 cnt_eht_crc32_ok;
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u32 cnt_eht_crc32_error;
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u32 cnt_crc32_error_all;
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u32 cnt_crc32_ok_all;
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u32 cnt_sfd_gg;
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u32 cnt_sig_gg;
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u32 cnt_cck_fail;
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u32 cnt_ofdm_fail;
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u32 cnt_lsig_brk_s_th;
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u32 cnt_lsig_brk_l_th;
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u32 cnt_parity_fail;
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u32 cnt_rate_illegal;
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u32 cnt_sb_search_fail;
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};
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struct rtw89_agc_gaincode_set {
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u8 lna_idx;
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u8 tia_idx;
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@ -6331,6 +6417,7 @@ struct rtw89_dev {
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struct ewma_rssi bcn_rssi;
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struct rtw89_pkt_stat cur_pkt_stat;
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struct rtw89_pkt_stat last_pkt_stat;
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struct rtw89_pmac_stat_info pmac_stat;
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} bbs[RTW89_PHY_NUM];
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struct wiphy_delayed_work track_work;
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@ -4141,10 +4141,43 @@ static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev,
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static int rtw89_get_bb_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb,
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char *buf, size_t bufsz)
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{
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struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat;
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char *p = buf, *end = buf + bufsz;
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p += scnprintf(p, end - p, "\n[PHY %u]\n", bb->phy_idx);
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p += scnprintf(p, end - p, "== PMAC\n");
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p += scnprintf(p, end - p,
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"TX [CCK_TXEN, CCK_TXON, OFDM_TXEN, OFDM_TXON]: [%d, %d, %d, %d]\n",
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pmac->cck_mac_txen, pmac->cck_phy_txon,
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pmac->ofdm_mac_txen, pmac->ofdm_phy_txon);
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p += scnprintf(p, end - p, "CRC [CCK, OFDM, HT, VHT, HE, EHT, ALL, MPDU]\n");
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p += scnprintf(p, end - p, " ok: [%d, %d, %d, %d, %d, %d, %d, %d]\n",
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pmac->cnt_cck_crc32_ok, pmac->cnt_ofdm_crc32_ok,
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pmac->cnt_ht_crc32_ok, pmac->cnt_vht_crc32_ok,
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pmac->cnt_he_crc32_ok, pmac->cnt_eht_crc32_ok,
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pmac->cnt_crc32_ok_all, pmac->cnt_ampdu_crc_ok);
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p += scnprintf(p, end - p, "err: [%d, %d, %d, %d, %d, %d, %d, %d]\n",
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pmac->cnt_cck_crc32_error, pmac->cnt_ofdm_crc32_error,
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pmac->cnt_ht_crc32_error, pmac->cnt_vht_crc32_error,
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pmac->cnt_he_crc32_error, pmac->cnt_eht_crc32_error,
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pmac->cnt_crc32_error_all, pmac->cnt_ampdu_crc_error);
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p += scnprintf(p, end - p, "CCA [CCK, OFDM]: [%d, %d]\n",
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pmac->cnt_cck_cca, pmac->cnt_ofdm_cca);
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p += scnprintf(p, end - p, "FA [CCK, OFDM]: [%d, %d]\n",
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pmac->cnt_cck_fail, pmac->cnt_ofdm_fail);
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p += scnprintf(p, end - p, "CCA spoofing [CCK, OFDM]: [%d, %d]\n",
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pmac->cnt_cck_spoofing, pmac->cnt_ofdm_spoofing);
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p += scnprintf(p, end - p, "CCK SFD: %d, SIG_GG: %d\n",
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pmac->cnt_sfd_gg, pmac->cnt_sig_gg);
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p += scnprintf(p, end - p,
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"OFDM Parity: %d, Rate: %d, LSIG_BRK_S: %d, LSIG_BRK_L: %d, SBD: %d\n",
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pmac->cnt_parity_fail, pmac->cnt_rate_illegal,
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pmac->cnt_lsig_brk_s_th, pmac->cnt_lsig_brk_l_th,
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pmac->cnt_sb_search_fail);
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p += scnprintf(p, end - p, "AMPDU miss: %d\n\n", pmac->cnt_ampdu_miss);
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p += scnprintf(p, end - p, "== RSSI/RX Rate\n");
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p += rtw89_get_rx_pkt_stat(rtwdev, bb, p, end - p);
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@ -5844,6 +5844,196 @@ static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
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rtwdev->hal.thermal_prot_lv = 0;
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}
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static void rtw89_phy_pmac_stat_reset(struct rtw89_dev *rtwdev,
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struct rtw89_bb_ctx *bb, bool cck)
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{
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const struct rtw89_pmac_regs *regs = rtwdev->chip->pmac_regs;
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if (cck) {
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rtw89_phy_write32_clr(rtwdev, regs->r1b_rx_rpt_rst.addr,
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regs->r1b_rx_rpt_rst.mask);
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rtw89_phy_write32_set(rtwdev, regs->r1b_rx_rpt_rst.addr,
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regs->r1b_rx_rpt_rst.mask);
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}
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rtw89_phy_write32_idx_set(rtwdev, regs->enable_all_cnt.addr,
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regs->enable_all_cnt.mask, bb->phy_idx);
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rtw89_phy_write32_idx_set(rtwdev, regs->rst_all_cnt.addr,
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regs->rst_all_cnt.mask, bb->phy_idx);
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rtw89_phy_write32_idx_clr(rtwdev, regs->rst_all_cnt.addr,
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regs->rst_all_cnt.mask, bb->phy_idx);
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}
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static void rtw89_phy_pmac_stat_cck(struct rtw89_dev *rtwdev,
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struct rtw89_bb_ctx *bb)
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{
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const struct rtw89_pmac_regs *regs = rtwdev->chip->pmac_regs;
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struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat;
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const struct rtw89_chip_info *chip = rtwdev->chip;
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u32 val;
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pmac->cck_phy_txon =
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rtw89_phy_read32_mask(rtwdev, regs->cck_txon.addr, regs->cck_txon.mask);
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pmac->cck_mac_txen =
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rtw89_phy_read32_mask(rtwdev, regs->cck_txen.addr, regs->cck_txen.mask);
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if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
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rtw89_phy_write32_mask(rtwdev, regs->r1b_rr_sel.addr,
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regs->r1b_rr_sel.mask, 0x2);
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if (bb->phy_idx == RTW89_PHY_1)
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pmac->cnt_cck_cca =
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rtw89_phy_read32_mask(rtwdev, regs->cck_cca.addr + 8,
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regs->cck_cca.mask);
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else
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pmac->cnt_cck_cca =
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rtw89_phy_read32_mask(rtwdev, regs->cck_cca.addr,
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regs->cck_cca.mask);
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if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
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rtw89_phy_write32_mask(rtwdev, regs->r1b_rr_sel.addr,
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regs->r1b_rr_sel.mask, 0x1);
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if (bb->phy_idx == RTW89_PHY_1)
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val = rtw89_phy_read32(rtwdev, regs->cck_crc32 + 8);
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else
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val = rtw89_phy_read32(rtwdev, regs->cck_crc32);
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pmac->cnt_cck_crc32_ok = field_get(regs->cck_crc32_ok_mask, val);
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pmac->cnt_cck_crc32_error = field_get(regs->cck_crc32_fail_mask, val);
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pmac->cnt_sfd_gg =
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rtw89_phy_read32_idx(rtwdev, regs->cck_sfd_gg.addr,
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regs->cck_sfd_gg.mask, bb->phy_idx);
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pmac->cnt_sig_gg =
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rtw89_phy_read32_idx(rtwdev, regs->cck_sig_gg.addr,
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regs->cck_sig_gg.mask, bb->phy_idx);
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pmac->cnt_cck_spoofing =
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rtw89_phy_read32_idx(rtwdev, regs->cck_spoofing.addr,
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regs->cck_spoofing.mask, bb->phy_idx);
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if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev))
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pmac->cnt_cck_fail =
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pmac->cnt_cck_cca - pmac->cnt_cck_crc32_ok -
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pmac->cnt_cck_crc32_error - pmac->cnt_cck_spoofing;
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else
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pmac->cnt_cck_fail =
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rtw89_phy_read32_idx(rtwdev, regs->cck_brk.addr,
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regs->cck_brk.mask, bb->phy_idx);
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}
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static void rtw89_phy_pmac_stat_ofdm(struct rtw89_dev *rtwdev,
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struct rtw89_bb_ctx *bb)
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{
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const struct rtw89_pmac_regs *regs = rtwdev->chip->pmac_regs;
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struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat;
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const struct rtw89_chip_info *chip = rtwdev->chip;
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u32 val;
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val = rtw89_phy_read32_idx(rtwdev, regs->ofdm_txon, MASKDWORD, bb->phy_idx);
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pmac->ofdm_phy_txon = field_get(regs->ofdm_txon_mask, val);
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pmac->ofdm_mac_txen = field_get(regs->ofdm_txen_mask, val);
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val = rtw89_phy_read32_idx(rtwdev, regs->l_crc, MASKDWORD, bb->phy_idx);
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pmac->cnt_ofdm_crc32_ok = field_get(regs->l_crc_ok_mask, val);
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pmac->cnt_ofdm_crc32_error = field_get(regs->l_crc_err_mask, val);
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val = rtw89_phy_read32_idx(rtwdev, regs->ht_crc, MASKDWORD, bb->phy_idx);
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pmac->cnt_ht_crc32_ok = field_get(regs->ht_crc_ok_mask, val);
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pmac->cnt_ht_crc32_error = field_get(regs->ht_crc_err_mask, val);
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val = rtw89_phy_read32_idx(rtwdev, regs->vht_crc, MASKDWORD, bb->phy_idx);
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pmac->cnt_vht_crc32_ok = field_get(regs->vht_crc_ok_mask, val);
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pmac->cnt_vht_crc32_error = field_get(regs->vht_crc_err_mask, val);
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val = rtw89_phy_read32_idx(rtwdev, regs->he_crc, MASKDWORD, bb->phy_idx);
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pmac->cnt_he_crc32_ok = field_get(regs->he_crc_ok_mask, val);
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pmac->cnt_he_crc32_error = field_get(regs->he_crc_err_mask, val);
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if (chip->chip_gen == RTW89_CHIP_BE) {
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val = rtw89_phy_read32_idx(rtwdev, regs->eht_crc,
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MASKDWORD, bb->phy_idx);
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pmac->cnt_eht_crc32_ok = field_get(regs->eht_crc_ok_mask, val);
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pmac->cnt_eht_crc32_error = field_get(regs->eht_crc_err_mask, val);
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}
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val = rtw89_phy_read32_idx(rtwdev, regs->ampdu_crc, MASKDWORD, bb->phy_idx);
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pmac->cnt_ampdu_crc_ok = field_get(regs->ampdu_crc_ok_mask, val);
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pmac->cnt_ampdu_crc_error = field_get(regs->ampdu_crc_err_mask, val);
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val = rtw89_phy_read32_idx(rtwdev, regs->brk.addr, regs->brk.mask, bb->phy_idx);
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if (chip->chip_id == RTL8852C &&
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rtw89_phy_read32_idx(rtwdev, regs->brk_option.addr,
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regs->brk_option.mask, bb->phy_idx) == 1) {
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u32 tmp = pmac->ofdm_phy_txon + pmac->cck_phy_txon;
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val = (val > tmp) ? (val - tmp) : 0;
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}
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pmac->cnt_ofdm_fail = val;
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pmac->cnt_sb_search_fail =
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rtw89_phy_read32_idx(rtwdev, regs->search_fail.addr,
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regs->search_fail.mask, bb->phy_idx);
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pmac->cnt_lsig_brk_s_th =
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rtw89_phy_read32_idx(rtwdev, regs->lsig_brk_s_th.addr,
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regs->lsig_brk_s_th.mask, bb->phy_idx);
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pmac->cnt_lsig_brk_l_th =
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rtw89_phy_read32_idx(rtwdev, regs->lsig_brk_l_th.addr,
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regs->lsig_brk_l_th.mask, bb->phy_idx);
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pmac->cnt_parity_fail =
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rtw89_phy_read32_idx(rtwdev, regs->rxl_err_parity.addr,
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regs->rxl_err_parity.mask, bb->phy_idx);
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pmac->cnt_rate_illegal =
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rtw89_phy_read32_idx(rtwdev, regs->rxl_err_rate.addr,
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regs->rxl_err_rate.mask, bb->phy_idx);
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pmac->cnt_ofdm_cca =
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rtw89_phy_read32_idx(rtwdev, regs->ofdm_cca.addr,
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regs->ofdm_cca.mask, bb->phy_idx);
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pmac->cnt_ofdm_spoofing =
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rtw89_phy_read32_idx(rtwdev, regs->cca_spoofing.addr,
|
||||
regs->cca_spoofing.mask, bb->phy_idx);
|
||||
pmac->cnt_ampdu_miss =
|
||||
rtw89_phy_read32_idx(rtwdev, regs->ampdu_miss.addr,
|
||||
regs->ampdu_miss.mask, bb->phy_idx);
|
||||
}
|
||||
|
||||
static void rtw89_phy_pmac_stat_update(struct rtw89_dev *rtwdev,
|
||||
struct rtw89_bb_ctx *bb)
|
||||
{
|
||||
struct rtw89_pmac_stat_info *pmac = &bb->pmac_stat;
|
||||
const struct rtw89_chip_info *chip = rtwdev->chip;
|
||||
struct rtw89_entity_conf conf;
|
||||
const struct rtw89_chan *chan;
|
||||
bool cck;
|
||||
|
||||
rtw89_entity_get_conf(rtwdev, &conf);
|
||||
chan = conf.chans[bb->phy_idx];
|
||||
cck = chan->band_type == RTW89_BAND_2G;
|
||||
|
||||
if (cck)
|
||||
rtw89_phy_pmac_stat_cck(rtwdev, bb);
|
||||
|
||||
rtw89_phy_pmac_stat_ofdm(rtwdev, bb);
|
||||
|
||||
pmac->cnt_crc32_error_all = pmac->cnt_he_crc32_error +
|
||||
pmac->cnt_vht_crc32_error +
|
||||
pmac->cnt_ht_crc32_error +
|
||||
pmac->cnt_ofdm_crc32_error +
|
||||
pmac->cnt_cck_crc32_error;
|
||||
|
||||
pmac->cnt_crc32_ok_all = pmac->cnt_he_crc32_ok +
|
||||
pmac->cnt_vht_crc32_ok +
|
||||
pmac->cnt_ht_crc32_ok +
|
||||
pmac->cnt_ofdm_crc32_ok +
|
||||
pmac->cnt_cck_crc32_ok;
|
||||
|
||||
if (chip->chip_gen == RTW89_CHIP_BE) {
|
||||
pmac->cnt_crc32_error_all += pmac->cnt_eht_crc32_error;
|
||||
pmac->cnt_crc32_ok_all += pmac->cnt_eht_crc32_ok;
|
||||
}
|
||||
|
||||
rtw89_phy_pmac_stat_reset(rtwdev, bb, cck);
|
||||
}
|
||||
|
||||
static void rtw89_phy_trigger_tx_count(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
if (RTW89_CHK_FW_FEATURE(TX_HISTORY_V1, &rtwdev->fw))
|
||||
|
|
@ -5854,10 +6044,15 @@ static void rtw89_phy_trigger_tx_count(struct rtw89_dev *rtwdev)
|
|||
|
||||
static void rtw89_phy_stat_update(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
struct rtw89_bb_ctx *bb;
|
||||
|
||||
if (!rtwdev->phy_info.bb_stat_cfg.enable)
|
||||
return;
|
||||
|
||||
rtw89_phy_trigger_tx_count(rtwdev);
|
||||
|
||||
rtw89_for_each_active_bb(rtwdev, bb)
|
||||
rtw89_phy_pmac_stat_update(rtwdev, bb);
|
||||
}
|
||||
|
||||
void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
|
||||
|
|
|
|||
|
|
@ -8799,6 +8799,12 @@
|
|||
#define R_P0_ANT_SW 0x0728
|
||||
#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12)
|
||||
#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0)
|
||||
#define R_RST_ALL_CNT 0x0730
|
||||
#define R_RST_ALL_CNT_BE4 0x20730
|
||||
#define B_RST_ALL_CNT BIT(0)
|
||||
#define R_ENABLE_ALL_CNT 0x0730
|
||||
#define R_ENABLE_ALL_CNT_BE4 0x20730
|
||||
#define B_ENABLE_ALL_CNT BIT(1)
|
||||
#define R_MAC_PIN_SEL 0x0734
|
||||
#define R_MAC_PIN_SEL_BE4 0x20734
|
||||
#define B_CH_IDX_SEG0 GENMASK(23, 16)
|
||||
|
|
@ -8949,6 +8955,8 @@
|
|||
#define B_RXHT_MCS_LIMIT GENMASK(9, 8)
|
||||
#define R_RXVHT_MCS_LIMIT 0x0D18
|
||||
#define B_RXVHT_MCS_LIMIT GENMASK(22, 21)
|
||||
#define R_BRK_OPT 0x0D44
|
||||
#define B_BRK_OPT BIT(31)
|
||||
#define R_P0_EN_SOUND_WO_NDP 0x0D7C
|
||||
#define B_P0_EN_SOUND_WO_NDP BIT(1)
|
||||
#define R_RXHE 0x0D80
|
||||
|
|
@ -9004,6 +9012,21 @@
|
|||
#define R_CFO_COMP_SEG0_L 0x1384
|
||||
#define R_CFO_COMP_SEG0_H 0x1388
|
||||
#define R_CFO_COMP_SEG0_CTRL 0x138C
|
||||
#define R_CNT_CCKTXEN 0x1700
|
||||
#define R_CNT_CCKTXEN_V1 0x2E00
|
||||
#define R_CNT_CCKTXEN_BE4 0x2CF00
|
||||
#define B_CNT_CCKTXEN GENMASK(31, 16)
|
||||
#define R_CNT_CCKTXON 0x1704
|
||||
#define R_CNT_CCKTXON_V1 0x2E04
|
||||
#define R_CNT_CCKTXON_BE4 0x2CF04
|
||||
#define B_CNT_CCKTXON GENMASK(15, 0)
|
||||
#define R_CNT_CCK_CCA_P0 0x1710
|
||||
#define R_CNT_CCK_CCA_P0_V1 0x2E10
|
||||
#define B_CNT_CCK_CCA_P0 GENMASK(15, 0)
|
||||
#define R_CNT_CCK_CRC32_P0 0x1714
|
||||
#define R_CNT_CCK_CRC32_P0_V1 0x2E14
|
||||
#define B_CNT_CCK_CRC32OK_P0 GENMASK(15, 0)
|
||||
#define B_CNT_CCK_CRC32FAIL_P0 GENMASK(31, 16)
|
||||
#define R_DBG32_D 0x1730
|
||||
#define R_EDCCA_RPT_A 0x1738
|
||||
#define R_EDCCA_RPT_B 0x173c
|
||||
|
|
@ -9019,7 +9042,73 @@
|
|||
#define B_SWSI_W_BUSY_V1 BIT(24)
|
||||
#define B_SWSI_R_BUSY_V1 BIT(25)
|
||||
#define B_SWSI_R_DATA_DONE_V1 BIT(26)
|
||||
#define R_CNT_LSIG_BRK_S_TH 0x1A00
|
||||
#define R_CNT_LSIG_BRK_S_TH_V1 0x0E00
|
||||
#define R_CNT_LSIG_BRK_S_TH_BE4 0x20E00
|
||||
#define B_CNT_LSIG_BRK_S_TH GENMASK(31, 16)
|
||||
#define R_CNT_CCA_SPOOFING 0x1A00
|
||||
#define R_CNT_CCA_SPOOFING_V1 0x0E00
|
||||
#define R_CNT_CCA_SPOOFING_BE4 0x20E00
|
||||
#define B_CNT_CCA_SPOOFING GENMASK(15, 0)
|
||||
#define R_CNT_LSIG_BRK_L_TH 0x1A04
|
||||
#define R_CNT_LSIG_BRK_L_TH_V1 0x0E04
|
||||
#define R_CNT_LSIG_BRK_L_TH_BE4 0x20E04
|
||||
#define B_CNT_LSIG_BRK_L_TH GENMASK(15, 0)
|
||||
#define R_CNT_BRK 0x1A08
|
||||
#define R_CNT_BRK_V1 0x0E08
|
||||
#define R_CNT_BRK_BE4 0x20E08
|
||||
#define B_CNT_BRK GENMASK(31, 16)
|
||||
#define R_CNT_RXL_ERR_PARITY 0x1A0C
|
||||
#define R_CNT_RXL_ERR_PARITY_V1 0x0E0C
|
||||
#define R_CNT_RXL_ERR_PARITY_BE4 0x20E0C
|
||||
#define B_CNT_RXL_ERR_PARITY GENMASK(31, 16)
|
||||
#define R_CNT_RXL_ERR_RATE 0x1A10
|
||||
#define R_CNT_RXL_ERR_RATE_V1 0x0E10
|
||||
#define R_CNT_RXL_ERR_RATE_BE4 0x20E10
|
||||
#define B_CNT_RXL_ERR_RATE GENMASK(15, 0)
|
||||
#define R_CNT_SEARCH_FAIL 0x1A20
|
||||
#define R_CNT_SEARCH_FAIL_V1 0x0E20
|
||||
#define R_CNT_SEARCH_FAIL_BE4 0x20E20
|
||||
#define B_CNT_SEARCH_FAIL GENMASK(31, 16)
|
||||
#define R_CNT_OFDM_CCA 0x1A24
|
||||
#define R_CNT_OFDM_CCA_V1 0x0E24
|
||||
#define R_CNT_OFDM_CCA_BE4 0x20E24
|
||||
#define B_CNT_OFDM_CCA GENMASK(15, 0)
|
||||
#define R_TX_COUNTER 0x1A40
|
||||
#define R_CNT_OFDMTXON 0x1A40
|
||||
#define R_CNT_OFDMTXON_V1 0x0E40
|
||||
#define R_CNT_OFDMTXON_BE4 0x20E40
|
||||
#define B_CNT_OFDMTXON GENMASK(15, 0)
|
||||
#define B_CNT_OFDMTXEN GENMASK(31, 16)
|
||||
#define R_CNT_HE_CRC 0x1A58
|
||||
#define R_CNT_HE_CRC_V1 0x0E58
|
||||
#define R_CNT_HE_CRC_BE4 0x20E58
|
||||
#define B_CNT_HE_CRC_OK GENMASK(15, 0)
|
||||
#define B_CNT_HE_CRC_ERR GENMASK(31, 16)
|
||||
#define R_CNT_VHT_CRC 0x1A5C
|
||||
#define R_CNT_VHT_CRC_V1 0x0E5C
|
||||
#define R_CNT_VHT_CRC_BE4 0x20E5C
|
||||
#define B_CNT_VHT_CRC_OK GENMASK(15, 0)
|
||||
#define B_CNT_VHT_CRC_ERR GENMASK(31, 16)
|
||||
#define R_CNT_HT_CRC 0x1A60
|
||||
#define R_CNT_HT_CRC_V1 0x0E60
|
||||
#define R_CNT_HT_CRC_BE4 0x20E60
|
||||
#define B_CNT_HT_CRC_OK GENMASK(15, 0)
|
||||
#define B_CNT_HT_CRC_ERR GENMASK(31, 16)
|
||||
#define R_CNT_L_CRC 0x1A64
|
||||
#define R_CNT_L_CRC_V1 0x0E64
|
||||
#define R_CNT_L_CRC_BE4 0x20E64
|
||||
#define B_CNT_L_CRC_OK GENMASK(15, 0)
|
||||
#define B_CNT_L_CRC_ERR GENMASK(31, 16)
|
||||
#define R_CNT_AMPDU_MISS 0x1A7C
|
||||
#define R_CNT_AMPDU_MISS_V1 0x0E7C
|
||||
#define R_CNT_AMPDU_MISS_BE4 0x20E7C
|
||||
#define B_CNT_AMPDU_MISS GENMASK(31, 16)
|
||||
#define R_CNT_AMPDU_RX_CRC32 0x1A80
|
||||
#define R_CNT_AMPDU_RX_CRC32_V1 0x0E80
|
||||
#define R_CNT_AMPDU_RX_CRC32_BE4 0x20E80
|
||||
#define B_CNT_AMPDU_RX_CRC32_OK GENMASK(15, 0)
|
||||
#define B_CNT_AMPDU_RX_CRC32_ERR GENMASK(31, 16)
|
||||
#define R_NHM_CNT0 0x1A88
|
||||
#define B_NHM_CNT0_MSK GENMASK(15, 0)
|
||||
#define B_NHM_CNT1_MSK GENMASK(31, 16)
|
||||
|
|
@ -9137,12 +9226,41 @@
|
|||
#define B_RXCCA_DIS_V1 BIT(0)
|
||||
#define R_RXSC 0x237C
|
||||
#define B_RXSC_EN BIT(0)
|
||||
#define R_R1B_RR_SEL 0x2388
|
||||
#define B_R1B_RR_SEL GENMASK(24, 23)
|
||||
#define R_R1B_RX_RPT_RST 0x2388
|
||||
#define R_R1B_RX_RPT_RST_V1 0x2340
|
||||
#define R_R1B_RX_RPT_RST_BE 0x0540
|
||||
#define R_R1B_RX_RPT_RST_BE4 0x20540
|
||||
#define B_R1B_RX_RPT_RST BIT(15)
|
||||
#define B_R1B_RX_RPT_RST_V1 BIT(7)
|
||||
#define R_BRK_CNT 0x239C
|
||||
#define R_BRK_CNT_V1 0x059C
|
||||
#define R_BRK_CNT_BE4 0x2059C
|
||||
#define B_BRK_CNT GENMASK(31, 16)
|
||||
#define R_RX_RPL_OFST 0x23AC
|
||||
#define B_RX_RPL_OFST_CCK_MASK GENMASK(6, 0)
|
||||
#define R_RXSCOBC 0x23B0
|
||||
#define B_RXSCOBC_TH GENMASK(18, 0)
|
||||
#define R_RXSCOCCK 0x23B4
|
||||
#define B_RXSCOCCK_TH GENMASK(18, 0)
|
||||
#define R_SFD_GG_CNT 0x23E0
|
||||
#define R_SFD_GG_CNT_V1 0x23A0
|
||||
#define R_SFD_GG_CNT_V2 0x05A0
|
||||
#define R_SFD_GG_CNT_BE4 0x205A0
|
||||
#define B_SFD_GG_CNT GENMASK(15, 0)
|
||||
#define R_SIG_GG_CNT 0x23E8
|
||||
#define R_SIG_GG_CNT_V1 0x23AC
|
||||
#define R_SIG_GG_CNT_V2 0x05AC
|
||||
#define R_SIG_GG_CNT_BE4 0x205AC
|
||||
#define B_SIG_GG_CNT GENMASK(15, 0)
|
||||
#define B_SIG_GG_CNT_V1 GENMASK(15, 8)
|
||||
#define R_SPOOF_CNT 0x23EC
|
||||
#define R_SPOOF_CNT_V1 0x23A8
|
||||
#define R_SPOOF_CNT_V2 0x05A8
|
||||
#define R_SPOOF_CNT_BE4 0x205A8
|
||||
#define B_SPOOF_CNT GENMASK(7, 0)
|
||||
#define B_SPOOF_CNT_V1 GENMASK(31, 16)
|
||||
#define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410
|
||||
#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14)
|
||||
#define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13)
|
||||
|
|
@ -9179,6 +9297,10 @@
|
|||
#define R_EDCCA_RPT_B_BE4_C1 0x2FE34
|
||||
#define R_EDCCA_RPT_P1_A_BE 0x2E40
|
||||
#define R_EDCCA_RPT_P1_B_BE 0x2E44
|
||||
#define R_CNT_EHT_CRC 0x2F00
|
||||
#define R_CNT_EHT_CRC_BE4 0x22F00
|
||||
#define B_CNT_EHT_CRC_OK GENMASK(15, 0)
|
||||
#define B_CNT_EHT_CRC_ERR GENMASK(31, 16)
|
||||
#define R_S1_HW_SI_DIS 0x3200
|
||||
#define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28)
|
||||
#define R_P1_RXCK 0x32A0
|
||||
|
|
@ -10547,6 +10669,11 @@
|
|||
#define R_IFS_T3_HIS_BE4 0x20F54
|
||||
#define B_IFS_T3_HIS_BE4 GENMASK(15, 0)
|
||||
#define B_IFS_T4_HIS_BE4 GENMASK(31, 16)
|
||||
#define R_CNT_CCK_CCA_BE4 0x20FE8
|
||||
#define B_CNT_CCK_CCA_BE4 GENMASK(15, 0)
|
||||
#define R_CNT_CCK_CRC32_BE4 0x20FEC
|
||||
#define B_CNT_CCK_CRC32OK_BE4 GENMASK(15, 0)
|
||||
#define B_CNT_CCK_CRC32FAIL_BE4 GENMASK(31, 16)
|
||||
|
||||
#define R_TX_ERROR_SEL_BE4 0x21254
|
||||
#define B_TX_ERROR_PSDU_BE4 BIT(11)
|
||||
|
|
|
|||
|
|
@ -307,6 +307,54 @@ static const struct rtw89_edcca_regs rtw8851b_edcca_regs = {
|
|||
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
|
||||
};
|
||||
|
||||
static const struct rtw89_pmac_regs rtw8851b_pmac_regs = {
|
||||
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
|
||||
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
|
||||
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
|
||||
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
|
||||
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
|
||||
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
|
||||
.cck_brk = {},
|
||||
.brk = {R_CNT_BRK, B_CNT_BRK},
|
||||
.brk_option = {},
|
||||
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
|
||||
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
|
||||
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
|
||||
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
|
||||
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
|
||||
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
|
||||
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
|
||||
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
|
||||
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
|
||||
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
|
||||
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
|
||||
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
|
||||
.cck_crc32 = R_CNT_CCK_CRC32_P0,
|
||||
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
|
||||
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
|
||||
.ofdm_txon = R_CNT_OFDMTXON,
|
||||
.ofdm_txon_mask = B_CNT_OFDMTXON,
|
||||
.ofdm_txen_mask = B_CNT_OFDMTXEN,
|
||||
.l_crc = R_CNT_L_CRC,
|
||||
.l_crc_ok_mask = B_CNT_L_CRC_OK,
|
||||
.l_crc_err_mask = B_CNT_L_CRC_ERR,
|
||||
.ht_crc = R_CNT_HT_CRC,
|
||||
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
|
||||
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
|
||||
.vht_crc = R_CNT_VHT_CRC,
|
||||
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
|
||||
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
|
||||
.he_crc = R_CNT_HE_CRC,
|
||||
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
|
||||
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
|
||||
.eht_crc = 0,
|
||||
.eht_crc_ok_mask = 0,
|
||||
.eht_crc_err_mask = 0,
|
||||
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
|
||||
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
|
||||
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
|
||||
};
|
||||
|
||||
static const struct rtw89_btc_rf_trx_para rtw89_btc_8851b_rf_ul[] = {
|
||||
{255, 0, 0, 7}, /* 0 -> original */
|
||||
{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
|
||||
|
|
@ -2722,6 +2770,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
|
|||
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
|
||||
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
|
||||
.edcca_regs = &rtw8851b_edcca_regs,
|
||||
.pmac_regs = &rtw8851b_pmac_regs,
|
||||
#ifdef CONFIG_PM
|
||||
.wowlan_stub = &rtw_wowlan_stub_8851b,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -621,6 +621,54 @@ static const struct rtw89_edcca_regs rtw8852a_edcca_regs = {
|
|||
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
|
||||
};
|
||||
|
||||
static const struct rtw89_pmac_regs rtw8852a_pmac_regs = {
|
||||
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
|
||||
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
|
||||
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
|
||||
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
|
||||
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
|
||||
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
|
||||
.cck_brk = {},
|
||||
.brk = {R_CNT_BRK, B_CNT_BRK},
|
||||
.brk_option = {},
|
||||
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
|
||||
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
|
||||
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
|
||||
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
|
||||
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
|
||||
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
|
||||
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
|
||||
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
|
||||
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
|
||||
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
|
||||
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
|
||||
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
|
||||
.cck_crc32 = R_CNT_CCK_CRC32_P0,
|
||||
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
|
||||
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
|
||||
.ofdm_txon = R_CNT_OFDMTXON,
|
||||
.ofdm_txon_mask = B_CNT_OFDMTXON,
|
||||
.ofdm_txen_mask = B_CNT_OFDMTXEN,
|
||||
.l_crc = R_CNT_L_CRC,
|
||||
.l_crc_ok_mask = B_CNT_L_CRC_OK,
|
||||
.l_crc_err_mask = B_CNT_L_CRC_ERR,
|
||||
.ht_crc = R_CNT_HT_CRC,
|
||||
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
|
||||
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
|
||||
.vht_crc = R_CNT_VHT_CRC,
|
||||
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
|
||||
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
|
||||
.he_crc = R_CNT_HE_CRC,
|
||||
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
|
||||
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
|
||||
.eht_crc = 0,
|
||||
.eht_crc_ok_mask = 0,
|
||||
.eht_crc_err_mask = 0,
|
||||
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
|
||||
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
|
||||
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
|
||||
};
|
||||
|
||||
static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
|
||||
struct rtw8852a_efuse *map)
|
||||
{
|
||||
|
|
@ -2459,6 +2507,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
|
|||
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
|
||||
.dma_ch_mask = 0,
|
||||
.edcca_regs = &rtw8852a_edcca_regs,
|
||||
.pmac_regs = &rtw8852a_pmac_regs,
|
||||
#ifdef CONFIG_PM
|
||||
.wowlan_stub = &rtw_wowlan_stub_8852a,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -259,6 +259,54 @@ static const struct rtw89_edcca_regs rtw8852b_edcca_regs = {
|
|||
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
|
||||
};
|
||||
|
||||
static const struct rtw89_pmac_regs rtw8852b_pmac_regs = {
|
||||
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
|
||||
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
|
||||
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
|
||||
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
|
||||
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
|
||||
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
|
||||
.cck_brk = {},
|
||||
.brk = {R_CNT_BRK, B_CNT_BRK},
|
||||
.brk_option = {},
|
||||
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
|
||||
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
|
||||
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
|
||||
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
|
||||
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
|
||||
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
|
||||
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
|
||||
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
|
||||
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
|
||||
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
|
||||
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
|
||||
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
|
||||
.cck_crc32 = R_CNT_CCK_CRC32_P0,
|
||||
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
|
||||
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
|
||||
.ofdm_txon = R_CNT_OFDMTXON,
|
||||
.ofdm_txon_mask = B_CNT_OFDMTXON,
|
||||
.ofdm_txen_mask = B_CNT_OFDMTXEN,
|
||||
.l_crc = R_CNT_L_CRC,
|
||||
.l_crc_ok_mask = B_CNT_L_CRC_OK,
|
||||
.l_crc_err_mask = B_CNT_L_CRC_ERR,
|
||||
.ht_crc = R_CNT_HT_CRC,
|
||||
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
|
||||
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
|
||||
.vht_crc = R_CNT_VHT_CRC,
|
||||
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
|
||||
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
|
||||
.he_crc = R_CNT_HE_CRC,
|
||||
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
|
||||
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
|
||||
.eht_crc = 0,
|
||||
.eht_crc_ok_mask = 0,
|
||||
.eht_crc_err_mask = 0,
|
||||
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
|
||||
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
|
||||
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
|
||||
};
|
||||
|
||||
static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = {
|
||||
{255, 0, 0, 7}, /* 0 -> original */
|
||||
{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
|
||||
|
|
@ -1056,6 +1104,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
|
|||
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
|
||||
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
|
||||
.edcca_regs = &rtw8852b_edcca_regs,
|
||||
.pmac_regs = &rtw8852b_pmac_regs,
|
||||
#ifdef CONFIG_PM
|
||||
.wowlan_stub = &rtw_wowlan_stub_8852b,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -202,6 +202,54 @@ static const struct rtw89_edcca_regs rtw8852bt_edcca_regs = {
|
|||
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
|
||||
};
|
||||
|
||||
static const struct rtw89_pmac_regs rtw8852bt_pmac_regs = {
|
||||
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
|
||||
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
|
||||
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
|
||||
.cck_sfd_gg = {R_SFD_GG_CNT, B_SFD_GG_CNT},
|
||||
.cck_sig_gg = {R_SIG_GG_CNT, B_SIG_GG_CNT},
|
||||
.cck_spoofing = {R_SPOOF_CNT, B_SPOOF_CNT},
|
||||
.cck_brk = {},
|
||||
.brk = {R_CNT_BRK, B_CNT_BRK},
|
||||
.brk_option = {},
|
||||
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
|
||||
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
|
||||
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
|
||||
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
|
||||
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
|
||||
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
|
||||
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
|
||||
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
|
||||
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST, B_R1B_RX_RPT_RST},
|
||||
.r1b_rr_sel = {R_R1B_RR_SEL, B_R1B_RR_SEL},
|
||||
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
|
||||
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
|
||||
.cck_crc32 = R_CNT_CCK_CRC32_P0,
|
||||
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
|
||||
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
|
||||
.ofdm_txon = R_CNT_OFDMTXON,
|
||||
.ofdm_txon_mask = B_CNT_OFDMTXON,
|
||||
.ofdm_txen_mask = B_CNT_OFDMTXEN,
|
||||
.l_crc = R_CNT_L_CRC,
|
||||
.l_crc_ok_mask = B_CNT_L_CRC_OK,
|
||||
.l_crc_err_mask = B_CNT_L_CRC_ERR,
|
||||
.ht_crc = R_CNT_HT_CRC,
|
||||
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
|
||||
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
|
||||
.vht_crc = R_CNT_VHT_CRC,
|
||||
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
|
||||
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
|
||||
.he_crc = R_CNT_HE_CRC,
|
||||
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
|
||||
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
|
||||
.eht_crc = 0,
|
||||
.eht_crc_ok_mask = 0,
|
||||
.eht_crc_err_mask = 0,
|
||||
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
|
||||
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
|
||||
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
|
||||
};
|
||||
|
||||
static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_ul[] = {
|
||||
{255, 0, 0, 7}, /* 0 -> original */
|
||||
{255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
|
||||
|
|
@ -893,6 +941,7 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
|
|||
BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
|
||||
BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
|
||||
.edcca_regs = &rtw8852bt_edcca_regs,
|
||||
.pmac_regs = &rtw8852bt_pmac_regs,
|
||||
#ifdef CONFIG_PM
|
||||
.wowlan_stub = &rtw_wowlan_stub_8852bt,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -270,6 +270,54 @@ static const struct rtw89_edcca_regs rtw8852c_edcca_regs = {
|
|||
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
|
||||
};
|
||||
|
||||
static const struct rtw89_pmac_regs rtw8852c_pmac_regs = {
|
||||
.cck_txon = {R_CNT_CCKTXON, B_CNT_CCKTXON},
|
||||
.cck_txen = {R_CNT_CCKTXEN, B_CNT_CCKTXEN},
|
||||
.cck_cca = {R_CNT_CCK_CCA_P0, B_CNT_CCK_CCA_P0},
|
||||
.cck_sfd_gg = {R_SFD_GG_CNT_V1, B_SFD_GG_CNT},
|
||||
.cck_sig_gg = {R_SIG_GG_CNT_V1, B_SIG_GG_CNT_V1},
|
||||
.cck_spoofing = {R_SPOOF_CNT_V1, B_SPOOF_CNT_V1},
|
||||
.cck_brk = {R_BRK_CNT, B_BRK_CNT},
|
||||
.brk = {R_CNT_BRK, B_CNT_BRK},
|
||||
.brk_option = {R_BRK_OPT, B_BRK_OPT},
|
||||
.search_fail = {R_CNT_SEARCH_FAIL, B_CNT_SEARCH_FAIL},
|
||||
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH, B_CNT_LSIG_BRK_S_TH},
|
||||
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH, B_CNT_LSIG_BRK_L_TH},
|
||||
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY, B_CNT_RXL_ERR_PARITY},
|
||||
.rxl_err_rate = {R_CNT_RXL_ERR_RATE, B_CNT_RXL_ERR_RATE},
|
||||
.ofdm_cca = {R_CNT_OFDM_CCA, B_CNT_OFDM_CCA},
|
||||
.cca_spoofing = {R_CNT_CCA_SPOOFING, B_CNT_CCA_SPOOFING},
|
||||
.ampdu_miss = {R_CNT_AMPDU_MISS, B_CNT_AMPDU_MISS},
|
||||
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_V1, B_R1B_RX_RPT_RST_V1},
|
||||
.r1b_rr_sel = {},
|
||||
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
|
||||
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
|
||||
.cck_crc32 = R_CNT_CCK_CRC32_P0,
|
||||
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
|
||||
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
|
||||
.ofdm_txon = R_CNT_OFDMTXON,
|
||||
.ofdm_txon_mask = B_CNT_OFDMTXON,
|
||||
.ofdm_txen_mask = B_CNT_OFDMTXEN,
|
||||
.l_crc = R_CNT_L_CRC,
|
||||
.l_crc_ok_mask = B_CNT_L_CRC_OK,
|
||||
.l_crc_err_mask = B_CNT_L_CRC_ERR,
|
||||
.ht_crc = R_CNT_HT_CRC,
|
||||
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
|
||||
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
|
||||
.vht_crc = R_CNT_VHT_CRC,
|
||||
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
|
||||
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
|
||||
.he_crc = R_CNT_HE_CRC,
|
||||
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
|
||||
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
|
||||
.eht_crc = 0,
|
||||
.eht_crc_ok_mask = 0,
|
||||
.eht_crc_err_mask = 0,
|
||||
.ampdu_crc = R_CNT_AMPDU_RX_CRC32,
|
||||
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
|
||||
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
|
||||
};
|
||||
|
||||
static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
|
||||
enum rtw89_phy_idx phy_idx);
|
||||
|
||||
|
|
@ -3252,6 +3300,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
|
|||
.btc_sb = {{{R_AX_SCOREBOARD, R_AX_SCOREBOARD},}},
|
||||
.dma_ch_mask = 0,
|
||||
.edcca_regs = &rtw8852c_edcca_regs,
|
||||
.pmac_regs = &rtw8852c_pmac_regs,
|
||||
#ifdef CONFIG_PM
|
||||
.wowlan_stub = &rtw_wowlan_stub_8852c,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -383,6 +383,54 @@ static const struct rtw89_edcca_regs rtw8922a_edcca_regs = {
|
|||
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
|
||||
};
|
||||
|
||||
static const struct rtw89_pmac_regs rtw8922a_pmac_regs = {
|
||||
.cck_txon = {R_CNT_CCKTXON_V1, B_CNT_CCKTXON},
|
||||
.cck_txen = {R_CNT_CCKTXEN_V1, B_CNT_CCKTXEN},
|
||||
.cck_cca = {R_CNT_CCK_CCA_P0_V1, B_CNT_CCK_CCA_P0},
|
||||
.cck_sfd_gg = {R_SFD_GG_CNT_V2, B_SFD_GG_CNT},
|
||||
.cck_sig_gg = {R_SIG_GG_CNT_V2, B_SIG_GG_CNT_V1},
|
||||
.cck_spoofing = {R_SPOOF_CNT_V2, B_SPOOF_CNT_V1},
|
||||
.cck_brk = {R_BRK_CNT_V1, B_BRK_CNT},
|
||||
.brk = {R_CNT_BRK_V1, B_CNT_BRK},
|
||||
.brk_option = {},
|
||||
.search_fail = {R_CNT_SEARCH_FAIL_V1, B_CNT_SEARCH_FAIL},
|
||||
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH_V1, B_CNT_LSIG_BRK_S_TH},
|
||||
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH_V1, B_CNT_LSIG_BRK_L_TH},
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||||
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY_V1, B_CNT_RXL_ERR_PARITY},
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||||
.rxl_err_rate = {R_CNT_RXL_ERR_RATE_V1, B_CNT_RXL_ERR_RATE},
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||||
.ofdm_cca = {R_CNT_OFDM_CCA_V1, B_CNT_OFDM_CCA},
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.cca_spoofing = {R_CNT_CCA_SPOOFING_V1, B_CNT_CCA_SPOOFING},
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.ampdu_miss = {R_CNT_AMPDU_MISS_V1, B_CNT_AMPDU_MISS},
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.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_BE, B_R1B_RX_RPT_RST_V1},
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||||
.r1b_rr_sel = {},
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||||
.enable_all_cnt = {R_ENABLE_ALL_CNT, B_ENABLE_ALL_CNT},
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||||
.rst_all_cnt = {R_RST_ALL_CNT, B_RST_ALL_CNT},
|
||||
.cck_crc32 = R_CNT_CCK_CRC32_P0_V1,
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||||
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_P0,
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||||
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_P0,
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||||
.ofdm_txon = R_CNT_OFDMTXON_V1,
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||||
.ofdm_txon_mask = B_CNT_OFDMTXON,
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||||
.ofdm_txen_mask = B_CNT_OFDMTXEN,
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||||
.l_crc = R_CNT_L_CRC_V1,
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||||
.l_crc_ok_mask = B_CNT_L_CRC_OK,
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||||
.l_crc_err_mask = B_CNT_L_CRC_ERR,
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||||
.ht_crc = R_CNT_HT_CRC_V1,
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||||
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
|
||||
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
|
||||
.vht_crc = R_CNT_VHT_CRC_V1,
|
||||
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
|
||||
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
|
||||
.he_crc = R_CNT_HE_CRC_V1,
|
||||
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
|
||||
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
|
||||
.eht_crc = R_CNT_EHT_CRC,
|
||||
.eht_crc_ok_mask = B_CNT_EHT_CRC_OK,
|
||||
.eht_crc_err_mask = B_CNT_EHT_CRC_ERR,
|
||||
.ampdu_crc = R_CNT_AMPDU_RX_CRC32_V1,
|
||||
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
|
||||
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
|
||||
};
|
||||
|
||||
static const struct rtw89_efuse_block_cfg rtw8922a_efuse_blocks[] = {
|
||||
[RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
|
||||
[RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
|
||||
|
|
@ -3245,6 +3293,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
|
|||
.btc_sb = {{{R_BE_SCOREBOARD, R_BE_SCOREBOARD},}},
|
||||
.dma_ch_mask = 0,
|
||||
.edcca_regs = &rtw8922a_edcca_regs,
|
||||
.pmac_regs = &rtw8922a_pmac_regs,
|
||||
#ifdef CONFIG_PM
|
||||
.wowlan_stub = &rtw_wowlan_stub_8922a,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -227,6 +227,54 @@ static const struct rtw89_edcca_regs rtw8922d_edcca_regs = {
|
|||
.tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
|
||||
};
|
||||
|
||||
static const struct rtw89_pmac_regs rtw8922d_pmac_regs = {
|
||||
.cck_txon = {R_CNT_CCKTXON_BE4, B_CNT_CCKTXON},
|
||||
.cck_txen = {R_CNT_CCKTXEN_BE4, B_CNT_CCKTXEN},
|
||||
.cck_cca = {R_CNT_CCK_CCA_BE4, B_CNT_CCK_CCA_BE4},
|
||||
.cck_sfd_gg = {R_SFD_GG_CNT_BE4, B_SFD_GG_CNT},
|
||||
.cck_sig_gg = {R_SIG_GG_CNT_BE4, B_SIG_GG_CNT_V1},
|
||||
.cck_spoofing = {R_SPOOF_CNT_BE4, B_SPOOF_CNT_V1},
|
||||
.cck_brk = {R_BRK_CNT_BE4, B_BRK_CNT},
|
||||
.brk = {R_CNT_BRK_BE4, B_CNT_BRK},
|
||||
.brk_option = {},
|
||||
.search_fail = {R_CNT_SEARCH_FAIL_BE4, B_CNT_SEARCH_FAIL},
|
||||
.lsig_brk_s_th = {R_CNT_LSIG_BRK_S_TH_BE4, B_CNT_LSIG_BRK_S_TH},
|
||||
.lsig_brk_l_th = {R_CNT_LSIG_BRK_L_TH_BE4, B_CNT_LSIG_BRK_L_TH},
|
||||
.rxl_err_parity = {R_CNT_RXL_ERR_PARITY_BE4, B_CNT_RXL_ERR_PARITY},
|
||||
.rxl_err_rate = {R_CNT_RXL_ERR_RATE_BE4, B_CNT_RXL_ERR_RATE},
|
||||
.ofdm_cca = {R_CNT_OFDM_CCA_BE4, B_CNT_OFDM_CCA},
|
||||
.cca_spoofing = {R_CNT_CCA_SPOOFING_BE4, B_CNT_CCA_SPOOFING},
|
||||
.ampdu_miss = {R_CNT_AMPDU_MISS_BE4, B_CNT_AMPDU_MISS},
|
||||
.r1b_rx_rpt_rst = {R_R1B_RX_RPT_RST_BE4, B_R1B_RX_RPT_RST_V1},
|
||||
.r1b_rr_sel = {},
|
||||
.enable_all_cnt = {R_ENABLE_ALL_CNT_BE4, B_ENABLE_ALL_CNT},
|
||||
.rst_all_cnt = {R_RST_ALL_CNT_BE4, B_RST_ALL_CNT},
|
||||
.cck_crc32 = R_CNT_CCK_CRC32_BE4,
|
||||
.cck_crc32_ok_mask = B_CNT_CCK_CRC32OK_BE4,
|
||||
.cck_crc32_fail_mask = B_CNT_CCK_CRC32FAIL_BE4,
|
||||
.ofdm_txon = R_CNT_OFDMTXON_BE4,
|
||||
.ofdm_txon_mask = B_CNT_OFDMTXON,
|
||||
.ofdm_txen_mask = B_CNT_OFDMTXEN,
|
||||
.l_crc = R_CNT_L_CRC_BE4,
|
||||
.l_crc_ok_mask = B_CNT_L_CRC_OK,
|
||||
.l_crc_err_mask = B_CNT_L_CRC_ERR,
|
||||
.ht_crc = R_CNT_HT_CRC_BE4,
|
||||
.ht_crc_ok_mask = B_CNT_HT_CRC_OK,
|
||||
.ht_crc_err_mask = B_CNT_HT_CRC_ERR,
|
||||
.vht_crc = R_CNT_VHT_CRC_BE4,
|
||||
.vht_crc_ok_mask = B_CNT_VHT_CRC_OK,
|
||||
.vht_crc_err_mask = B_CNT_VHT_CRC_ERR,
|
||||
.he_crc = R_CNT_HE_CRC_BE4,
|
||||
.he_crc_ok_mask = B_CNT_HE_CRC_OK,
|
||||
.he_crc_err_mask = B_CNT_HE_CRC_ERR,
|
||||
.eht_crc = R_CNT_EHT_CRC_BE4,
|
||||
.eht_crc_ok_mask = B_CNT_EHT_CRC_OK,
|
||||
.eht_crc_err_mask = B_CNT_EHT_CRC_ERR,
|
||||
.ampdu_crc = R_CNT_AMPDU_RX_CRC32_BE4,
|
||||
.ampdu_crc_ok_mask = B_CNT_AMPDU_RX_CRC32_OK,
|
||||
.ampdu_crc_err_mask = B_CNT_AMPDU_RX_CRC32_ERR,
|
||||
};
|
||||
|
||||
static const struct rtw89_efuse_block_cfg rtw8922d_efuse_blocks[] = {
|
||||
[RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
|
||||
[RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
|
||||
|
|
@ -3085,6 +3133,7 @@ const struct rtw89_chip_info rtw8922d_chip_info = {
|
|||
BIT(RTW89_DMA_ACH5) | BIT(RTW89_DMA_ACH7) |
|
||||
BIT(RTW89_DMA_B0HI) | BIT(RTW89_DMA_B1HI),
|
||||
.edcca_regs = &rtw8922d_edcca_regs,
|
||||
.pmac_regs = &rtw8922d_pmac_regs,
|
||||
#ifdef CONFIG_PM
|
||||
.wowlan_stub = &rtw_wowlan_stub_8922d,
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user