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wifi: rtw89: debug: bb_info entry including TX rate count for WiFi 7 chips
Enhance TX performance visibility for WiFi 7 chips by introducing TX
rate count tracking. This is critical for debugging and validation.
Additionally, introduce a new debugfs bb_info to enable and provide
baseband status.
Usage of bb_info debugfs:
$ echo enable 1 > bb_info // Start logging BB statistics information
$ echo mac_id 0 > bb_info // Specify mac_id for TX rate count tracking
The output of bb_info:
TP TX: 0 [0] Mbps, RX: 0 [0] Mbps
Avg packet length: TX=118, RX=136
TF: 0
TX count [0]:
Legacy: [0, 0, 0, 0]
OFDM: [0, 0, 0, 0, 0, 0, 0, 0]
MCS 1SS: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
MCS 2SS: [183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
[PHY 0]
== RSSI/RX Rate
Beacon: 19 (-41 dBm)
RX count:
Legacy: [0, 0, 0, 0]
OFDM: [0, 0, 0, 0, 0, 0, 0, 0]
HT 0: [0, 0, 0, 0, 0, 0, 0, 0]
HT 1: [0, 0, 0, 0, 0, 0, 0, 0]
VHT 1SS: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0][0, 0]
VHT 2SS: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0][0, 0]
HE 1SS: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
HE 2SS: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
EHT 1SS: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0][0, 0]
EHT 2SS: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 185]
TX rate [0, 2]: EHT 2SS MCS-0 GI:0.8 FB_G BW:160 (hw_rate=0x420) ==> agg_wait=-1 (1)
RX rate [0, 2]: EHT 2SS MCS-13 GI:0.8 BW:160 (hw_rate=0x42d)
RSSI: -43 dBm (raw=134, prev=135) [-43, -44]
EVM: [38.75, (41.50, 43.00)] SNR: 39
Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260429132625.1659182-4-pkshih@realtek.com
This commit is contained in:
Kuan-Chung Chen
Ping-Ke Shih
parent
09d369c663
commit
523d012f47
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@ -6613,6 +6613,8 @@ int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
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if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
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rtw89_chip_rfk_channel(rtwdev, target);
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rtw89_fw_h2c_tx_history(rtwdev, target->mac_id);
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rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
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wake_queue:
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@ -4511,6 +4511,15 @@ struct rtw89_antdiv_info {
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bool get_stats;
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};
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struct rtw89_bb_stat_cfg {
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bool enable;
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u16 mac_id;
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};
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struct rtw89_phy_info {
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struct rtw89_bb_stat_cfg bb_stat_cfg;
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};
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enum rtw89_chanctx_state {
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RTW89_CHANCTX_STATE_MCC_START,
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RTW89_CHANCTX_STATE_MCC_STOP,
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@ -4831,6 +4840,7 @@ enum rtw89_fw_feature {
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RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C,
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RTW89_FW_FEATURE_LPS_ML_INFO_V1,
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RTW89_FW_FEATURE_SER_POST_RECOVER_DMAC,
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RTW89_FW_FEATURE_TX_HISTORY_V1,
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NUM_OF_RTW89_FW_FEATURES,
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};
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@ -5342,9 +5352,11 @@ struct rtw89_beacon_stat {
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DECLARE_EWMA(thermal, 4, 4);
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#define RTW89_TX_RATE_NR 40
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struct rtw89_phy_stat {
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struct ewma_thermal avg_thermal[RF_PATH_MAX];
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u8 last_thermal_max;
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u32 tx_rate_cnt[RTW89_TX_RATE_NR];
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struct rtw89_beacon_stat bcn_stat;
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};
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@ -6308,6 +6320,7 @@ struct rtw89_dev {
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struct rtw89_phy_efuse_gain efuse_gain;
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struct rtw89_phy_ul_tb_info ul_tb_info;
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struct rtw89_antdiv_info antdiv;
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struct rtw89_phy_info phy_info;
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struct rtw89_bb_ctx {
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enum rtw89_phy_idx phy_idx;
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@ -85,6 +85,7 @@ struct rtw89_debugfs {
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struct rtw89_debugfs_priv btc_manual;
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struct rtw89_debugfs_priv fw_log_manual;
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struct rtw89_debugfs_priv phy_info;
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struct rtw89_debugfs_priv bb_info;
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struct rtw89_debugfs_priv stations;
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struct rtw89_debugfs_priv disable_dm;
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struct rtw89_debugfs_priv static_pd_th;
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@ -4016,15 +4017,15 @@ static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
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}
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static int
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rtw89_debug_append_rx_rate(char *buf, size_t bufsz, struct rtw89_pkt_stat *pkt_stat,
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enum rtw89_hw_rate first_rate, int len)
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rtw89_debug_append_rate(char *buf, size_t bufsz, const u32 *rate_cnt,
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int first_rate, int len)
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{
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char *p = buf, *end = buf + bufsz;
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int i;
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for (i = 0; i < len; i++)
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p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ",
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pkt_stat->rx_rate_cnt[first_rate + i]);
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rate_cnt[first_rate + i]);
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return p - buf;
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}
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@ -4051,6 +4052,17 @@ static const struct rtw89_rx_rate_cnt_info {
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{FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"},
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};
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static const struct rtw89_tx_rate_cnt_info {
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int first_rate;
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int len;
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const char *rate_mode;
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} rtw89_tx_rate_cnt_infos[] = {
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{0, 4, "Legacy:"},
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{4, 8, "OFDM:"},
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{12, 14, "MCS 1SS:"},
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{26, 14, "MCS 2SS:"},
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};
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static int rtw89_get_rx_pkt_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb,
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char *buf, size_t bufsz)
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{
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@ -4075,12 +4087,13 @@ static int rtw89_get_rx_pkt_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *
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continue;
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p += scnprintf(p, end - p, "%10s [", info->rate_mode);
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p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat,
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first_rate, info->len);
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p += rtw89_debug_append_rate(p, end - p, pkt_stat->rx_rate_cnt,
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first_rate, info->len);
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if (info->ext) {
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p += scnprintf(p, end - p, "][");
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p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat,
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first_rate + info->len, info->ext);
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p += rtw89_debug_append_rate(p, end - p, pkt_stat->rx_rate_cnt,
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first_rate + info->len,
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info->ext);
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}
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p += scnprintf(p, end - p, "]\n");
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}
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@ -4125,6 +4138,87 @@ static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev,
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return p - buf;
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}
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static int rtw89_get_bb_stat(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb,
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char *buf, size_t bufsz)
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{
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char *p = buf, *end = buf + bufsz;
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p += scnprintf(p, end - p, "\n[PHY %u]\n", bb->phy_idx);
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p += scnprintf(p, end - p, "== RSSI/RX Rate\n");
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p += rtw89_get_rx_pkt_stat(rtwdev, bb, p, end - p);
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return p - buf;
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}
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static ssize_t
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rtw89_debug_priv_bb_info_get(struct rtw89_dev *rtwdev,
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struct rtw89_debugfs_priv *debugfs_priv,
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char *buf, size_t bufsz)
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{
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struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg;
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struct rtw89_traffic_stats *stats = &rtwdev->stats;
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const struct rtw89_chip_info *chip = rtwdev->chip;
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const struct rtw89_tx_rate_cnt_info *info;
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struct rtw89_debugfs_iter_data iter_data;
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char *p = buf, *end = buf + bufsz;
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struct rtw89_bb_ctx *bb;
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int i;
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p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps, RX: %u [%u] Mbps\n",
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stats->tx_throughput, stats->tx_throughput_raw,
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stats->rx_throughput, stats->rx_throughput_raw);
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p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n",
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stats->tx_avg_len,
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stats->rx_avg_len);
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p += scnprintf(p, end - p, "TF: %u\n", stats->rx_tf_periodic);
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if (chip->chip_gen != RTW89_CHIP_AX) {
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p += scnprintf(p, end - p,
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"TX count [0x%x]:\n", bb_stat->mac_id);
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for (i = 0; i < ARRAY_SIZE(rtw89_tx_rate_cnt_infos); i++) {
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info = &rtw89_tx_rate_cnt_infos[i];
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p += scnprintf(p, end - p, "%10s [", info->rate_mode);
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p += rtw89_debug_append_rate(p, end - p,
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rtwdev->phystat.tx_rate_cnt,
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info->first_rate, info->len);
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p += scnprintf(p, end - p, "]\n");
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}
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}
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rtw89_for_each_active_bb(rtwdev, bb)
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p += rtw89_get_bb_stat(rtwdev, bb, p, end - p);
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p += scnprintf(p, end - p, "\n");
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rtw89_debugfs_iter_data_setup(&iter_data, p, end - p);
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ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data);
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p += iter_data.written_sz;
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return p - buf;
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}
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static ssize_t
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rtw89_debug_priv_bb_info_set(struct rtw89_dev *rtwdev,
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struct rtw89_debugfs_priv *debugfs_priv,
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const char *buf, size_t count)
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{
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struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg;
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int val;
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lockdep_assert_wiphy(rtwdev->hw->wiphy);
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if (sscanf(buf, "enable %d", &val) == 1)
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bb_stat->enable = !!val;
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else if (sscanf(buf, "mac_id %x", &val) == 1)
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rtw89_fw_h2c_tx_history(rtwdev, val);
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else
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return -EINVAL;
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return count;
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}
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static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev,
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char *buf, size_t bufsz,
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struct rtw89_addr_cam_entry *addr_cam)
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@ -5000,6 +5094,7 @@ static const struct rtw89_debugfs rtw89_debugfs_templ = {
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.btc_manual = rtw89_debug_priv_set(btc_manual),
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.fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK),
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.phy_info = rtw89_debug_priv_get(phy_info),
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.bb_info = rtw89_debug_priv_set_and_get(bb_info, RWLOCK),
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.stations = rtw89_debug_priv_get(stations, RLOCK),
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.disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK),
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.static_pd_th = rtw89_debug_priv_set_and_get(static_pd_th, RWLOCK),
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@ -5049,6 +5144,7 @@ void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_top
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rtw89_debugfs_add_w(btc_manual);
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rtw89_debugfs_add_w(fw_log_manual);
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rtw89_debugfs_add_r(phy_info);
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rtw89_debugfs_add_rw(bb_info);
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rtw89_debugfs_add_r(stations);
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rtw89_debugfs_add_rw(disable_dm);
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rtw89_debugfs_add_rw(static_pd_th);
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@ -930,6 +930,7 @@ static const struct __fw_feat_cfg fw_feat_tbl[] = {
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__DIS_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, WITH_RFK_PRE_NOTIFY, G),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 84, 0, RFK_PRE_NOTIFY_MCC_V1),
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__CFG_FW_FEAT(RTL8922A, lt, 0, 35, 84, 0, ADDR_CAM_V0),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 92, 0, TX_HISTORY_V1),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 97, 0, SIM_SER_L0L1_BY_HALT_H2C),
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__CFG_FW_FEAT(RTL8922A, ge, 0, 35, 100, 0, SER_POST_RECOVER_DMAC),
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};
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@ -5588,6 +5589,127 @@ int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi
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return ret;
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}
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int rtw89_fw_h2c_tx_history(struct rtw89_dev *rtwdev, u16 mac_id)
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{
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struct rtw89_bb_stat_cfg *bb_stat = &rtwdev->phy_info.bb_stat_cfg;
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_h2c_ra_tx_history *h2c;
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u32 len = sizeof(*h2c);
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struct sk_buff *skb;
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int ret;
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if (chip->chip_gen == RTW89_CHIP_AX)
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return 0;
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skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
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if (!skb) {
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rtw89_err(rtwdev, "failed to alloc skb for h2c tx history\n");
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return -ENOMEM;
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}
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skb_put(skb, len);
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h2c = (struct rtw89_h2c_ra_tx_history *)skb->data;
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h2c->w0 = le32_encode_bits(mac_id, RTW89_H2C_RA_TX_HISTORY_W0_MACID) |
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le32_encode_bits(0, RTW89_H2C_RA_TX_HISTORY_W0_PER_PPDU);
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rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
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H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA,
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H2C_FUNC_OUTSRC_RA_TX_HISTORY, 0, 0, len);
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ret = rtw89_h2c_tx(rtwdev, skb, false);
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if (ret) {
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rtw89_err(rtwdev, "failed to send h2c\n");
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goto fail;
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}
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bb_stat->mac_id = mac_id;
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return 0;
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fail:
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dev_kfree_skb_any(skb);
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return ret;
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}
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int rtw89_fw_h2c_phy_ch_rpt(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_h2c_ra_phy_ch_rpt *h2c;
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u32 len = sizeof(*h2c);
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struct sk_buff *skb;
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int ret;
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if (chip->chip_gen == RTW89_CHIP_AX)
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return 0;
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skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
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if (!skb) {
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rtw89_err(rtwdev, "failed to alloc skb for h2c phy ch rpt\n");
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return -ENOMEM;
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}
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skb_put(skb, len);
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h2c = (struct rtw89_h2c_ra_phy_ch_rpt *)skb->data;
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h2c->w1 = le32_encode_bits(1, RTW89_H2C_RA_PHY_CH_RPT_W1_RPT_TX_COUNT);
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rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
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H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA,
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H2C_FUNC_OUTSRC_RA_PHY_CH_RPT, 0, 0, len);
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ret = rtw89_h2c_tx(rtwdev, skb, false);
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if (ret) {
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rtw89_err(rtwdev, "failed to send h2c\n");
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goto fail;
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}
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return 0;
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fail:
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dev_kfree_skb_any(skb);
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return ret;
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}
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int rtw89_fw_h2c_drv_ctrl_fw(struct rtw89_dev *rtwdev)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct rtw89_h2c_ra_drv_ctrl_fw *h2c;
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u32 len = sizeof(*h2c);
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struct sk_buff *skb;
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int ret;
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if (chip->chip_gen == RTW89_CHIP_AX)
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return 0;
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skb = rtw89_fw_h2c_alloc_skb_with_hdr(rtwdev, len);
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if (!skb) {
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rtw89_err(rtwdev, "failed to alloc skb for h2c drv ctrl fw\n");
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return -ENOMEM;
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}
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skb_put(skb, len);
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h2c = (struct rtw89_h2c_ra_drv_ctrl_fw *)skb->data;
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h2c->w0 = le32_encode_bits(1, RTW89_H2C_RA_DRV_CTRL_FW_W0_RPT_TX_COUNT);
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rtw89_h2c_pkt_set_hdr(rtwdev, skb, FWCMD_TYPE_H2C,
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||||
H2C_CAT_OUTSRC, H2C_CL_OUTSRC_RA,
|
||||
H2C_FUNC_OUTSRC_RA_DRV_CTRL_FW, 0, 0, len);
|
||||
|
||||
ret = rtw89_h2c_tx(rtwdev, skb, false);
|
||||
if (ret) {
|
||||
rtw89_err(rtwdev, "failed to send h2c\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
dev_kfree_skb_any(skb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type)
|
||||
{
|
||||
struct rtw89_btc *btc = &rtwdev->btc;
|
||||
|
|
|
|||
|
|
@ -471,6 +471,28 @@ struct rtw89_h2c_ra_v1 {
|
|||
#define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)
|
||||
#define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)
|
||||
|
||||
struct rtw89_h2c_ra_tx_history {
|
||||
__le32 w0;
|
||||
} __packed;
|
||||
|
||||
#define RTW89_H2C_RA_TX_HISTORY_W0_MACID GENMASK(15, 0)
|
||||
#define RTW89_H2C_RA_TX_HISTORY_W0_PER_PPDU GENMASK(23, 16)
|
||||
|
||||
struct rtw89_h2c_ra_phy_ch_rpt {
|
||||
__le32 w0;
|
||||
__le32 w1;
|
||||
__le32 w2;
|
||||
__le32 w3;
|
||||
} __packed;
|
||||
|
||||
#define RTW89_H2C_RA_PHY_CH_RPT_W1_RPT_TX_COUNT BIT(10)
|
||||
|
||||
struct rtw89_h2c_ra_drv_ctrl_fw {
|
||||
__le32 w0;
|
||||
} __packed;
|
||||
|
||||
#define RTW89_H2C_RA_DRV_CTRL_FW_W0_RPT_TX_COUNT BIT(13)
|
||||
|
||||
static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)
|
||||
{
|
||||
le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0));
|
||||
|
|
@ -3973,6 +3995,13 @@ struct rtw89_c2h_lps_rpt {
|
|||
*/
|
||||
} __packed;
|
||||
|
||||
struct rtw89_c2h_ra_tx_history {
|
||||
struct rtw89_c2h_hdr hdr;
|
||||
__le32 ra_tbtt_cnt;
|
||||
__le32 tx_rate_tot_cnt_hist[RTW89_TX_RATE_NR];
|
||||
__le32 tx_cat_cnt[3];
|
||||
} __packed;
|
||||
|
||||
struct rtw89_c2h_fw_scan_rpt {
|
||||
struct rtw89_c2h_hdr hdr;
|
||||
u8 phy_idx;
|
||||
|
|
@ -4771,6 +4800,9 @@ enum rtw89_mrc_h2c_func {
|
|||
|
||||
#define H2C_CL_OUTSRC_RA 0x1
|
||||
#define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0
|
||||
#define H2C_FUNC_OUTSRC_RA_TX_HISTORY 0x9
|
||||
#define H2C_FUNC_OUTSRC_RA_PHY_CH_RPT 0xe
|
||||
#define H2C_FUNC_OUTSRC_RA_DRV_CTRL_FW 0xf
|
||||
|
||||
#define H2C_CL_OUTSRC_DM 0x2
|
||||
#define H2C_FUNC_FW_MCC_DIG 0x6
|
||||
|
|
@ -5349,6 +5381,9 @@ int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev,
|
|||
struct rtw89_rx_phy_ppdu *phy_ppdu);
|
||||
int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
|
||||
int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi);
|
||||
int rtw89_fw_h2c_phy_ch_rpt(struct rtw89_dev *rtwdev);
|
||||
int rtw89_fw_h2c_tx_history(struct rtw89_dev *rtwdev, u16 mac_id);
|
||||
int rtw89_fw_h2c_drv_ctrl_fw(struct rtw89_dev *rtwdev);
|
||||
int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type);
|
||||
int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type);
|
||||
int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type);
|
||||
|
|
|
|||
|
|
@ -721,14 +721,21 @@ static void rtw89_ops_vif_cfg_changed(struct ieee80211_hw *hw,
|
|||
|
||||
if (changed & BSS_CHANGED_MLD_VALID_LINKS) {
|
||||
struct rtw89_vif_link *cur = rtw89_get_designated_link(rtwvif);
|
||||
u16 mac_id;
|
||||
|
||||
if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
|
||||
rtw89_chip_rfk_channel(rtwdev, cur);
|
||||
|
||||
if (hweight16(vif->active_links) == 1)
|
||||
if (hweight16(vif->active_links) == 1) {
|
||||
mac_id = cur->mac_id;
|
||||
rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
|
||||
else
|
||||
} else {
|
||||
/* Specify for all MAC ID */
|
||||
mac_id = 0xffff;
|
||||
rtwvif->mlo_mode = RTW89_MLO_MODE_EMLSR;
|
||||
}
|
||||
|
||||
rtw89_fw_h2c_tx_history(rtwdev, mac_id);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3379,12 +3379,24 @@ rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
|
|||
&ra_data);
|
||||
}
|
||||
|
||||
static void
|
||||
rtw89_phy_c2h_tx_history(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
|
||||
{
|
||||
const struct rtw89_c2h_ra_tx_history *history = (const void *)c2h->data;
|
||||
u32 *tx_rate_cnt = rtwdev->phystat.tx_rate_cnt;
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < RTW89_TX_RATE_NR; i++)
|
||||
tx_rate_cnt[i] = le32_to_cpu(history->tx_rate_tot_cnt_hist[i]);
|
||||
}
|
||||
|
||||
static
|
||||
void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
|
||||
struct sk_buff *c2h, u32 len) = {
|
||||
[RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
|
||||
[RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
|
||||
[RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
|
||||
[RTW89_PHY_C2H_FUNC_TX_HISTORY] = rtw89_phy_c2h_tx_history,
|
||||
[RTW89_PHY_C2H_FUNC_ACCELERATE_EN] = rtw89_fw_c2h_dummy_handler,
|
||||
};
|
||||
|
||||
|
|
@ -5832,6 +5844,22 @@ static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
|
|||
rtwdev->hal.thermal_prot_lv = 0;
|
||||
}
|
||||
|
||||
static void rtw89_phy_trigger_tx_count(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
if (RTW89_CHK_FW_FEATURE(TX_HISTORY_V1, &rtwdev->fw))
|
||||
rtw89_fw_h2c_phy_ch_rpt(rtwdev);
|
||||
else
|
||||
rtw89_fw_h2c_drv_ctrl_fw(rtwdev);
|
||||
}
|
||||
|
||||
static void rtw89_phy_stat_update(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
if (!rtwdev->phy_info.bb_stat_cfg.enable)
|
||||
return;
|
||||
|
||||
rtw89_phy_trigger_tx_count(rtwdev);
|
||||
}
|
||||
|
||||
void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
|
||||
{
|
||||
struct rtw89_bb_ctx *bb;
|
||||
|
|
@ -5839,6 +5867,7 @@ void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
|
|||
rtw89_phy_stat_thermal_update(rtwdev);
|
||||
rtw89_phy_thermal_protect(rtwdev);
|
||||
rtw89_phy_stat_rssi_update(rtwdev);
|
||||
rtw89_phy_stat_update(rtwdev);
|
||||
|
||||
rtw89_for_each_active_bb(rtwdev, bb) {
|
||||
bb->last_pkt_stat = bb->cur_pkt_stat;
|
||||
|
|
|
|||
|
|
@ -139,6 +139,7 @@ enum rtw89_phy_c2h_ra_func {
|
|||
RTW89_PHY_C2H_FUNC_STS_RPT,
|
||||
RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
|
||||
RTW89_PHY_C2H_FUNC_TXSTS,
|
||||
RTW89_PHY_C2H_FUNC_TX_HISTORY = 0x4,
|
||||
RTW89_PHY_C2H_FUNC_ACCELERATE_EN = 0x7,
|
||||
|
||||
RTW89_PHY_C2H_FUNC_RA_NUM,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user