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Qualcomm ARM32 DeviceTree updates for v6.6

Browse Source 
GCC and LCC clock controller parent clocks are introduced on MDM9615.
 
 The newly introduced RPM representation is introduced across multiple
 platforms.
 
 Voltage ADC channel names are corrected across multiple platforms.
 
 APQ8064 gains a definition for GSBI4.
 
 The XO clock for SDHCI is corrected, as is the USB node name, on
 IPQ4019. USB node name is also corrected for SDX55.
 
 The correct PMIC is included on SDX65 MTP.
 
 The incorrect spi-max-frequency property is removed from controllers on
 IPQ8064 and MSM8960.
 
 OCMEM and the display subsystem are added to MSM8226.
 
 Reset line is added to the PM8941 and the APQ8074 Dragonboard, while a
 few properties of the Sony Xperia Z2 Tablet touchscreen are corrected.
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Merge tag 'qcom-dts-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM32 DeviceTree updates for v6.6

GCC and LCC clock controller parent clocks are introduced on MDM9615.

The newly introduced RPM representation is introduced across multiple
platforms.

Voltage ADC channel names are corrected across multiple platforms.

APQ8064 gains a definition for GSBI4.

The XO clock for SDHCI is corrected, as is the USB node name, on
IPQ4019. USB node name is also corrected for SDX55.

The correct PMIC is included on SDX65 MTP.

The incorrect spi-max-frequency property is removed from controllers on
IPQ8064 and MSM8960.

OCMEM and the display subsystem are added to MSM8226.

Reset line is added to the PM8941 and the APQ8074 Dragonboard, while a
few properties of the Sony Xperia Z2 Tablet touchscreen are corrected.

* tag 'qcom-dts-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: apq8064: add support to gsbi4 uart
  ARM: dts: qcom: sdx65-mtp: Update the pmic used in sdx65
  ARM: dts: qcom: ipq4019: correct SDHCI XO clock
  ARM: dts: qcom: Use labels with generic node names for ADC channels
  ARM: dts: qcom-mdm9615: specify gcc clocks
  ARM: dts: qcom-mdm9615: specify clocks for the lcc device
  ARM: dts: qcom: msm8974pro-castor: correct touchscreen syna,nosleep-mode
  ARM: dts: qcom: msm8974pro-castor: correct touchscreen function names
  ARM: dts: qcom: msm8974pro-castor: correct inverted X of touchscreen
  ARM: dts: qcom: apq8064: Drop redundant /smd node
  ARM: dts: qcom: Add rpm-proc node for SMD platforms
  ARM: dts: qcom: apq8074-dragonboard: add resin
  ARM: dts: qcom-pm8941: add resin support
  ARM: dts: qcom: minor whitespace cleanup around '='
  ARM: dts: qcom: msm8960: drop spi-max-frequency from controller
  ARM: dts: qcom: ipq8064: drop spi-max-frequency from controller
  ARM: dts: qcom: sdx55: use generic node names for USB
  ARM: dts: qcom: ipq4019: use generic node names for USB
  ARM: dts: qcom: msm8226: Add ocmem
  ARM: dts: qcom: msm8226: Add mdss nodes

Link: https://lore.kernel.org/r/20230818024928.2485173-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-08-21 21:34:26 -04:00
commit 3b6d013cd0
20 changed files with 313 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi
View File

@ -233,6 +233,22 @@ pinconf {
};
};
gsbi4_uart_pin_a: gsbi4-uart-pin-active-state {
rx-pins {
pins = "gpio11";
function = "gsbi4";
drive-strength = <2>;
bias-disable;
};
tx-pins {
pins = "gpio10";
function = "gsbi4";
drive-strength = <4>;
bias-disable;
};
};
gsbi6_uart_2pins: gsbi6_uart_2pins {
mux {
pins = "gpio14", "gpio15";

52
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
View File

@ -226,46 +226,6 @@ smem {
hwlocks = <&sfpb_mutex 3>;
};
smd {
compatible = "qcom,smd";
modem-edge {
interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&l2cc 8 3>;
qcom,smd-edge = <0>;
status = "disabled";
};
q6-edge {
interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&l2cc 8 15>;
qcom,smd-edge = <1>;
status = "disabled";
};
dsps-edge {
interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
qcom,smd-edge = <3>;
status = "disabled";
};
riva-edge {
interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&l2cc 8 25>;
qcom,smd-edge = <6>;
status = "disabled";
};
};
smsm {
compatible = "qcom,smsm";
@ -555,6 +515,18 @@ gsbi4: gsbi@16300000 {
#size-cells = <1>;
ranges;
gsbi4_serial: serial@16340000 {
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16340000 0x100>,
<0x16300000 0x3>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&gsbi4_uart_pin_a>;
pinctrl-names = "default";
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
gsbi4_i2c: i2c@16380000 {
compatible = "qcom,i2c-qup-v1.1.1";
pinctrl-0 = <&i2c4_pins>;

5
arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts
View File

@ -156,6 +156,11 @@ led@7 {
};
};
&pm8941_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&pm8941_wled {
qcom,cs-out;
qcom,switching-freq = <3200>;

6
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
View File

@ -784,10 +784,10 @@ spmi_bus: spmi@fc4cf000 {
};
};
smd {
compatible = "qcom,smd";
rpm: remoteproc {
compatible = "qcom,apq8084-rpm-proc", "qcom,rpm-proc";
rpm {
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;

7
arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
View File

@ -262,10 +262,11 @@ &usb3_hs_phy {
&usb3 {
status = "okay";
dwc3@8a00000 {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
&usb3_dwc {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
&usb2_hs_phy {

43
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
View File

@ -230,9 +230,12 @@ sdhci: mmc@7824900 {
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_DCD_XO_CLK>;
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo>;
clock-names = "iface",
"core",
"xo";
status = "disabled";
};
@ -416,10 +419,10 @@ restart@4ab000 {
pcie0: pci@40000000 {
compatible = "qcom,pcie-ipq4019";
reg = <0x40000000 0xf1d
0x40000f20 0xa8
0x80000 0x2000
0x40100000 0x1000>;
reg = <0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x80000 0x2000>,
<0x40100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
@ -543,9 +546,9 @@ wifi0: wifi@a000000 {
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
"msi12", "msi13", "msi14", "msi15",
"legacy";
status = "disabled";
@ -585,9 +588,9 @@ wifi1: wifi@a800000 {
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
"msi12", "msi13", "msi14", "msi15",
"legacy";
status = "disabled";
@ -621,7 +624,7 @@ ethphy4: ethernet-phy@4 {
};
};
usb3_ss_phy: ssphy@9a000 {
usb3_ss_phy: usb-phy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;
reg = <0x9a000 0x800>;
@ -631,7 +634,7 @@ usb3_ss_phy: ssphy@9a000 {
status = "disabled";
};
usb3_hs_phy: hsphy@a6000 {
usb3_hs_phy: usb-phy@a6000 {
compatible = "qcom,usb-hs-ipq4019-phy";
#phy-cells = <0>;
reg = <0xa6000 0x40>;
@ -641,7 +644,7 @@ usb3_hs_phy: hsphy@a6000 {
status = "disabled";
};
usb3: usb3@8af8800 {
usb3: usb@8af8800 {
compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
reg = <0x8af8800 0x100>;
#address-cells = <1>;
@ -653,7 +656,7 @@ usb3: usb3@8af8800 {
ranges;
status = "disabled";
dwc3@8a00000 {
usb3_dwc: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xf8000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
@ -663,7 +666,7 @@ dwc3@8a00000 {
};
};
usb2_hs_phy: hsphy@a8000 {
usb2_hs_phy: usb-phy@a8000 {
compatible = "qcom,usb-hs-ipq4019-phy";
#phy-cells = <0>;
reg = <0xa8000 0x40>;
@ -673,7 +676,7 @@ usb2_hs_phy: hsphy@a8000 {
status = "disabled";
};
usb2: usb2@60f8800 {
usb2: usb@60f8800 {
compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
reg = <0x60f8800 0x100>;
#address-cells = <1>;
@ -685,7 +688,7 @@ usb2: usb2@60f8800 {
ranges;
status = "disabled";
dwc3@6000000 {
usb@6000000 {
compatible = "snps,dwc3";
reg = <0x6000000 0xf8000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

1
arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts
View File

@ -282,7 +282,6 @@ gsbi5: gsbi@1a200000 {
spi4: spi@1a280000 {
status = "okay";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";

1
arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi
View File

@ -30,7 +30,6 @@ gsbi5: gsbi@1a200000 {
spi4: spi@1a280000 {
status = "okay";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";

19
arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
View File

@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
#include <dt-bindings/clock/qcom,lcc-msm8960.h>
#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>
@ -39,7 +40,7 @@ cpu-pmu {
};
clocks {
cxo_board {
cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
@ -106,6 +107,8 @@ gcc: clock-controller@900000 {
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x900000 0x4000>;
clocks = <&cxo_board>,
<&lcc PLL4>;
};
lcc: clock-controller@28000000 {
@ -113,6 +116,20 @@ lcc: clock-controller@28000000 {
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&cxo_board>,
<&gcc PLL4_VOTE>,
<0>,
<0>, <0>,
<0>, <0>,
<0>;
clock-names = "cxo",
"pll4_vote",
"mi2s_codec_clk",
"codec_i2s_mic_codec_clk",
"spare_i2s_mic_codec_clk",
"codec_i2s_spkr_codec_clk",
"spare_i2s_spkr_codec_clk",
"pcm_codec_clk";
};
l2cc: clock-controller@2011000 {

182
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
View File

@ -53,26 +53,10 @@ pmu {
IRQ_TYPE_LEVEL_HIGH)>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rpm: remoteproc {
compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";
smem_region: smem@3000000 {
reg = <0x3000000 0x100000>;
no-map;
};
adsp_region: adsp@dc00000 {
reg = <0x0dc00000 0x1900000>;
no-map;
};
};
smd {
compatible = "qcom,smd";
rpm {
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
@ -120,6 +104,22 @@ rpmpd_opp_super_turbo: opp6 {
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
smem_region: smem@3000000 {
reg = <0x3000000 0x100000>;
no-map;
};
adsp_region: adsp@dc00000 {
reg = <0x0dc00000 0x1900000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
@ -784,6 +784,23 @@ smd-edge {
};
};
sram@fdd00000 {
compatible = "qcom,msm8226-ocmem";
reg = <0xfdd00000 0x2000>,
<0xfec00000 0x20000>;
reg-names = "ctrl", "mem";
ranges = <0 0xfec00000 0x20000>;
clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <1>;
gmu_sram: gmu-sram@0 {
reg = <0x0 0x20000>;
};
};
sram@fe805000 {
compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
reg = <0xfe805000 0x1000>;
@ -797,6 +814,133 @@ reboot-mode {
mode-recovery = <0x77665502>;
};
};
mdss: display-subsystem@fd900000 {
compatible = "qcom,mdss";
reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
reg-names = "mdss_phys", "vbif_phys";
power-domains = <&mmcc MDSS_GDSC>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"vsync";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
mdss_mdp: display-controller@fd900000 {
compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
reg = <0xfd900100 0x22000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_mdp_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
};
};
mdss_dsi0: dsi@fd922800 {
compatible = "qcom,msm8226-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
reg = <0xfd922800 0x1f8>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
<&mmcc PCLK0_CLK_SRC>;
assigned-clock-parents = <&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc MMSS_MISC_AHB_CLK>;
clock-names = "mdp_core",
"iface",
"bus",
"byte",
"pixel",
"core",
"core_mmss";
phys = <&mdss_dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&mdss_mdp_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
};
};
};
};
mdss_dsi0_phy: phy@fd922a00 {
compatible = "qcom,dsi-phy-28nm-8226";
reg = <0xfd922a00 0xd4>,
<0xfd922b00 0x280>,
<0xfd922d80 0x30>;
reg-names = "dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface",
"ref";
};
};
};
thermal-zones {

1
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
View File

@ -364,7 +364,6 @@ gsbi1_spi: spi@16080000 {
#size-cells = <0>;
reg = <0x16080000 0x1000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <24000000>;
cs-gpios = <&msmgpio 8 0>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;

44
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
View File

@ -113,6 +113,28 @@ pmu {
interrupts = <GIC_PPI 7 0xf04>;
};
rpm: remoteproc {
compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
smd-edge {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8974";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};
};
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
@ -293,28 +315,6 @@ wcnss_smsm: wcnss@7 {
};
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8974";
qcom,smd-channels = "rpm_requests";
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
#clock-cells = <1>;
clocks = <&xo_board>;
clock-names = "xo";
};
};
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts
View File

@ -414,7 +414,7 @@ cmd-data-pins {
wcnss_pin_a: wcnss-pin-active-state {
wlan-pins {
pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40";
function = "wlan";
drive-strength = <6>;

8
arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts
View File

@ -125,15 +125,15 @@ synaptics@2c {
syna,startup-delay-ms = <100>;
rmi-f01@1 {
rmi4-f01@1 {
reg = <0x1>;
syna,nosleep = <1>;
syna,nosleep-mode = <1>;
};
rmi-f11@11 {
rmi4-f11@11 {
reg = <0x11>;
syna,f11-flip-x = <1>;
syna,sensor-type = <1>;
touchscreen-inverted-x;
};
};
};

12
arch/arm/boot/dts/qcom/qcom-pm8226.dtsi
View File

@ -102,27 +102,27 @@ pm8226_vadc: adc@3100 {
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@7 {
channel@7 {
reg = <VADC_VSYS>;
qcom,pre-scaling = <1 3>;
label = "vph_pwr";
};
adc-chan@8 {
channel@8 {
reg = <VADC_DIE_TEMP>;
label = "die_temp";
};
adc-chan@9 {
channel@9 {
reg = <VADC_REF_625MV>;
label = "ref_625mv";
};
adc-chan@a {
channel@a {
reg = <VADC_REF_1250MV>;
label = "ref_1250mv";
};
adc-chan@e {
channel@e {
reg = <VADC_GND_REF>;
};
adc-chan@f {
channel@f {
reg = <VADC_VDD_VADC>;
};
};

36
arch/arm/boot/dts/qcom/qcom-pm8941.dtsi
View File

@ -50,12 +50,24 @@ rtc@6000 {
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pwrkey@800 {
compatible = "qcom,pm8941-pwrkey";
pon@800 {
compatible = "qcom,pm8941-pon";
reg = <0x800>;
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
};
pm8941_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
usb_id: usb-detect@900 {
@ -133,31 +145,31 @@ pm8941_vadc: adc@3100 {
#io-channel-cells = <1>;
adc-chan@6 {
channel@6 {
reg = <VADC_VBAT_SNS>;
};
adc-chan@8 {
channel@8 {
reg = <VADC_DIE_TEMP>;
};
adc-chan@9 {
channel@9 {
reg = <VADC_REF_625MV>;
};
adc-chan@a {
channel@a {
reg = <VADC_REF_1250MV>;
};
adc-chan@e {
channel@e {
reg = <VADC_GND_REF>;
};
adc-chan@f {
channel@f {
reg = <VADC_VDD_VADC>;
};
adc-chan@30 {
channel@30 {
reg = <VADC_LR_MUX1_BAT_THERM>;
};
};

12
arch/arm/boot/dts/qcom/qcom-pma8084.dtsi
View File

@ -64,27 +64,27 @@ pma8084_vadc: adc@3100 {
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@8 {
channel@8 {
reg = <VADC_DIE_TEMP>;
};
adc-chan@9 {
channel@9 {
reg = <VADC_REF_625MV>;
};
adc-chan@a {
channel@a {
reg = <VADC_REF_1250MV>;
};
adc-chan@c {
channel@c {
reg = <VADC_SPARE1>;
};
adc-chan@e {
channel@e {
reg = <VADC_GND_REF>;
};
adc-chan@f {
channel@f {
reg = <VADC_VDD_VADC>;
};
};

8
arch/arm/boot/dts/qcom/qcom-pmx55.dtsi
View File

@ -40,25 +40,25 @@ pmx55_adc: adc@3100 {
#io-channel-cells = <1>;
interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
ref-gnd@0 {
channel@0 {
reg = <ADC5_REF_GND>;
qcom,pre-scaling = <1 1>;
label = "ref_gnd";
};
vref-1p25@1 {
channel@1 {
reg = <ADC5_1P25VREF>;
qcom,pre-scaling = <1 1>;
label = "vref_1p25";
};
die-temp@6 {
channel@6 {
reg = <ADC5_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "die_temp";
};
chg-temp@9 {
channel@9 {
reg = <ADC5_CHG_TEMP>;
qcom,pre-scaling = <1 1>;
label = "chg_temp";

2
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
View File

@ -603,7 +603,7 @@ usb: usb@a6f8800 {
resets = <&gcc GCC_USB30_BCR>;
usb_dwc3: dwc3@a600000 {
usb_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0x0a600000 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts
View File

@ -7,7 +7,7 @@
#include "qcom-sdx65.dtsi"
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <arm64/qcom/pmk8350.dtsi>
#include <arm64/qcom/pm8150b.dtsi>
#include <arm64/qcom/pm7250b.dtsi>
#include "qcom-pmx65.dtsi"
/ {