From d5fb01ad5eb449ccfd950e946a882639cad168b3 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 1 Jun 2023 19:00:14 +0200 Subject: [PATCH 01/20] ARM: dts: qcom: msm8226: Add mdss nodes Add the nodes that describe the mdss so that display can work on MSM8226. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230308-msm8226-mdp-v3-7-b6284145d67a@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 127 +++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 313a726f4704..b6e2ca04a233 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -797,6 +797,133 @@ reboot-mode { mode-recovery = <0x77665502>; }; }; + + mdss: display-subsystem@fd900000 { + compatible = "qcom,mdss"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@fd900000 { + compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; + reg = <0xfd900100 0x22000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@fd922800 { + compatible = "qcom,msm8226-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922800 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-8226"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x280>, + <0xfd922d80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + }; + }; }; thermal-zones { From 4bad24d73abcc6adf70bc4c894c29cb1d0acda05 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 14 Jun 2023 18:35:52 +0200 Subject: [PATCH 02/20] ARM: dts: qcom: msm8226: Add ocmem Add a node for the ocmem found on msm8226. It contains one region, used as gmu_ram. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230506-msm8226-ocmem-v3-6-79da95a2581f@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index b6e2ca04a233..b6ae4b7936e3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -784,6 +784,23 @@ smd-edge { }; }; + sram@fdd00000 { + compatible = "qcom,msm8226-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x20000>; + reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x20000>; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; + clock-names = "core"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x20000>; + }; + }; + sram@fe805000 { compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; From 7caf09215ca32f1020df1559027d77770ca2e901 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 19 Jun 2023 19:01:48 +0200 Subject: [PATCH 03/20] ARM: dts: qcom: ipq4019: use generic node names for USB Device node names should be generic which is also expected by USB bindings: qcom-ipq4018-jalapeno.dtb: dwc3@6000000: $nodename:0: 'dwc3@6000000' does not match '^usb(@.*)?' Override also the DWC3 node in qcom-ipq4018-ap120c-ac.dtsi by label/phandle, not via node path, because it is less error-prone and makes the overriding node-name independent. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230619170151.65505-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi | 7 ++++--- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 14 +++++++------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index d90b4f4c63af..da67d55fa557 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -262,10 +262,11 @@ &usb3_hs_phy { &usb3 { status = "okay"; - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; }; + +&usb3_dwc { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; }; &usb2_hs_phy { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index f0ef86fadc9d..13388e5c1b4b 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -621,7 +621,7 @@ ethphy4: ethernet-phy@4 { }; }; - usb3_ss_phy: ssphy@9a000 { + usb3_ss_phy: usb-phy@9a000 { compatible = "qcom,usb-ss-ipq4019-phy"; #phy-cells = <0>; reg = <0x9a000 0x800>; @@ -631,7 +631,7 @@ usb3_ss_phy: ssphy@9a000 { status = "disabled"; }; - usb3_hs_phy: hsphy@a6000 { + usb3_hs_phy: usb-phy@a6000 { compatible = "qcom,usb-hs-ipq4019-phy"; #phy-cells = <0>; reg = <0xa6000 0x40>; @@ -641,7 +641,7 @@ usb3_hs_phy: hsphy@a6000 { status = "disabled"; }; - usb3: usb3@8af8800 { + usb3: usb@8af8800 { compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x8af8800 0x100>; #address-cells = <1>; @@ -653,7 +653,7 @@ usb3: usb3@8af8800 { ranges; status = "disabled"; - dwc3@8a00000 { + usb3_dwc: usb@8a00000 { compatible = "snps,dwc3"; reg = <0x8a00000 0xf8000>; interrupts = ; @@ -663,7 +663,7 @@ dwc3@8a00000 { }; }; - usb2_hs_phy: hsphy@a8000 { + usb2_hs_phy: usb-phy@a8000 { compatible = "qcom,usb-hs-ipq4019-phy"; #phy-cells = <0>; reg = <0xa8000 0x40>; @@ -673,7 +673,7 @@ usb2_hs_phy: hsphy@a8000 { status = "disabled"; }; - usb2: usb2@60f8800 { + usb2: usb@60f8800 { compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x60f8800 0x100>; #address-cells = <1>; @@ -685,7 +685,7 @@ usb2: usb2@60f8800 { ranges; status = "disabled"; - dwc3@6000000 { + usb@6000000 { compatible = "snps,dwc3"; reg = <0x6000000 0xf8000>; interrupts = ; From 9a3b29c33b5d3d3dd446c1fa314a79f7a905886a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 19 Jun 2023 19:01:49 +0200 Subject: [PATCH 04/20] ARM: dts: qcom: sdx55: use generic node names for USB Device node names should be generic which is also expected by USB bindings: qcom-sdx55-t55.dtb: dwc3@a600000: $nodename:0: 'dwc3@a600000' does not match '^usb(@.*)?' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230619170151.65505-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index df3cd9c4ffb9..55ce87b75253 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -603,7 +603,7 @@ usb: usb@a6f8800 { resets = <&gcc GCC_USB30_BCR>; - usb_dwc3: dwc3@a600000 { + usb_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; interrupts = ; From 1bfeee1aeef0e6070e9ca2f06d310eb1c3058464 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 19 Jun 2023 19:01:50 +0200 Subject: [PATCH 05/20] ARM: dts: qcom: ipq8064: drop spi-max-frequency from controller spi-max-frequency is a property of SPI device, not SPI controller. Drop it from the controller nodes. No functional impact expected because child SPI device already defines spi-max-frequency. This fixes dtbs_check warnings like: qcom-ipq8064-ap148.dtb: spi@1a280000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230619170151.65505-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts | 1 - arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts index 104eb729c2d6..1796ded31d17 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts @@ -282,7 +282,6 @@ gsbi5: gsbi@1a200000 { spi4: spi@1a280000 { status = "okay"; - spi-max-frequency = <50000000>; pinctrl-0 = <&spi_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi index c5abe7151f14..17f65e140e02 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi @@ -30,7 +30,6 @@ gsbi5: gsbi@1a200000 { spi4: spi@1a280000 { status = "okay"; - spi-max-frequency = <50000000>; pinctrl-0 = <&spi_pins>; pinctrl-names = "default"; From 594ccb8d24726c89dd6601b2322b399648da7a8c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 19 Jun 2023 19:01:51 +0200 Subject: [PATCH 06/20] ARM: dts: qcom: msm8960: drop spi-max-frequency from controller spi-max-frequency is a property of SPI device, not SPI controller. Drop it from the controller nodes. No functional impact expected, although qcom-msm8960-samsung-expressatt board does not have any child SPI devices thus the property disappears. This fixes dtbs_check warnings like: qcom-msm8960-cdp.dtb: spi@16080000: Unevaluated properties are not allowed ('spi-max-frequency' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230619170151.65505-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index fa2013388d99..d13080fcbeea 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -364,7 +364,6 @@ gsbi1_spi: spi@16080000 { #size-cells = <0>; reg = <0x16080000 0x1000>; interrupts = ; - spi-max-frequency = <24000000>; cs-gpios = <&msmgpio 8 0>; clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; From c4cf1cc5afbaa84513d1d4e2b60b1a434927f4ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 2 Jul 2023 20:50:51 +0200 Subject: [PATCH 07/20] ARM: dts: qcom: minor whitespace cleanup around '=' The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230702185051.43867-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 20 +++++++++---------- .../qcom/qcom-msm8974pro-fairphone-fp2.dts | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 13388e5c1b4b..1e06f76a7369 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -416,10 +416,10 @@ restart@4ab000 { pcie0: pci@40000000 { compatible = "qcom,pcie-ipq4019"; - reg = <0x40000000 0xf1d - 0x40000f20 0xa8 - 0x80000 0x2000 - 0x40100000 0x1000>; + reg = <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x80000 0x2000>, + <0x40100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -543,9 +543,9 @@ wifi0: wifi@a000000 { , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14", "msi15", "legacy"; status = "disabled"; @@ -585,9 +585,9 @@ wifi1: wifi@a800000 { , , ; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14", "msi15", "legacy"; status = "disabled"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts index f531d2679f6c..42d253b75dad 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts @@ -414,7 +414,7 @@ cmd-data-pins { wcnss_pin_a: wcnss-pin-active-state { wlan-pins { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; function = "wlan"; drive-strength = <6>; From de57328b1c9da0f30ccca4925ed6d5615b1a72b3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 9 Jun 2023 05:25:52 +0300 Subject: [PATCH 08/20] ARM: dts: qcom-pm8941: add resin support Wrap existing pwrkey and new resin nodes into the new pon node to enable volume-down key support on platforms using pm8941 PMIC. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230609022553.1775844-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-pm8941.dtsi | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi index b3e246bacd78..1e3bf643af1b 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi @@ -50,12 +50,24 @@ rtc@6000 { interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; + pon@800 { + compatible = "qcom,pm8941-pon"; reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + + pm8941_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; }; usb_id: usb-detect@900 { From a9037f330e9d6faeba6f5663ca05f525aa1954f4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 9 Jun 2023 05:25:53 +0300 Subject: [PATCH 09/20] ARM: dts: qcom: apq8074-dragonboard: add resin Add device nodes for resin (reset, volume-down) device node. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230609022553.1775844-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index e0679436000b..6d1b2439ae3a 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -156,6 +156,11 @@ led@7 { }; }; +&pm8941_resin { + linux,code = ; + status = "okay"; +}; + &pm8941_wled { qcom,cs-out; qcom,switching-freq = <3200>; From b471a1bc797429f905b97edd727f4678d7b20ec8 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:45 +0200 Subject: [PATCH 10/20] ARM: dts: qcom: Add rpm-proc node for SMD platforms Rather than having the RPM SMD channels as the only child of a dummy SMD node, switch to representing the RPM as remoteproc like all the other remoteprocs (WCNSS, modem DSP). This allows assigning additional subdevices to it like the MPM interrupt-controller or rpm-master-stats. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-12-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 6 ++-- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 38 ++++++++++---------- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 44 ++++++++++++------------ 3 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 8f178bc87e1d..2b1f9d0fb510 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -784,10 +784,10 @@ spmi_bus: spmi@fc4cf000 { }; }; - smd { - compatible = "qcom,smd"; + rpm: remoteproc { + compatible = "qcom,apq8084-rpm-proc", "qcom,rpm-proc"; - rpm { + smd-edge { interrupts = ; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index b6ae4b7936e3..44f3f0127fd7 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -53,26 +53,10 @@ pmu { IRQ_TYPE_LEVEL_HIGH)>; }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; + rpm: remoteproc { + compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; - smem_region: smem@3000000 { - reg = <0x3000000 0x100000>; - no-map; - }; - - adsp_region: adsp@dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { + smd-edge { interrupts = ; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; @@ -120,6 +104,22 @@ rpmpd_opp_super_turbo: opp6 { }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_region: smem@3000000 { + reg = <0x3000000 0x100000>; + no-map; + }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; + }; + }; + smem { compatible = "qcom,smem"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index aeca504918a0..706fef53767e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -113,6 +113,28 @@ pmu { interrupts = ; }; + rpm: remoteproc { + compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8974"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + }; + }; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -293,28 +315,6 @@ wcnss_smsm: wcnss@7 { }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - }; - }; - }; - soc: soc { #address-cells = <1>; #size-cells = <1>; From 3f30509ff561453ea0c4de1716ab72125f8bf83c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:46 +0200 Subject: [PATCH 11/20] ARM: dts: qcom: apq8064: Drop redundant /smd node The "smd-edge"s for remote processors are typically specified below the remoteproc nodes. For some reason apq8064 also has them all listed in a top-level /smd node, disabled by default. None of the boards enable them. Right now apq8064 only has support for WCNSS/riva, but there the smd-edge is already defined with the same interrupt etc below the riva-pil node. Drop these redundant definitions since the /smd top-level node is now deprecated. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-13-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 40 ------------------------ 1 file changed, 40 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index d2289205ff81..e0adf237fc5c 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -226,46 +226,6 @@ smem { hwlocks = <&sfpb_mutex 3>; }; - smd { - compatible = "qcom,smd"; - - modem-edge { - interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 3>; - qcom,smd-edge = <0>; - - status = "disabled"; - }; - - q6-edge { - interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 15>; - qcom,smd-edge = <1>; - - status = "disabled"; - }; - - dsps-edge { - interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&sps_sic_non_secure 0x4080 0>; - qcom,smd-edge = <3>; - - status = "disabled"; - }; - - riva-edge { - interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 25>; - qcom,smd-edge = <6>; - - status = "disabled"; - }; - }; - smsm { compatible = "qcom,smsm"; From 43db69268149049540b1d2bbe8a69e59d5cb43b6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 13:53:33 +0200 Subject: [PATCH 12/20] ARM: dts: qcom: msm8974pro-castor: correct inverted X of touchscreen There is no syna,f11-flip-x property, so assume intention was to use touchscreen-inverted-x. Fixes: ab80661883de ("ARM: dts: qcom: msm8974: Add Sony Xperia Z2 Tablet") Cc: Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230720115335.137354-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 154639d56f35..c41e25367bc9 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -132,8 +132,8 @@ rmi-f01@1 { rmi-f11@11 { reg = <0x11>; - syna,f11-flip-x = <1>; syna,sensor-type = <1>; + touchscreen-inverted-x; }; }; }; From 31fba16c19c45b2b3a7c23b0bfef80aed1b29050 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 13:53:34 +0200 Subject: [PATCH 13/20] ARM: dts: qcom: msm8974pro-castor: correct touchscreen function names The node names for functions of Synaptics RMI4 touchscreen must be as "rmi4-fXX", as required by bindings and Linux driver. qcom-msm8974pro-sony-xperia-shinano-castor.dtb: synaptics@2c: Unevaluated properties are not allowed ('rmi-f01@1', 'rmi-f11@11' were unexpected) Fixes: ab80661883de ("ARM: dts: qcom: msm8974: Add Sony Xperia Z2 Tablet") Cc: Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230720115335.137354-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index c41e25367bc9..726ed67415e1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -125,12 +125,12 @@ synaptics@2c { syna,startup-delay-ms = <100>; - rmi-f01@1 { + rmi4-f01@1 { reg = <0x1>; syna,nosleep = <1>; }; - rmi-f11@11 { + rmi4-f11@11 { reg = <0x11>; syna,sensor-type = <1>; touchscreen-inverted-x; From 7c74379afdfee7b13f1cd8ff1ad6e0f986aec96c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 13:53:35 +0200 Subject: [PATCH 14/20] ARM: dts: qcom: msm8974pro-castor: correct touchscreen syna,nosleep-mode There is no syna,nosleep property in Synaptics RMI4 touchscreen: qcom-msm8974pro-sony-xperia-shinano-castor.dtb: synaptics@2c: rmi4-f01@1: 'syna,nosleep' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: ab80661883de ("ARM: dts: qcom: msm8974: Add Sony Xperia Z2 Tablet") Cc: Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230720115335.137354-6-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 726ed67415e1..11468d1409f7 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -127,7 +127,7 @@ synaptics@2c { rmi4-f01@1 { reg = <0x1>; - syna,nosleep = <1>; + syna,nosleep-mode = <1>; }; rmi4-f11@11 { From 174b934c3dc4fc7bd1d2075745bba829a743553f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:26 +0300 Subject: [PATCH 15/20] ARM: dts: qcom-mdm9615: specify clocks for the lcc device Specify clocks used by the LCC device on the MDM9615 platform. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512211727.3445575-10-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index b40c52ddf9b4..556abe90cf5b 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -39,7 +39,7 @@ cpu-pmu { }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; @@ -113,6 +113,20 @@ lcc: clock-controller@28000000 { reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&cxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "cxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; l2cc: clock-controller@2011000 { From d988aa8cd09653d9607788e9d1c98f0d7a55e731 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:27 +0300 Subject: [PATCH 16/20] ARM: dts: qcom-mdm9615: specify gcc clocks Fully specify the clocks used by the GCC on the mdm9615 platform. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512211727.3445575-11-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index 556abe90cf5b..fc4f52f9e9f7 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -106,6 +107,8 @@ gcc: clock-controller@900000 { #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&cxo_board>, + <&lcc PLL4>; }; lcc: clock-controller@28000000 { From 04601b9b1b67888b7e2987e31ab40637f7c999c0 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Jul 2023 22:31:25 +0200 Subject: [PATCH 17/20] ARM: dts: qcom: Use labels with generic node names for ADC channels A future bindings update will replace the free-form qcom,spmi-vadc and qcom,spmi-adc5 channel node names with the specific name `channel`, to be more consistent with how the driver parses the nodes and to match the generic node name set in `iio/adc/adc.yaml`. Signed-off-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230730-generic-adc-channels-v5-1-e6c69bda8034@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-pm8226.dtsi | 12 ++++++------ arch/arm/boot/dts/qcom/qcom-pm8941.dtsi | 14 +++++++------- arch/arm/boot/dts/qcom/qcom-pma8084.dtsi | 12 ++++++------ arch/arm/boot/dts/qcom/qcom-pmx55.dtsi | 8 ++++---- 4 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi index 3b8ad28cecb0..2413778f3715 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi @@ -102,27 +102,27 @@ pm8226_vadc: adc@3100 { #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@7 { + channel@7 { reg = ; qcom,pre-scaling = <1 3>; label = "vph_pwr"; }; - adc-chan@8 { + channel@8 { reg = ; label = "die_temp"; }; - adc-chan@9 { + channel@9 { reg = ; label = "ref_625mv"; }; - adc-chan@a { + channel@a { reg = ; label = "ref_1250mv"; }; - adc-chan@e { + channel@e { reg = ; }; - adc-chan@f { + channel@f { reg = ; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi index 1e3bf643af1b..ed0ba591c755 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi @@ -145,31 +145,31 @@ pm8941_vadc: adc@3100 { #io-channel-cells = <1>; - adc-chan@6 { + channel@6 { reg = ; }; - adc-chan@8 { + channel@8 { reg = ; }; - adc-chan@9 { + channel@9 { reg = ; }; - adc-chan@a { + channel@a { reg = ; }; - adc-chan@e { + channel@e { reg = ; }; - adc-chan@f { + channel@f { reg = ; }; - adc-chan@30 { + channel@30 { reg = ; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi index 2dd4c6aa71c9..2985f4805b93 100644 --- a/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi @@ -64,27 +64,27 @@ pma8084_vadc: adc@3100 { #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@8 { + channel@8 { reg = ; }; - adc-chan@9 { + channel@9 { reg = ; }; - adc-chan@a { + channel@a { reg = ; }; - adc-chan@c { + channel@c { reg = ; }; - adc-chan@e { + channel@e { reg = ; }; - adc-chan@f { + channel@f { reg = ; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi index e1b869480bbd..da0851173c69 100644 --- a/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi @@ -40,25 +40,25 @@ pmx55_adc: adc@3100 { #io-channel-cells = <1>; interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - chg-temp@9 { + channel@9 { reg = ; qcom,pre-scaling = <1 1>; label = "chg_temp"; From b5ed7a5c1fdb3981713f7b637b72aa390c3db036 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 11 Aug 2023 13:01:16 +0200 Subject: [PATCH 18/20] ARM: dts: qcom: ipq4019: correct SDHCI XO clock Using GCC_DCD_XO_CLK as the XO clock for SDHCI controller is not correct, it seems that I somehow made a mistake of passing it instead of the fixed XO clock. Fixes: 04b3b72b5b8f ("ARM: dts: qcom: ipq4019: Add SDHCI controller node") Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811110150.229966-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 1e06f76a7369..9844e0b7cff9 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -230,9 +230,12 @@ sdhci: mmc@7824900 { interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_DCD_XO_CLK>; - clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names = "iface", + "core", + "xo"; status = "disabled"; }; From f636d6c356b339b0d29eed025f8bf9efcb6eb274 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:51 +0530 Subject: [PATCH 19/20] ARM: dts: qcom: sdx65-mtp: Update the pmic used in sdx65 Update the pmic used in sdx65 platform to pm7250b. Fixes: 26380f298b2b (ARM: dts: qcom: sdx65-mtp: Add pmk8350b and pm8150b pmic) Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-7-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts index 02d8d6e241ae..fcf1c51c5e7a 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts @@ -7,7 +7,7 @@ #include "qcom-sdx65.dtsi" #include #include -#include +#include #include "qcom-pmx65.dtsi" / { From 3cfa5569cedf1e5d125b62e690c1915d6b757a47 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 14 Aug 2023 17:00:40 +0200 Subject: [PATCH 20/20] ARM: dts: qcom: apq8064: add support to gsbi4 uart This patch adds support to gsbi4 uart which is used in LG Mako. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20230814150040.64133-1-david@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 12 ++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi index b4d286a6fab1..7c545c50847b 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -233,6 +233,22 @@ pinconf { }; }; + gsbi4_uart_pin_a: gsbi4-uart-pin-active-state { + rx-pins { + pins = "gpio11"; + function = "gsbi4"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio10"; + function = "gsbi4"; + drive-strength = <4>; + bias-disable; + }; + }; + gsbi6_uart_2pins: gsbi6_uart_2pins { mux { pins = "gpio14", "gpio15"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index e0adf237fc5c..516f0d2495e2 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -515,6 +515,18 @@ gsbi4: gsbi@16300000 { #size-cells = <1>; ranges; + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x100>, + <0x16300000 0x3>; + interrupts = ; + pinctrl-0 = <&gsbi4_uart_pin_a>; + pinctrl-names = "default"; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + gsbi4_i2c: i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; pinctrl-0 = <&i2c4_pins>;