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Amlogic ARM64 DT for v6.20:

Browse Source 
- Cleanups:
   - Use lowercase hex
   - Use hyphen in node names
   - move CPU OPP table and clock assignment to SoC.dtsi
   - drop useless assigned-clock-parents
 - MMC clock fixup across multiple families
 - Add type-c controller on Radxa Zero 2 and enable NPU
 - New board:
   - Khadas VIM1s based on Amlogic S4
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Merge tag 'amlogic-arm64-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt

Amlogic ARM64 DT for v6.20:
- Cleanups:
  - Use lowercase hex
  - Use hyphen in node names
  - move CPU OPP table and clock assignment to SoC.dtsi
  - drop useless assigned-clock-parents
- MMC clock fixup across multiple families
- Add type-c controller on Radxa Zero 2 and enable NPU
- New board:
  - Khadas VIM1s based on Amlogic S4

* tag 'amlogic-arm64-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable SDIO interface
  arm64: dts: amlogic: add the type-c controller on Radxa Zero 2
  arm64: dts: amlogic: meson-sm1-odroid: Eliminate Odroid HC4 power glitches during boot.
  arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable eMMC storage
  arm64: dts: meson-s4-s905y4-khadas-vim1s: add initial device tree
  arm64: dts: meson-s4-aq222: update compatible string with s805x2
  dt-bindings: arm: amlogic: introduce specific compatibles for S4 family
  arm64: dts: amlogic: Enable the npu node on Radxa Zero 2
  arm64: dts: amlogic: g12: assign the MMC A signal clock
  arm64: dts: amlogic: g12: assign the MMC B and C signal clocks
  arm64: dts: amlogic: gx: assign the MMC signal clocks
  arm64: dts: amlogic: axg: assign the MMC signal clocks
  arm64: dts: amlogic: a1: align the mmc clock setup
  arm64: dts: amlogic: c3: assign the MMC signal clocks
  arm64: dts: amlogic: s4: fix mmc clock assignment
  arm64: dts: amlogic: s4: assign mmc b clock to 24MHz
  arm64: dts: amlogic: drop useless assigned-clock-parents
  arm64: dts: amlogic: move CPU OPP table and clock assignment to SoC.dtsi
  arm64: dts: amlogic: Use lowercase hex
  arm64: dts: amlogic: Use hyphen in node names

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-01-28 18:40:33 +01:00
commit 3b2db85f48
79 changed files with 442 additions and 247 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -245,6 +245,14 @@ properties:
items:
- enum:
- amlogic,aq222
- const: amlogic,s805x2
- const: amlogic,s4
- description: Boards with the Amlogic Meson S4 S905Y4 SoC
items:
- enum:
- khadas,vim1s
- const: amlogic,s905y4
- const: amlogic,s4
- description: Boards with the Amlogic S6 S905X5 SoC

1
arch/arm64/boot/dts/amlogic/Makefile
View File

@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-ugoos-am3.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-s4-s905y4-khadas-vim1s.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m2-pro.dtb

13
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
View File

@ -108,7 +108,7 @@ scmi_shmem: sram@0 {
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x820000C1>;
arm,smc-id = <0x820000c1>;
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
@ -780,7 +780,7 @@ int_mdio: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
internal_ephy: ethernet_phy@8 {
internal_ephy: ethernet-phy@8 {
compatible = "ethernet-phy-id0180.3301",
"ethernet-phy-ieee802.3-c22";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@ -969,6 +969,10 @@ sdio: mmc@88000 {
no-sd;
resets = <&reset RESET_SD_EMMC_A>;
status = "disabled";
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>;
assigned-clock-rates = <24000000>;
};
sd: mmc@8a000 {
@ -984,12 +988,15 @@ sd: mmc@8a000 {
no-sdio;
resets = <&reset RESET_SD_EMMC_B>;
status = "disabled";
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>;
assigned-clock-rates = <24000000>;
};
nand: nand-controller@8d000 {
compatible = "amlogic,meson-axg-nfc";
reg = <0x0 0x8d000 0x0 0x200>,
<0x0 0x8C000 0x0 0x4>;
<0x0 0x8c000 0x0 0x4>;
reg-names = "nfc", "emmc";
interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,

2
arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts
View File

@ -20,7 +20,7 @@ aliases {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0xE0000000
reg = <0x00000000 0x00000000 0x00000000 0xe0000000
0x00000001 0x00000000 0x00000000 0x20000000>;
};

5
arch/arm64/boot/dts/amlogic/meson-a1.dtsi
View File

@ -674,11 +674,12 @@ sd_emmc: mmc@10000 {
clock-names = "core",
"clkin0",
"clkin1";
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
assigned-clock-parents = <&xtal>;
resets = <&reset RESET_SD_EMMC_A>;
power-domains = <&pwrc PWRC_SD_EMMC_ID>;
status = "disabled";
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC>;
assigned-clock-rates = <24000000>;
};
};

1
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
View File

@ -275,7 +275,6 @@ sound {
assigned-clocks = <&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <589824000>,
<270950400>,
<393216000>;

6
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@ -1960,6 +1960,9 @@ sd_emmc_b: mmc@5000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
assigned-clock-rates = <24000000>;
};
sd_emmc_c: mmc@7000 {
@ -1972,6 +1975,9 @@ sd_emmc_c: mmc@7000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
assigned-clock-rates = <24000000>;
};
nfc: nand-controller@7800 {

9
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View File

@ -2431,6 +2431,9 @@ sd_emmc_a: mmc@ffe03000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
assigned-clock-rates = <24000000>;
};
sd_emmc_b: mmc@ffe05000 {
@ -2443,6 +2446,9 @@ sd_emmc_b: mmc@ffe05000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
assigned-clock-rates = <24000000>;
};
sd_emmc_c: mmc@ffe07000 {
@ -2455,6 +2461,9 @@ sd_emmc_c: mmc@ffe07000 {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
assigned-clock-rates = <24000000>;
};
usb: usb@ffe09000 {

9
arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
View File

@ -183,7 +183,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -265,26 +264,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&ethmac {

9
arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
View File

@ -145,7 +145,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -218,26 +217,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {

9
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
View File

@ -208,7 +208,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -312,26 +311,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {

9
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
View File

@ -245,7 +245,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -405,26 +404,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&clkc_audio {

9
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
View File

@ -165,7 +165,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -261,26 +260,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cvbs_vdac_port {

8
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
View File

@ -25,6 +25,8 @@ cpu0: cpu@0 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
@ -40,6 +42,8 @@ cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu2: cpu@2 {
@ -55,6 +59,8 @@ cpu2: cpu@2 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu3: cpu@3 {
@ -70,6 +76,8 @@ cpu3: cpu@3 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
l2: l2-cache0 {

13
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
View File

@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-g12b-a311d.dtsi"
#include "meson-libretech-cottonwood.dtsi"
@ -74,38 +73,26 @@ sound {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&pwm_ab {

24
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
View File

@ -109,3 +109,27 @@ opp-2208000000 {
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu1 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu100 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu101 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu102 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu103 {
operating-points-v2 = <&cpub_opp_table_1>;
};

1
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts
View File

@ -77,7 +77,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts
View File

@ -86,7 +86,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

12
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
View File

@ -153,38 +153,26 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&ext_mdio {

13
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
View File

@ -201,7 +201,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -261,38 +260,26 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&ethmac {

1
arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi
View File

@ -47,7 +47,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts
View File

@ -55,7 +55,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts
View File

@ -56,7 +56,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts
View File

@ -44,7 +44,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

12
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
View File

@ -49,38 +49,26 @@ vddcpu_b: regulator-vddcpu-b {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&pwm_ab {

13
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
View File

@ -241,7 +241,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -279,38 +278,26 @@ &arb {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
/* RK817 only supports 12.5mV steps, round up the values */

1
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
View File

@ -102,7 +102,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts
View File

@ -46,7 +46,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

12
arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
View File

@ -225,38 +225,26 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu_thermal {

51
arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
View File

@ -183,7 +183,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -257,38 +256,26 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu_thermal {
@ -364,12 +351,46 @@ hdmi_tx_tmds_out: endpoint {
};
};
/* Also exposed on the 40-pin header: SDA pin 3, SCL pin 5 */
&i2c3 {
pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>;
pinctrl-names = "default";
status = "okay";
fusb0: typec-portc@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
pinctrl-0 = <&fusb302_irq_pins>;
pinctrl-names = "default";
interrupt-parent = <&gpio_intc>;
interrupts = <74 IRQ_TYPE_LEVEL_LOW>;
vbus-supply = <&ao_5v>;
connector {
compatible = "usb-c-connector";
};
};
};
&ir {
status = "disabled";
pinctrl-0 = <&remote_input_ao_pins>;
pinctrl-names = "default";
};
&periphs_pinctrl {
fusb302_irq_pins: fusb302-irq {
mux {
groups = "GPIOA_13";
function = "gpio_periphs";
bias-pull-up;
output-disable;
};
};
};
&pwm_ab {
pinctrl-0 = <&pwm_a_e_pins>;
pinctrl-names = "default";
@ -394,6 +415,10 @@ &pwm_AO_cd {
status = "okay";
};
&npu {
status = "okay";
};
&saradc {
status = "okay";
vref-supply = <&vddao_1v8>;

24
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
View File

@ -99,3 +99,27 @@ opp-1908000000 {
};
};
};
&cpu0 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu1 {
operating-points-v2 = <&cpu_opp_table_0>;
};
&cpu100 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu101 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu102 {
operating-points-v2 = <&cpub_opp_table_1>;
};
&cpu103 {
operating-points-v2 = <&cpub_opp_table_1>;
};

1
arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts
View File

@ -39,7 +39,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

12
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
View File

@ -211,38 +211,26 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
&cvbs_vdac_port {

7
arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
View File

@ -57,6 +57,7 @@ cpu0: cpu@0 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
@ -73,6 +74,7 @@ cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu100: cpu@100 {
@ -89,6 +91,7 @@ cpu100: cpu@100 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu101: cpu@101 {
@ -105,6 +108,7 @@ cpu101: cpu@101 {
i-cache-sets = <32>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu102: cpu@102 {
@ -121,6 +125,7 @@ cpu102: cpu@102 {
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
cpu103: cpu@103 {
@ -137,6 +142,8 @@ cpu103: cpu@103 {
i-cache-sets = <64>;
next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
};
l2_cache_l: l2-cache-cluster0 {

1
arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi
View File

@ -201,7 +201,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
View File

@ -136,7 +136,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts
View File

@ -52,7 +52,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
View File

@ -142,7 +142,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
View File

@ -149,7 +149,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View File

@ -184,7 +184,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
View File

@ -75,7 +75,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
View File

@ -24,7 +24,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View File

@ -115,7 +115,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts
View File

@ -23,7 +23,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts
View File

@ -55,7 +55,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

9
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -824,6 +824,9 @@ &sd_emmc_a {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_b {
@ -832,6 +835,9 @@ &sd_emmc_b {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_c {
@ -840,6 +846,9 @@ &sd_emmc_c {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
assigned-clock-rates = <24000000>;
};
&simplefb_hdmi {

1
arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts
View File

@ -130,7 +130,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts
View File

@ -135,7 +135,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts
View File

@ -125,7 +125,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts
View File

@ -74,7 +74,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts
View File

@ -167,7 +167,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View File

@ -149,7 +149,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
View File

@ -57,7 +57,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts
View File

@ -98,7 +98,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

9
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -894,6 +894,9 @@ &sd_emmc_a {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_b {
@ -902,6 +905,9 @@ &sd_emmc_b {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>;
assigned-clock-rates = <24000000>;
};
&sd_emmc_c {
@ -910,6 +916,9 @@ &sd_emmc_c {
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>;
assigned-clock-rates = <24000000>;
};
&simplefb_hdmi {

1
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts
View File

@ -157,7 +157,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

2
arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts
View File

@ -17,7 +17,7 @@ / {
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0xC0000000>;
reg = <0x0 0x0 0x0 0xc0000000>;
};
adc-keys {

1
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
View File

@ -93,7 +93,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
View File

@ -108,7 +108,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi
View File

@ -189,7 +189,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi
View File

@ -207,7 +207,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

2
arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
View File

@ -9,7 +9,7 @@
/ {
model = "Amlogic Meson S4 AQ222 Development Board";
compatible = "amlogic,aq222", "amlogic,s4";
compatible = "amlogic,aq222", "amlogic,s805x2", "amlogic,s4";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;

259
arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts Normal file
View File

@ -0,0 +1,259 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2026 Khadas Technology Co., Ltd.
*/
/dts-v1/;
#include "meson-s4.dtsi"
/ {
model = "Khadas VIM1S";
compatible = "khadas,vim1s", "amlogic,s905y4", "amlogic,s4";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
mmc0 = &emmc; /* eMMC */
mmc1 = &sd; /* SD card */
mmc2 = &sdio; /* SDIO */
serial0 = &uart_b;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 52 MiB reserved for ARM Trusted Firmware */
secmon_reserved: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x3400000>;
no-map;
};
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>;
};
sdio_32k: sdio-32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&sdio_32k>;
clock-names = "ext_clock";
};
main_5v: regulator-main-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
sd_3v3: regulator-sd-3v3 {
compatible = "regulator-fixed";
regulator-name = "SD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio GPIOD_4 GPIO_ACTIVE_LOW>;
regulator-always-on;
};
vddio_sd: regulator-vddio-sd {
compatible = "regulator-gpio";
regulator-name = "VDDIO_SD";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <1800000 1
3300000 0>;
};
vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_5v>;
regulator-always-on;
};
vddio_ao1v8: regulator-vddio-ao1v8 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
/* SY8120B1ABC DC/DC Regulator. */
vddcpu: regulator-vddcpu {
compatible = "pwm-regulator";
regulator-name = "VDDCPU";
regulator-min-microvolt = <689000>;
regulator-max-microvolt = <1049000>;
vin-supply = <&main_5v>;
pwms = <&pwm_ij 1 1500 0>;
pwm-dutycycle-range = <100 0>;
regulator-boot-on;
regulator-always-on;
/* Voltage Duty-Cycle */
voltage-table = <1049000 0>,
<1039000 3>,
<1029000 6>,
<1019000 9>,
<1009000 12>,
<999000 14>,
<989000 17>,
<979000 20>,
<969000 23>,
<959000 26>,
<949000 29>,
<939000 31>,
<929000 34>,
<919000 37>,
<909000 40>,
<899000 43>,
<889000 45>,
<879000 48>,
<869000 51>,
<859000 54>,
<849000 56>,
<839000 59>,
<829000 62>,
<819000 65>,
<809000 68>,
<799000 70>,
<789000 73>,
<779000 76>,
<769000 79>,
<759000 81>,
<749000 84>,
<739000 87>,
<729000 89>,
<719000 92>,
<709000 95>,
<699000 98>,
<689000 100>;
};
};
&emmc {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_ao1v8>;
};
&ethmac {
status = "okay";
phy-handle = <&internal_ephy>;
phy-mode = "rmii";
};
&ir {
status = "okay";
pinctrl-0 = <&remote_pins>;
pinctrl-names = "default";
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins1>;
pinctrl-names = "default";
};
&pwm_ij {
status = "okay";
};
&sd {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&sd_3v3>;
vqmmc-supply = <&vddio_sd>;
};
&sdio {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <50000000>;
non-removable;
disable-wp;
no-sd;
no-mmc;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_ao1v8>;
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
};
};
&spicc0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spicc0_pins_x>;
cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
};
&uart_b {
status = "okay";
};

13
arch/arm64/boot/dts/amlogic/meson-s4.dtsi
View File

@ -819,13 +819,16 @@ sdio: mmc@fe088000 {
reg = <0x0 0xfe088000 0x0 0x800>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc_periphs CLKID_SDEMMC_A>,
<&xtal>,
<&clkc_periphs CLKID_SD_EMMC_A>,
<&clkc_pll CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_A>;
cap-sdio-irq;
keep-power-in-suspend;
status = "disabled";
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>;
assigned-clock-rates = <24000000>;
};
sd: mmc@fe08a000 {
@ -838,6 +841,9 @@ sd: mmc@fe08a000 {
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
status = "disabled";
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>;
assigned-clock-rates = <24000000>;
};
emmc: mmc@fe08c000 {
@ -845,13 +851,16 @@ emmc: mmc@fe08c000 {
reg = <0x0 0xfe08c000 0x0 0x800>;
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_periphs CLKID_NAND>,
<&xtal>,
<&clkc_periphs CLKID_SD_EMMC_C>,
<&clkc_pll CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_NAND_EMMC>;
no-sdio;
no-sd;
status = "disabled";
assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C>;
assigned-clock-rates = <24000000>;
};
};
};

1
arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts
View File

@ -29,7 +29,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts
View File

@ -29,7 +29,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

8
arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
View File

@ -145,26 +145,18 @@ &cecb_AO {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&cvbs_vdac_port {

1
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts
View File

@ -29,7 +29,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts
View File

@ -64,7 +64,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

8
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
View File

@ -183,26 +183,18 @@ &arb {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&ext_mdio {

1
arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts
View File

@ -29,7 +29,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

8
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
View File

@ -49,26 +49,18 @@ sound {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&pwm_AO_cd {

2
arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts
View File

@ -52,6 +52,7 @@ p12v_0: regulator-p12v-0 {
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
@ -65,6 +66,7 @@ p12v_1: regulator-p12v-1 {
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
};

12
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
View File

@ -37,6 +37,7 @@ tflash_vdd: regulator-tflash-vdd {
gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
@ -50,6 +51,7 @@ tf_io: gpio-regulator-tf-io {
enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
@ -81,6 +83,7 @@ vcc_5v: regulator-vcc-5v {
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&main_12v>;
gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
@ -181,7 +184,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -248,26 +250,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&ext_mdio {

9
arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
View File

@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-sm1.dtsi"
#include "meson-libretech-cottonwood.dtsi"
@ -62,24 +61,16 @@ sound {
&cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};

9
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
View File

@ -246,7 +246,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
@ -357,26 +356,18 @@ &clkc_audio {
&cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
&ethmac {

1
arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts
View File

@ -29,7 +29,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

1
arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts
View File

@ -29,7 +29,6 @@ sound {
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;

8
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View File

@ -63,6 +63,8 @@ cpu0: cpu@0 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
};
cpu1: cpu@1 {
@ -78,6 +80,8 @@ cpu1: cpu@1 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
};
cpu2: cpu@2 {
@ -93,6 +97,8 @@ cpu2: cpu@2 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
};
cpu3: cpu@3 {
@ -108,6 +114,8 @@ cpu3: cpu@3 {
i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
};
l2: l2-cache0 {