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clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks

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The PCIe and USB3 pipe clocks on Nord are sourced from their
respective PHYs. The halt bit for these branches does not toggle
reliably when the PHY is powered down or not yet brought up, so
polling for it with BRANCH_HALT_VOTED can spuriously time out.

Switch these pipe clock branches to BRANCH_HALT_SKIP, matching the
convention used for PHY-sourced pipe clocks elsewhere in the Qualcomm
clock drivers.

Fixes: a4f780cd5c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260716-b4-nord-pipe-clk-fixes-v1-1-e4f583633356@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das 2026-07-16 16:29:11 +05:30 committed by Bjorn Andersson
parent 830ead322c
commit 3a8a7d597b
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/qcom/gcc-nord.c
View File

@ -702,7 +702,7 @@ static struct clk_branch gcc_pcie_a_phy_rchng_clk = {
static struct clk_branch gcc_pcie_a_pipe_clk = {
.halt_reg = 0x49068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x49068,
.hwcg_bit = 1,
.clkr = {
@ -851,7 +851,7 @@ static struct clk_branch gcc_pcie_b_phy_rchng_clk = {
static struct clk_branch gcc_pcie_b_pipe_clk = {
.halt_reg = 0x4a068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x9d008,
.enable_mask = BIT(24),
@ -996,7 +996,7 @@ static struct clk_branch gcc_pcie_c_phy_rchng_clk = {
static struct clk_branch gcc_pcie_c_pipe_clk = {
.halt_reg = 0x4b068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x9d010,
.enable_mask = BIT(1),
@ -1141,7 +1141,7 @@ static struct clk_branch gcc_pcie_d_phy_rchng_clk = {
static struct clk_branch gcc_pcie_d_pipe_clk = {
.halt_reg = 0x4c068,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x9d010,
.enable_mask = BIT(10),

4
drivers/clk/qcom/negcc-nord.c
View File

@ -1642,7 +1642,7 @@ static struct clk_branch ne_gcc_usb3_prim_phy_com_aux_clk = {
static struct clk_branch ne_gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x2a074,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2a074,
.hwcg_bit = 1,
.clkr = {
@ -1698,7 +1698,7 @@ static struct clk_branch ne_gcc_usb3_sec_phy_com_aux_clk = {
static struct clk_branch ne_gcc_usb3_sec_phy_pipe_clk = {
.halt_reg = 0x2c074,
.halt_check = BRANCH_HALT_VOTED,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x2c074,
.hwcg_bit = 1,
.clkr = {