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clk: qcom: Fix test_ctl_hi field for DEFAULT_EVO PLLs

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CLK_ALPHA_PLL_TYPE_DEFAULT_EVO type PLLs do not have the PLL_TEST_CTL_U1
register, so clk_alpha_pll_configure() does not program test_ctl_hi1_val
for this PLL type.

The GCC PLL configurations for QCM2290, Shikra and SM6115 wrongly use
test_ctl_hi1_val instead of test_ctl_hi_val, deviating from the hardware
recommended settings. Fix them to use test_ctl_hi_val.

Fixes: 496d1a13d4 ("clk: qcom: Add Global Clock Controller driver for QCM2290")
Fixes: 01cf3e2782 ("clk: qcom: Add Global clock controller support on Qualcomm Shikra SoC")
Fixes: e88c533d8a ("clk: qcom: gcc-sm6115: Add missing PLL config properties")
Cc: stable@vger.kernel.org
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260729-pll-test-ctrl-fixup-v1-1-246d79589380@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Imran Shaik 2026-07-29 20:53:47 +05:30 committed by Bjorn Andersson
parent cc881afb66
commit 830ead322c
3 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/clk/qcom/gcc-qcm2290.c
View File

@ -116,7 +116,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll10 = {
@ -148,7 +148,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll11 = {
@ -309,7 +309,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055B,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll8 = {

6
drivers/clk/qcom/gcc-shikra.c
View File

@ -122,7 +122,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll10 = {
@ -155,7 +155,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll11 = {
@ -360,7 +360,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = BIT(8),
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
};
static struct clk_alpha_pll gpll8 = {

6
drivers/clk/qcom/gcc-sm6115.c
View File

@ -120,7 +120,7 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
@ -173,7 +173,7 @@ static const struct alpha_pll_config gpll11_config = {
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
@ -367,7 +367,7 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_val = 0x1,
.test_ctl_hi_mask = 0x1,
};