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clk: rockchip: px30: Add pclk for cif and isp

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Change-Id: Ied25f2c6746e7cc233c4c22436f45ba82900631a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao 2018-01-23 19:35:40 +08:00 committed by Tao Huang
parent f37ae45b20
commit 38cd02b946
2 changed files with 7 additions and 1 deletions
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4
drivers/clk/rockchip/clk-px30.c
View File

@ -424,6 +424,10 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE(SCLK_CIF_OUT, "clk_cif_out", mux_cif_out_p, 0,
PX30_CLKSEL_CON(13), 6, 2, MFLAGS, 0, 6, DFLAGS,
PX30_CLKGATE_CON(4), 11, GFLAGS),
GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
PX30_CLKGATE_CON(4), 13, GFLAGS),
GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
PX30_CLKGATE_CON(4), 14, GFLAGS),
/*
* Clock-Architecture Diagram 6

4
include/dt-bindings/clock/px30-cru.h
View File

@ -178,8 +178,10 @@
#define PCLK_GPIO1 348
#define PCLK_GPIO2 349
#define PCLK_GPIO3 350
#define PCLK_ISP 351
#define PCLK_CIF 352
#define CLK_NR_CLKS (PCLK_GPIO3 + 1)
#define CLK_NR_CLKS (PCLK_CIF + 1)
/* pmu-clocks indices */