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clk: rockchip: rk3308: Use MUXTBL to cover Mux selects priorities

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Change-Id: I14d08f3b98b1dcaf1c9e4b9114ebd103e2dc51c9
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-08-28 09:32:47 +08:00
parent 2c6bab0663
commit 35f541c5a7
1 changed files with 12 additions and 10 deletions
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22
drivers/clk/rockchip/clk-rk3308.c
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@ -190,6 +190,8 @@ PNAME(mux_spdif_tx_src_p) = { "clk_spdif_tx_div", "clk_spdif_tx_div50" };
PNAME(mux_spdif_tx_p) = { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
PNAME(mux_spdif_rx_src_p) = { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
PNAME(mux_spdif_rx_p) = { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
PNAME(mux_uart_src_p) = { "xin24m", "usb480m", "dpll", "vpll0", "vpll1" };
static u32 uart_src_mux_idx[] = { 4, 3, 0, 1, 2 };
static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
@ -342,8 +344,8 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 1, GFLAGS),
COMPOSITE(0, "clk_uart0_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, 0, 5, DFLAGS,
COMPOSITE_MUXTBL(0, "clk_uart0_src", mux_uart_src_p, 0,
RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(12), 0,
@ -352,8 +354,8 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
RK3308_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE(0, "clk_uart1_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, 0, 5, DFLAGS,
COMPOSITE_MUXTBL(0, "clk_uart1_src", mux_uart_src_p, 0,
RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(1), 13, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(15), 0,
@ -362,8 +364,8 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
RK3308_CLKGATE_CON(2), 0, GFLAGS),
COMPOSITE(0, "clk_uart2_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, 0, 5, DFLAGS,
COMPOSITE_MUXTBL(0, "clk_uart2_src", mux_uart_src_p, 0,
RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 1, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(18), 0,
@ -372,8 +374,8 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
RK3308_CLKGATE_CON(2), 4, GFLAGS),
COMPOSITE(0, "clk_uart3_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, 0, 5, DFLAGS,
COMPOSITE_MUXTBL(0, "clk_uart3_src", mux_uart_src_p, 0,
RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 5, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(21), 0,
@ -382,8 +384,8 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
RK3308_CLKGATE_CON(2), 8, GFLAGS),
COMPOSITE(0, "clk_uart4_src", mux_dpll_vpll0_vpll1_usb480m_xin24m_p, 0,
RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, 0, 5, DFLAGS,
COMPOSITE_MUXTBL(0, "clk_uart4_src", mux_uart_src_p, 0,
RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
RK3308_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(24), 0,