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clk: rockchip: add COMPOSITE_MUXTBL and MUXTBL variant

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A clock branch consisting of a mux with non-standard
select values.
The parent in Mux table is sorted by priority.

Change-Id: Ibcaa35541cf8bc255175a62c7950b2241aac2f55
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang 2019-08-28 09:10:40 +08:00
parent a5ba41ceff
commit 2c6bab0663
2 changed files with 60 additions and 6 deletions
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27
drivers/clk/rockchip/clk.c
View File

@ -46,6 +46,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
u32 *mux_table,
int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
@ -68,6 +69,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
mux->table = mux_table;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
@ -308,6 +310,8 @@ static struct clk *rockchip_clk_register_frac_branch(
frac_mux->shift = child->mux_shift;
frac_mux->mask = BIT(child->mux_width) - 1;
frac_mux->flags = child->mux_flags;
if (child->mux_table)
frac_mux->table = child->mux_table;
frac_mux->lock = lock;
frac_mux->hw.init = &init;
@ -479,11 +483,21 @@ void __init rockchip_clk_register_branches(
/* catch simple muxes */
switch (list->branch_type) {
case branch_mux:
clk = clk_register_mux(NULL, list->name,
list->parent_names, list->num_parents,
flags, ctx->reg_base + list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, &ctx->lock);
if (list->mux_table)
clk = clk_register_mux_table(NULL, list->name,
list->parent_names, list->num_parents,
flags,
ctx->reg_base + list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, list->mux_table,
&ctx->lock);
else
clk = clk_register_mux(NULL, list->name,
list->parent_names, list->num_parents,
flags,
ctx->reg_base + list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags, &ctx->lock);
break;
case branch_muxgrf:
clk = rockchip_clk_register_muxgrf(list->name,
@ -548,7 +562,8 @@ void __init rockchip_clk_register_branches(
ctx->reg_base, list->muxdiv_offset,
list->mux_shift,
list->mux_width, list->mux_flags,
list->div_offset, list->div_shift, list->div_width,
list->mux_table, list->div_offset,
list->div_shift, list->div_width,
list->div_flags, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);

39
drivers/clk/rockchip/clk.h
View File

@ -449,6 +449,7 @@ struct rockchip_clk_branch {
u8 mux_shift;
u8 mux_width;
u8 mux_flags;
u32 *mux_table;
int div_offset;
u8 div_shift;
u8 div_width;
@ -482,6 +483,28 @@ struct rockchip_clk_branch {
.gate_flags = gf, \
}
#define COMPOSITE_MUXTBL(_id, cname, pnames, f, mo, ms, mw, mf, \
mt, ds, dw, df, go, gs, gf) \
{ \
.id = _id, \
.branch_type = branch_composite, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = mo, \
.mux_shift = ms, \
.mux_width = mw, \
.mux_flags = mf, \
.mux_table = mt, \
.div_shift = ds, \
.div_width = dw, \
.div_flags = df, \
.gate_offset = go, \
.gate_shift = gs, \
.gate_flags = gf, \
}
#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
mf, do, ds, dw, df, go, gs, gf) \
{ \
@ -685,6 +708,22 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
{ \
.id = _id, \
.branch_type = branch_mux, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = o, \
.mux_shift = s, \
.mux_width = w, \
.mux_flags = mf, \
.gate_offset = -1, \
.mux_table = mt, \
}
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
{ \
.id = _id, \