arm64: dts: ti: k3-j721e-main: Add CSI2 interrupts property

Add interrupts property for CSI2RX. Interrupt IDs are taken from the
J721E TRM [0].

Interrupt Line    | Source Interrupt
------------------|-------------------------
GIC500_SPI_IN_185 | CSI_RX_IF0_CSI_ERR_IRQ_0
GIC500_SPI_IN_184 | CSI_RX_IF0_CSI_IRQ_0
GIC500_SPI_IN_189 | CSI_RX_IF1_CSI_ERR_IRQ_0
GIC500_SPI_IN_188 | CSI_RX_IF1_CSI_IRQ_0

[0]: http://www.ti.com/lit/pdf/spruil1

Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Jared McArthur <j-mcarthur@ti.com>
Link: https://lore.kernel.org/r/20250808095804.544298-3-y-abhilashchandra@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Yemike Abhilash Chandra 2025-08-08 15:27:59 +05:30 committed by Nishanth Menon
parent 94801d4bf1
commit 33b34bfa4f

View File

@ -608,6 +608,9 @@ ti_csi2rx0: ticsi2rx@4500000 {
cdns_csi2rx0: csi-bridge@4504000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x0 0x4504000 0x0 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error_irq", "irq";
clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
<&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
@ -661,6 +664,9 @@ ti_csi2rx1: ticsi2rx@4510000 {
cdns_csi2rx1: csi-bridge@4514000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x0 0x4514000 0x0 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error_irq", "irq";
clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
<&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",