Minor improvements in DTS for v7.3

Several non-functional (white-space and style) changes to match with DTS
 coding style as reported by recent dt-check-style tool.
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Merge tag 'dt-cleanup-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

Minor improvements in DTS for v7.3

Several non-functional (white-space and style) changes to match with DTS
coding style as reported by recent dt-check-style tool.

* tag 'dt-cleanup-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  ARM: dts: Correct white-space style
  ARM: dts: nvidia: tegra114-asus-tf701t: Correct trailing whitespace
  ARM: dts: vt8500: Correct indentation
  ARM: dts: microchip: at91: Correct indentation
  ARM: dts: arm: Correct indentation
  ARM: dts: sigmastar: Correct indentation

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-08-10 18:02:55 +02:00
commit 334f983bb6
23 changed files with 129 additions and 129 deletions

View File

@ -51,7 +51,7 @@ vmmc: regulator-vmmc {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
#clock-cells = <0>;

View File

@ -53,7 +53,7 @@ vmmc: regulator-vmmc {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
veth: regulator-veth {
compatible = "regulator-fixed";

View File

@ -153,7 +153,7 @@ vmmc: regulator-vmmc {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
veth: regulator-veth {
compatible = "regulator-fixed";
@ -544,7 +544,7 @@ timer01: timer@10011000 {
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
arm,sp804-has-irq = <1>;
clocks = <&sp810_syscon 0>,
<&sp810_syscon 1>,
<&sp810_syscon 1>,
<&pclk>;
clock-names = "timer0clk",
"timer1clk",
@ -558,7 +558,7 @@ timer23: timer@10012000 {
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
arm,sp804-has-irq = <1>;
clocks = <&sp810_syscon 2>,
<&sp810_syscon 3>,
<&sp810_syscon 3>,
<&pclk>;
clock-names = "timer0clk",
"timer1clk",

View File

@ -52,7 +52,7 @@ vmmc: regulator-vmmc {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
veth: regulator-veth {
compatible = "regulator-fixed";
@ -373,7 +373,7 @@ timer01: timer@10011000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10011000 0x1000>;
clocks = <&sp810_syscon0 0>,
<&sp810_syscon0 1>,
<&sp810_syscon0 1>,
<&pclk>;
clock-names = "timerclk0",
"timerclk1",
@ -384,7 +384,7 @@ timer23: timer@10012000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10012000 0x1000>;
clocks = <&sp810_syscon0 2>,
<&sp810_syscon0 3>,
<&sp810_syscon0 3>,
<&pclk>;
clock-names = "timerclk2",
"timerclk3",

View File

@ -209,11 +209,11 @@ dma@7ff00000 {
clock-names = "apb_pclk";
};
scc@7fff0000 {
scc@7fff0000 {
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
reg = <0 0x7fff0000 0 0x1000>;
interrupts = <0 95 4>;
};
};
timer {
compatible = "arm,armv7-timer";

View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/ {
nvic: interrupt-controller@e000e100 {
nvic: interrupt-controller@e000e100 {
compatible = "arm,armv7m-nvic";
interrupt-controller;
#interrupt-cells = <1>;

View File

@ -141,7 +141,7 @@ mdio@200 {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch@0 {
compatible = "brcm,bcm53125";
#address-cells = <1>;
#size-cells = <0>;

View File

@ -30,12 +30,12 @@ pinctrl: pin-controller@10000 {
/* SATA Activity and Present pins are not connected */
pmx_sata0: pmx-sata0 {
marvell,pins ;
marvell,pins;
marvell,function = "sata0";
};
pmx_sata1: pmx-sata1 {
marvell,pins ;
marvell,pins;
marvell,function = "sata1";
};

View File

@ -35,7 +35,7 @@ led-4 {
};
};
led-controller-2 {
led-controller-2 {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_red
@ -58,7 +58,7 @@ led-6 {
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default" , "default", "default",
"default", "default" ;
"default", "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>;
pinctrl-2 = <&pinctrl_pio_io_boot
@ -170,7 +170,7 @@ verbose_bootloader {
input;
};
nail_bed_detection {
nail_bed_detection {
label = "nail bed detection";
gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>;
input;
@ -276,7 +276,7 @@ &uart4 {
&flx0 {
status = "okay";
uart5: serial@200 {
uart5: serial@200 {
status = "okay";
};
};

View File

@ -298,7 +298,7 @@ &flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "disabled";
uart5: serial@200 {
uart5: serial@200 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,use-dma-rx;

View File

@ -258,10 +258,10 @@ pinctrl_i2c1_default: i2c1_default {
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD4__GPIO>,
<PIN_PD5__GPIO>;
bias-disable;
};
pinmux = <PIN_PD4__GPIO>,
<PIN_PD5__GPIO>;
bias-disable;
};
pinctrl_isc_base: isc_base {

View File

@ -451,10 +451,10 @@ pinctrl_i2c1_default: i2c1_default {
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD19__GPIO>,
<PIN_PD20__GPIO>;
bias-disable;
};
pinmux = <PIN_PD19__GPIO>,
<PIN_PD20__GPIO>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PD0__GPIO>;

View File

@ -117,7 +117,7 @@ kernel@50000 {
reg = <0x50000 0x300000>;
};
root@350000 {
root@350000 {
label = "root";
reg = <0x350000 0x4B0000>;
};

View File

@ -64,7 +64,7 @@ fc3_b_pins: fc3-b-pins {
function = "fc3_b";
};
can0_b_pins: can0-b-pins {
can0_b_pins: can0-b-pins {
/* RX, TX */
pins = "GPIO_35", "GPIO_36";
function = "can0_b";

View File

@ -386,7 +386,7 @@ cam-i2c {
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
"ddc_sda_pv5";

View File

@ -7,17 +7,17 @@
#include "mstar-infinity.dtsi"
&cpu0_opp_table {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <300000>;
};
};
&cpus {

View File

@ -812,7 +812,7 @@ ethernet0: dwmac@9630000 {
<&clk_s_c0_flexgen CLK_ETH_PHY>;
};
mailbox0: mailbox@8f00000 {
mailbox0: mailbox@8f00000 {
compatible = "st,stih407-mailbox";
reg = <0x8f00000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

View File

@ -382,7 +382,7 @@ goodix: goodix-ts@5d {
VDDIO-supply = <&scmi_v3v3_sw>;
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
status = "okay" ;
status = "okay";
};
};

View File

@ -21,14 +21,14 @@ cpu@0 {
};
};
aliases {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
};
};
soc {
#address-cells = <1>;

View File

@ -21,7 +21,7 @@ cpu@0 {
};
};
aliases {
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
@ -147,12 +147,12 @@ clkddr: ddr {
};
clkuart0: uart0 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x250>;
enable-bit = <1>;
};
};
clkuart1: uart1 {
#clock-cells = <0>;

View File

@ -168,37 +168,37 @@ clkuart1: uart1 {
enable-bit = <25>;
};
clkuart2: uart2 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <26>;
};
clkuart2: uart2 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <26>;
};
clkuart3: uart3 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <27>;
};
clkuart3: uart3 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <27>;
};
clkuart4: uart4 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <28>;
};
clkuart4: uart4 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <28>;
};
clkuart5: uart5 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <29>;
};
clkuart5: uart5 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <29>;
};
clkpwm: pwm {
#clock-cells = <0>;
@ -286,37 +286,37 @@ uart1: serial@d82b0000 {
status = "disabled";
};
uart2: serial@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&clkuart2>;
uart2: serial@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&clkuart2>;
status = "disabled";
};
};
uart3: serial@d82c0000 {
compatible = "via,vt8500-uart";
reg = <0xd82c0000 0x1040>;
interrupts = <50>;
clocks = <&clkuart3>;
uart3: serial@d82c0000 {
compatible = "via,vt8500-uart";
reg = <0xd82c0000 0x1040>;
interrupts = <50>;
clocks = <&clkuart3>;
status = "disabled";
};
};
uart4: serial@d8370000 {
compatible = "via,vt8500-uart";
reg = <0xd8370000 0x1040>;
interrupts = <30>;
clocks = <&clkuart4>;
uart4: serial@d8370000 {
compatible = "via,vt8500-uart";
reg = <0xd8370000 0x1040>;
interrupts = <30>;
clocks = <&clkuart4>;
status = "disabled";
};
};
uart5: serial@d8380000 {
compatible = "via,vt8500-uart";
reg = <0xd8380000 0x1040>;
interrupts = <43>;
clocks = <&clkuart5>;
uart5: serial@d8380000 {
compatible = "via,vt8500-uart";
reg = <0xd8380000 0x1040>;
interrupts = <43>;
clocks = <&clkuart5>;
status = "disabled";
};
};
rtc@d8100000 {
compatible = "via,vt8500-rtc";

View File

@ -179,21 +179,21 @@ clkuart1: uart1 {
enable-bit = <25>;
};
clkuart2: uart2 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <26>;
};
clkuart2: uart2 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <26>;
};
clkuart3: uart3 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <27>;
};
clkuart3: uart3 {
#clock-cells = <0>;
compatible = "via,vt8500-device-clock";
clocks = <&ref24>;
enable-reg = <0x254>;
enable-bit = <27>;
};
clkpwm: pwm {
#clock-cells = <0>;
@ -273,21 +273,21 @@ uart1: serial@d82b0000 {
status = "disabled";
};
uart2: serial@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&clkuart2>;
uart2: serial@d8210000 {
compatible = "via,vt8500-uart";
reg = <0xd8210000 0x1040>;
interrupts = <47>;
clocks = <&clkuart2>;
status = "disabled";
};
};
uart3: serial@d82c0000 {
compatible = "via,vt8500-uart";
reg = <0xd82c0000 0x1040>;
interrupts = <50>;
clocks = <&clkuart3>;
uart3: serial@d82c0000 {
compatible = "via,vt8500-uart";
reg = <0xd82c0000 0x1040>;
interrupts = <50>;
clocks = <&clkuart3>;
status = "disabled";
};
};
rtc@d8100000 {
compatible = "via,vt8500-rtc";
@ -308,7 +308,7 @@ ethernet@d8004000 {
compatible = "via,vt8500-rhine";
reg = <0xd8004000 0x100>;
interrupts = <10>;
};
};
l2_cache: cache-controller@d9000000 {
compatible = "arm,pl310-cache";

View File

@ -92,8 +92,8 @@ partition@f00000 {
&sdhci1 {
status = "okay";
broken-cd ;
wp-inverted ;
broken-cd;
wp-inverted;
};
&uart0 {