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media: rockchip: isp1: support for isp new version in rk3326

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Change-Id: I226cc2d87053d1951252122c44b570030470ba42
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
This commit is contained in:
Hu Kejun 2018-07-14 11:58:54 +08:00 committed by Tao Huang
parent ffbd3042bc
commit 2ff670508e
8 changed files with 1006 additions and 318 deletions
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2
drivers/media/platform/rockchip/isp1/Kconfig
View File

@ -12,7 +12,7 @@ config VIDEO_ROCKCHIP_ISP1
Support for ISP1 on the rockchip SoC.
config VIDEO_ROCKCHIP_ISP_DPHY_SY
tristate "Rockchip Image Signal Processing v1 Unit driver"
tristate "Rockchip Image Signal Processing v1 Dphy driver"
depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
depends on ARCH_ROCKCHIP || COMPILE_TEST
default n

12
drivers/media/platform/rockchip/isp1/Makefile
View File

@ -2,9 +2,9 @@
obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += video_rkisp1.o
obj-$(CONFIG_VIDEO_ROCKCHIP_ISP_DPHY_SY) += mipi_dphy_sy.o
video_rkisp1-objs += rkisp1.o \
dev.o \
regs.o \
isp_stats.o \
isp_params.o \
capture.o
video_rkisp1-objs += rkisp1.o \
dev.o \
regs.o \
isp_stats.o \
isp_params.o \
capture.o

714
drivers/media/platform/rockchip/isp1/isp_params.c
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File diff suppressed because it is too large Load Diff

59
drivers/media/platform/rockchip/isp1/isp_params.h
View File

@ -38,6 +38,62 @@
#include <linux/rkisp1-config.h>
#include "common.h"
struct rkisp1_isp_params_vdev;
struct rkisp1_isp_params_ops {
void (*dpcc_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_dpcc_config *arg);
void (*bls_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_bls_config *arg);
void (*lsc_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_lsc_config *arg);
void (*lsc_matrix_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_lsc_config *pconfig);
void (*flt_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_flt_config *arg);
void (*bdm_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_bdm_config *arg);
void (*sdg_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_sdg_config *arg);
void (*goc_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_goc_config *arg);
void (*ctk_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_ctk_config *arg);
void (*ctk_enable)(struct rkisp1_isp_params_vdev *params_vdev,
bool en);
void (*awb_meas_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_awb_meas_config *arg);
void (*awb_meas_enable)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_awb_meas_config *arg,
bool en);
void (*awb_gain_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_awb_gain_config *arg);
void (*aec_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_aec_config *arg);
void (*cproc_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_cproc_config *arg);
void (*hst_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_hst_config *arg);
void (*hst_enable)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_hst_config *arg, bool en);
void (*afm_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_afc_config *arg);
void (*ie_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_ie_config *arg);
void (*ie_enable)(struct rkisp1_isp_params_vdev *params_vdev,
bool en);
void (*csm_config)(struct rkisp1_isp_params_vdev *params_vdev,
bool full_range);
void (*dpf_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_dpf_config *arg);
void (*dpf_strength_config)(struct rkisp1_isp_params_vdev *params_vdev,
const struct cifisp_dpf_strength_config *arg);
};
struct rkisp1_isp_params_config {
const int gamma_out_max_samples;
const int hst_weight_grids_size;
};
/*
* struct rkisp1_isp_subdev - ISP input parameters device
*
@ -57,6 +113,9 @@ struct rkisp1_isp_params_vdev {
enum v4l2_quantization quantization;
enum rkisp1_fmt_raw_pat_type raw_type;
struct rkisp1_isp_params_ops *ops;
struct rkisp1_isp_params_config *config;
};
/* config params before ISP streaming */

122
drivers/media/platform/rockchip/isp1/isp_stats.c
View File

@ -213,16 +213,16 @@ static int rkisp1_stats_init_vb2_queue(struct vb2_queue *q,
return vb2_queue_init(q);
}
static void rkisp1_stats_get_awb_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
/* Protect against concurrent access from ISR? */
u32 reg_val;
pbuf->meas_type |= CIFISP_STAT_AWB;
reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT);
reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10);
pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN);
reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10);
pbuf->params.awb.awb_mean[0].mean_cr_or_r =
CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
@ -232,17 +232,55 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
}
static void rkisp1_stats_get_aec_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
/* Protect against concurrent access from ISR? */
u32 reg_val;
pbuf->meas_type |= CIFISP_STAT_AWB;
reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12);
pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V12);
pbuf->params.awb.awb_mean[0].mean_cr_or_r =
CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
pbuf->params.awb.awb_mean[0].mean_cb_or_b =
CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
pbuf->params.awb.awb_mean[0].mean_y_or_g =
CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
}
static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
unsigned int i;
void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00;
void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00_V10;
pbuf->meas_type |= CIFISP_STAT_AUTOEXP;
for (i = 0; i < CIFISP_AE_MEAN_MAX; i++)
for (i = 0; i < stats_vdev->config->ae_mean_max; i++)
pbuf->params.ae.exp_mean[i] = (u8)readl(addr + i * 4);
}
static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
int i;
void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_V12;
u32 value;
pbuf->meas_type |= CIFISP_STAT_AUTOEXP;
for (i = 0; i < stats_vdev->config->ae_mean_max / 4; i++) {
value = readl(addr + i * 4);
pbuf->params.ae.exp_mean[4 * i + 0] = CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
pbuf->params.ae.exp_mean[4 * i + 1] = CIF_ISP_EXP_GET_MEAN_xy1_V12(value);
pbuf->params.ae.exp_mean[4 * i + 2] = CIF_ISP_EXP_GET_MEAN_xy2_V12(value);
pbuf->params.ae.exp_mean[4 * i + 3] = CIF_ISP_EXP_GET_MEAN_xy3_V12(value);
}
value = readl(addr + i * 4);
pbuf->params.ae.exp_mean[4 * i + 0] = CIF_ISP_EXP_GET_MEAN_xy0_V12(value);
}
static void rkisp1_stats_get_afc_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
@ -261,17 +299,32 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
af->window[2].lum = readl(base_addr + CIF_ISP_AFM_LUM_C);
}
static void rkisp1_stats_get_hst_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
int i;
void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_0;
void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_0_V10;
pbuf->meas_type |= CIFISP_STAT_HIST;
for (i = 0; i < CIFISP_HIST_BIN_N_MAX; i++)
for (i = 0; i < stats_vdev->config->hist_bin_n_max; i++)
pbuf->params.hist.hist_bins[i] = readl(addr + (i * 4));
}
static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
int i;
void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_V12;
u32 value;
pbuf->meas_type |= CIFISP_STAT_HIST;
for (i = 0; i < stats_vdev->config->hist_bin_n_max / 2; i++) {
value = readl(addr + (i * 4));
pbuf->params.hist.hist_bins[2 * i] = CIF_ISP_HIST_GET_BIN0_V12(value);
pbuf->params.hist.hist_bins[2 * i + 1] = CIF_ISP_HIST_GET_BIN1_V12(value);
}
}
static void rkisp1_stats_get_bls_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf)
{
@ -305,6 +358,32 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_isp_stats_vdev *stats_vdev,
}
}
static struct rkisp1_stats_ops rkisp1_v10_stats_ops = {
.get_awb_meas = rkisp1_stats_get_awb_meas_v10,
.get_aec_meas = rkisp1_stats_get_aec_meas_v10,
.get_afc_meas = rkisp1_stats_get_afc_meas,
.get_hst_meas = rkisp1_stats_get_hst_meas_v10,
.get_bls_meas = rkisp1_stats_get_bls_meas,
};
static struct rkisp1_stats_ops rkisp1_v12_stats_ops = {
.get_awb_meas = rkisp1_stats_get_awb_meas_v12,
.get_aec_meas = rkisp1_stats_get_aec_meas_v12,
.get_afc_meas = rkisp1_stats_get_afc_meas,
.get_hst_meas = rkisp1_stats_get_hst_meas_v12,
.get_bls_meas = rkisp1_stats_get_bls_meas,
};
static struct rkisp1_stats_config rkisp1_v10_stats_config = {
.ae_mean_max = 25,
.hist_bin_n_max = 16,
};
static struct rkisp1_stats_config rkisp1_v12_stats_config = {
.ae_mean_max = 81,
.hist_bin_n_max = 32,
};
static void
rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_isp_readout_work *meas_work)
@ -312,6 +391,7 @@ rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev,
unsigned int cur_frame_id = -1;
struct rkisp1_stat_buffer *cur_stat_buf;
struct rkisp1_buffer *cur_buf = NULL;
struct rkisp1_stats_ops *ops = stats_vdev->ops;
cur_frame_id = atomic_read(&stats_vdev->dev->isp_sdev.frm_sync_seq) - 1;
if (cur_frame_id != meas_work->frame_id) {
@ -337,23 +417,23 @@ rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev,
(struct rkisp1_stat_buffer *)(cur_buf->vaddr[0]);
if (meas_work->isp_ris & CIF_ISP_AWB_DONE) {
rkisp1_stats_get_awb_meas(stats_vdev, cur_stat_buf);
ops->get_awb_meas(stats_vdev, cur_stat_buf);
cur_stat_buf->meas_type |= CIFISP_STAT_AWB;
}
if (meas_work->isp_ris & CIF_ISP_AFM_FIN) {
rkisp1_stats_get_afc_meas(stats_vdev, cur_stat_buf);
ops->get_afc_meas(stats_vdev, cur_stat_buf);
cur_stat_buf->meas_type |= CIFISP_STAT_AFM_FIN;
}
if (meas_work->isp_ris & CIF_ISP_EXP_END) {
rkisp1_stats_get_aec_meas(stats_vdev, cur_stat_buf);
rkisp1_stats_get_bls_meas(stats_vdev, cur_stat_buf);
ops->get_aec_meas(stats_vdev, cur_stat_buf);
ops->get_bls_meas(stats_vdev, cur_stat_buf);
cur_stat_buf->meas_type |= CIFISP_STAT_AUTOEXP;
}
if (meas_work->isp_ris & CIF_ISP_HIST_MEASURE_RDY) {
rkisp1_stats_get_hst_meas(stats_vdev, cur_stat_buf);
ops->get_hst_meas(stats_vdev, cur_stat_buf);
cur_stat_buf->meas_type |= CIFISP_STAT_HIST;
}
@ -449,6 +529,14 @@ static void rkisp1_init_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev)
V4L2_META_FMT_RK_ISP1_STAT_3A;
stats_vdev->vdev_fmt.fmt.meta.buffersize =
sizeof(struct rkisp1_stat_buffer);
if (stats_vdev->dev->isp_ver == ISP_V12) {
stats_vdev->ops = &rkisp1_v12_stats_ops;
stats_vdev->config = &rkisp1_v12_stats_config;
} else {
stats_vdev->ops = &rkisp1_v10_stats_ops;
stats_vdev->config = &rkisp1_v10_stats_config;
}
}
int rkisp1_register_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev,

21
drivers/media/platform/rockchip/isp1/isp_stats.h
View File

@ -55,6 +55,24 @@ struct rkisp1_isp_readout_work {
struct vb2_buffer *vb;
};
struct rkisp1_stats_ops {
void (*get_awb_meas)(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf);
void (*get_aec_meas)(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf);
void (*get_afc_meas)(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf);
void (*get_hst_meas)(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf);
void (*get_bls_meas)(struct rkisp1_isp_stats_vdev *stats_vdev,
struct rkisp1_stat_buffer *pbuf);
};
struct rkisp1_stats_config {
const int ae_mean_max;
const int hist_bin_n_max;
};
/*
* struct rkisp1_isp_stats_vdev - ISP Statistics device
*
@ -73,6 +91,9 @@ struct rkisp1_isp_stats_vdev {
struct workqueue_struct *readout_wq;
struct mutex wq_lock;
struct rkisp1_stats_ops *ops;
struct rkisp1_stats_config *config;
};
int rkisp1_stats_isr(struct rkisp1_isp_stats_vdev *stats_vdev, u32 isp_ris);

384
drivers/media/platform/rockchip/isp1/regs.h
View File

@ -374,25 +374,57 @@
#define CIF_SUPER_IMP_CTRL_TRANSP_DIS BIT(2)
/* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
#define CIF_ISP_HIST_PROP_MODE_DIS (0 << 0)
#define CIF_ISP_HIST_PROP_MODE_RGB (1 << 0)
#define CIF_ISP_HIST_PROP_MODE_RED (2 << 0)
#define CIF_ISP_HIST_PROP_MODE_GREEN (3 << 0)
#define CIF_ISP_HIST_PROP_MODE_BLUE (4 << 0)
#define CIF_ISP_HIST_PROP_MODE_LUM (5 << 0)
#define CIF_ISP_HIST_PROP_MODE_MASK 0x7
#define CIF_ISP_HIST_PREDIV_SET(x) (((x) & 0x7F) << 3)
#define CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3) \
#define CIF_ISP_HIST_PROP_MODE_DIS_V10 (0 << 0)
#define CIF_ISP_HIST_PROP_MODE_RGB_V10 (1 << 0)
#define CIF_ISP_HIST_PROP_MODE_RED_V10 (2 << 0)
#define CIF_ISP_HIST_PROP_MODE_GREEN_V10 (3 << 0)
#define CIF_ISP_HIST_PROP_MODE_BLUE_V10 (4 << 0)
#define CIF_ISP_HIST_PROP_MODE_LUM_V10 (5 << 0)
#define CIF_ISP_HIST_PROP_MODE_MASK_V10 0x7
#define CIF_ISP_HIST_PREDIV_SET_V10(x) (((x) & 0x7F) << 3)
#define CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3) \
(((v0) & 0x1F) | (((v1) & 0x1F) << 8) |\
(((v2) & 0x1F) << 16) | \
(((v3) & 0x1F) << 24))
#define CIF_ISP_HIST_WINDOW_OFFSET_RESERVED 0xFFFFF000
#define CIF_ISP_HIST_WINDOW_SIZE_RESERVED 0xFFFFF800
#define CIF_ISP_HIST_WEIGHT_RESERVED 0xE0E0E0E0
#define CIF_ISP_MAX_HIST_PREDIVIDER 0x0000007F
#define CIF_ISP_HIST_ROW_NUM 5
#define CIF_ISP_HIST_COLUMN_NUM 5
#define CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10 0xFFFFF000
#define CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10 0xFFFFF800
#define CIF_ISP_HIST_WEIGHT_RESERVED_V10 0xE0E0E0E0
#define CIF_ISP_MAX_HIST_PREDIVIDER_V10 0x0000007F
#define CIF_ISP_HIST_ROW_NUM_V10 5
#define CIF_ISP_HIST_COLUMN_NUM_V10 5
/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
#define CIF_ISP_HIST_CTRL_EN_SET_V12(x) (((x) & 0x01) << 0)
#define CIF_ISP_HIST_CTRL_EN_MASK_V12 CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
#define CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x) (((x) & 0x7F) << 1)
#define CIF_ISP_HIST_CTRL_MODE_SET_V12(x) (((x) & 0x07) << 8)
#define CIF_ISP_HIST_CTRL_MODE_MASK_V12 CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
#define CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x) (((x) & 0x01) << 11)
#define CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x) (((x) & 0xFFF) << 12)
#define CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x) (((x) & 0x07) << 24)
#define CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x) (((x) & 0x01) << 27)
#define CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 28)
#define CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x) (((x) & 0x01) << 30)
#define CIF_ISP_HIST_ROW_NUM_V12 15
#define CIF_ISP_HIST_COLUMN_NUM_V12 15
#define CIF_ISP_HIST_WEIGHT_REG_SIZE_V12 \
(CIF_ISP_HIST_ROW_NUM_V12 * CIF_ISP_HIST_COLUMN_NUM_V12)
#define CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3) \
(((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
(((v2) & 0x3F) << 16) |\
(((v3) & 0x3F) << 24))
#define CIF_ISP_HIST_OFFS_SET_V12(v0, v1) \
(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
#define CIF_ISP_HIST_SIZE_SET_V12(v0, v1) \
(((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
#define CIF_ISP_HIST_GET_BIN0_V12(x) \
((x) & 0xFFFF)
#define CIF_ISP_HIST_GET_BIN1_V12(x) \
(((x) >> 16) & 0xFFFF)
/* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */
#define ISP_AFM_CTRL_ENABLE BIT(0)
@ -423,17 +455,18 @@
/* AWB */
/* ISP_AWB_PROP */
#define CIF_ISP_AWB_YMAX_CMP_EN BIT(2)
#define CIFISP_AWB_YMAX_READ(x) (((x) >> 2) & 1)
#define CIF_ISP_AWB_YMAX_READ(x) (((x) >> 2) & 1)
#define CIF_ISP_AWB_MODE_RGB_EN ((1 << 31) | (0x2 << 0))
#define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
#define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
#define CIF_ISP_AWB_MODE_MASK_NONE 0xFFFFFFFC
#define CIF_ISP_AWB_MODE_READ(x) ((x) & 3)
#define CIF_ISP_AWB_SET_FRAMES_V12(x) (((x) & 0x07) << 28)
#define CIF_ISP_AWB_SET_FRAMES_MASK_V12 CIF_ISP_AWB_SET_FRAMES_V12(0x07)
/* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G */
#define CIF_ISP_AWB_GAIN_R_SET(x) (((x) & 0x3FF) << 16)
#define CIF_ISP_AWB_GAIN_R_READ(x) (((x) >> 16) & 0x3FF)
#define CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FFF)
#define CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FFF)
#define CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FF)
#define CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FF)
/* ISP_AWB_REF */
#define CIF_ISP_AWB_REF_CR_SET(x) (((x) & 0xFF) << 8)
#define CIF_ISP_AWB_REF_CR_READ(x) (((x) >> 8) & 0xFF)
@ -463,6 +496,7 @@
/* ISP_EXP_CTRL */
#define CIF_ISP_EXP_ENA BIT(0)
#define CIF_ISP_EXP_CTRL_AUTOSTOP BIT(1)
#define CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 2)
/*
*'1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)
*'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
@ -470,43 +504,82 @@
#define CIF_ISP_EXP_CTRL_MEASMODE_1 BIT(31)
/* ISP_EXP_H_SIZE */
#define CIF_ISP_EXP_H_SIZE_SET(x) ((x) & 0x7FF)
#define CIF_ISP_EXP_HEIGHT_MASK 0x000007FF
#define CIF_ISP_EXP_H_SIZE_SET_V10(x) ((x) & 0x7FF)
#define CIF_ISP_EXP_HEIGHT_MASK_V10 0x000007FF
/* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
#define CIF_ISP_EXP_V_SIZE_SET(x) ((x) & 0x7FE)
#define CIF_ISP_EXP_V_SIZE_SET_V10(x) ((x) & 0x7FE)
/* ISP_EXP_H_OFFSET */
#define CIF_ISP_EXP_H_OFFSET_SET(x) ((x) & 0x1FFF)
#define CIF_ISP_EXP_MAX_HOFFS 2424
#define CIF_ISP_EXP_H_OFFSET_SET_V10(x) ((x) & 0x1FFF)
#define CIF_ISP_EXP_MAX_HOFFS_V10 2424
/* ISP_EXP_V_OFFSET */
#define CIF_ISP_EXP_V_OFFSET_SET(x) ((x) & 0x1FFF)
#define CIF_ISP_EXP_MAX_VOFFS 1806
#define CIF_ISP_EXP_V_OFFSET_SET_V10(x) ((x) & 0x1FFF)
#define CIF_ISP_EXP_MAX_VOFFS_V10 1806
#define CIF_ISP_EXP_ROW_NUM 5
#define CIF_ISP_EXP_COLUMN_NUM 5
#define CIF_ISP_EXP_NUM_LUMA_REGS \
(CIF_ISP_EXP_ROW_NUM * CIF_ISP_EXP_COLUMN_NUM)
#define CIF_ISP_EXP_BLOCK_MAX_HSIZE 516
#define CIF_ISP_EXP_BLOCK_MIN_HSIZE 35
#define CIF_ISP_EXP_BLOCK_MAX_VSIZE 390
#define CIF_ISP_EXP_BLOCK_MIN_VSIZE 28
#define CIF_ISP_EXP_MAX_HSIZE \
(CIF_ISP_EXP_BLOCK_MAX_HSIZE * CIF_ISP_EXP_COLUMN_NUM + 1)
#define CIF_ISP_EXP_MIN_HSIZE \
(CIF_ISP_EXP_BLOCK_MIN_HSIZE * CIF_ISP_EXP_COLUMN_NUM + 1)
#define CIF_ISP_EXP_MAX_VSIZE \
(CIF_ISP_EXP_BLOCK_MAX_VSIZE * CIF_ISP_EXP_ROW_NUM + 1)
#define CIF_ISP_EXP_MIN_VSIZE \
(CIF_ISP_EXP_BLOCK_MIN_VSIZE * CIF_ISP_EXP_ROW_NUM + 1)
#define CIF_ISP_EXP_ROW_NUM_V10 5
#define CIF_ISP_EXP_COLUMN_NUM_V10 5
#define CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
(CIF_ISP_EXP_ROW_NUM_V10 * CIF_ISP_EXP_COLUMN_NUM_V10)
#define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 516
#define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 35
#define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 390
#define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 28
#define CIF_ISP_EXP_MAX_HSIZE_V10 \
(CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
#define CIF_ISP_EXP_MIN_HSIZE_V10 \
(CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
#define CIF_ISP_EXP_MAX_VSIZE_V10 \
(CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1)
#define CIF_ISP_EXP_MIN_VSIZE_V10 \
(CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1)
/* ISP_EXP_H_SIZE */
#define CIF_ISP_EXP_H_SIZE_SET_V12(x) ((x) & 0x7FF)
#define CIF_ISP_EXP_HEIGHT_MASK_V12 0x000007FF
/* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
#define CIF_ISP_EXP_V_SIZE_SET_V12(x) (((x) & 0x7FE) << 16)
/* ISP_EXP_H_OFFSET */
#define CIF_ISP_EXP_H_OFFSET_SET_V12(x) ((x) & 0x1FFF)
#define CIF_ISP_EXP_MAX_HOFFS_V12 0x1FFF
/* ISP_EXP_V_OFFSET */
#define CIF_ISP_EXP_V_OFFSET_SET_V12(x) (((x) & 0x1FFF) << 16)
#define CIF_ISP_EXP_MAX_VOFFS_V12 0x1FFF
#define CIF_ISP_EXP_ROW_NUM_V12 15
#define CIF_ISP_EXP_COLUMN_NUM_V12 15
#define CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
(CIF_ISP_EXP_ROW_NUM_V12 * CIF_ISP_EXP_COLUMN_NUM_V12)
#define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 0x7FF
#define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 0xE
#define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 0x7FE
#define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 0xE
#define CIF_ISP_EXP_MAX_HSIZE_V12 \
(CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
#define CIF_ISP_EXP_MIN_HSIZE_V12 \
(CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
#define CIF_ISP_EXP_MAX_VSIZE_V12 \
(CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1)
#define CIF_ISP_EXP_MIN_VSIZE_V12 \
(CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1)
#define CIF_ISP_EXP_GET_MEAN_xy0_V12(x) ((x) & 0xFF)
#define CIF_ISP_EXP_GET_MEAN_xy1_V12(x) (((x) >> 8) & 0xFF)
#define CIF_ISP_EXP_GET_MEAN_xy2_V12(x) (((x) >> 16) & 0xFF)
#define CIF_ISP_EXP_GET_MEAN_xy3_V12(x) (((x) >> 24) & 0xFF)
/* LSC: ISP_LSC_CTRL */
#define CIF_ISP_LSC_CTRL_ENA BIT(0)
#define CIF_ISP_LSC_SECT_SIZE_RESERVED 0xFC00FC00
#define CIF_ISP_LSC_GRAD_RESERVED 0xF000F000
#define CIF_ISP_LSC_SAMPLE_RESERVED 0xF000F000
#define CIF_ISP_LSC_GRAD_RESERVED_V10 0xF000F000
#define CIF_ISP_LSC_SAMPLE_RESERVED_V10 0xF000F000
#define CIF_ISP_LSC_GRAD_RESERVED_V12 0xE000E000
#define CIF_ISP_LSC_SAMPLE_RESERVED_V12 0xE000E000
#define CIF_ISP_LSC_SECTORS_MAX 17
#define CIF_ISP_LSC_TABLE_DATA(v0, v1) \
#define CIF_ISP_LSC_TABLE_DATA_V10(v0, v1) \
(((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
#define CIF_ISP_LSC_TABLE_DATA_V12(v0, v1) \
(((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
#define CIF_ISP_LSC_SECT_SIZE(v0, v1) \
(((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
#define CIF_ISP_LSC_GRAD_SIZE(v0, v1) \
@ -579,6 +652,10 @@
(1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
#define CIFISP_DEGAMMA_Y_RESERVED 0xFFFFF000
/* GAMMA-OUT */
#define CIF_ISP_GAMMA_REG_VALUE_V12(x, y) \
(((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
/* AFM */
#define CIF_ISP_AFM_ENA BIT(0)
#define CIF_ISP_AFM_THRES_RESERVED 0xFFFF0000
@ -589,6 +666,11 @@
#define CIF_ISP_AFM_WINDOW_Y_MIN 0x2
#define CIF_ISP_AFM_WINDOW_X(x) (((x) & 0x1FFF) << 16)
#define CIF_ISP_AFM_WINDOW_Y(x) ((x) & 0x1FFF)
#define CIF_ISP_AFM_SET_SHIFT_a_V12(x, y) (((x) & 0x7) << 16 | ((y) & 0x7) << 0)
#define CIF_ISP_AFM_SET_SHIFT_b_V12(x, y) (((x) & 0x7) << 20 | ((y) & 0x7) << 4)
#define CIF_ISP_AFM_SET_SHIFT_c_V12(x, y) (((x) & 0x7) << 24 | ((y) & 0x7) << 8)
#define CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x) (((x) & 0x70000) >> 16)
#define CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x) ((x) & 0x7)
/* DPF */
#define CIF_ISP_DPF_MODE_EN BIT(0)
@ -696,18 +778,38 @@
#define CIF_ISP_GAMMA_B_Y14 (CIF_ISP_BASE + 0x000000E4)
#define CIF_ISP_GAMMA_B_Y15 (CIF_ISP_BASE + 0x000000E8)
#define CIF_ISP_GAMMA_B_Y16 (CIF_ISP_BASE + 0x000000EC)
#define CIF_ISP_AWB_PROP (CIF_ISP_BASE + 0x00000110)
#define CIF_ISP_AWB_WND_H_OFFS (CIF_ISP_BASE + 0x00000114)
#define CIF_ISP_AWB_WND_V_OFFS (CIF_ISP_BASE + 0x00000118)
#define CIF_ISP_AWB_WND_H_SIZE (CIF_ISP_BASE + 0x0000011C)
#define CIF_ISP_AWB_WND_V_SIZE (CIF_ISP_BASE + 0x00000120)
#define CIF_ISP_AWB_FRAMES (CIF_ISP_BASE + 0x00000124)
#define CIF_ISP_AWB_REF (CIF_ISP_BASE + 0x00000128)
#define CIF_ISP_AWB_THRESH (CIF_ISP_BASE + 0x0000012C)
#define CIF_ISP_AWB_GAIN_G (CIF_ISP_BASE + 0x00000138)
#define CIF_ISP_AWB_GAIN_RB (CIF_ISP_BASE + 0x0000013C)
#define CIF_ISP_AWB_WHITE_CNT (CIF_ISP_BASE + 0x00000140)
#define CIF_ISP_AWB_MEAN (CIF_ISP_BASE + 0x00000144)
#define CIF_ISP_AWB_PROP_V10 (CIF_ISP_BASE + 0x00000110)
#define CIF_ISP_AWB_WND_H_OFFS_V10 (CIF_ISP_BASE + 0x00000114)
#define CIF_ISP_AWB_WND_V_OFFS_V10 (CIF_ISP_BASE + 0x00000118)
#define CIF_ISP_AWB_WND_H_SIZE_V10 (CIF_ISP_BASE + 0x0000011C)
#define CIF_ISP_AWB_WND_V_SIZE_V10 (CIF_ISP_BASE + 0x00000120)
#define CIF_ISP_AWB_FRAMES_V10 (CIF_ISP_BASE + 0x00000124)
#define CIF_ISP_AWB_REF_V10 (CIF_ISP_BASE + 0x00000128)
#define CIF_ISP_AWB_THRESH_V10 (CIF_ISP_BASE + 0x0000012C)
#define CIF_ISP_AWB_GAIN_G_V10 (CIF_ISP_BASE + 0x00000138)
#define CIF_ISP_AWB_GAIN_RB_V10 (CIF_ISP_BASE + 0x0000013C)
#define CIF_ISP_AWB_WHITE_CNT_V10 (CIF_ISP_BASE + 0x00000140)
#define CIF_ISP_AWB_MEAN_V10 (CIF_ISP_BASE + 0x00000144)
#define CIF_ISP_AWB_PROP_V12 (CIF_ISP_BASE + 0x00000110)
#define CIF_ISP_AWB_SIZE_V12 (CIF_ISP_BASE + 0x00000114)
#define CIF_ISP_AWB_OFFS_V12 (CIF_ISP_BASE + 0x00000118)
#define CIF_ISP_AWB_REF_V12 (CIF_ISP_BASE + 0x0000011C)
#define CIF_ISP_AWB_THRESH_V12 (CIF_ISP_BASE + 0x00000120)
#define CIF_ISP_X_COOR12_V12 (CIF_ISP_BASE + 0x00000124)
#define CIF_ISP_X_COOR34_V12 (CIF_ISP_BASE + 0x00000128)
#define CIF_ISP_AWB_WHITE_CNT_V12 (CIF_ISP_BASE + 0x0000012C)
#define CIF_ISP_AWB_MEAN_V12 (CIF_ISP_BASE + 0x00000130)
#define CIF_ISP_DEGAIN_V12 (CIF_ISP_BASE + 0x00000134)
#define CIF_ISP_AWB_GAIN_G_V12 (CIF_ISP_BASE + 0x00000138)
#define CIF_ISP_AWB_GAIN_RB_V12 (CIF_ISP_BASE + 0x0000013C)
#define CIF_ISP_REGION_LINE_V12 (CIF_ISP_BASE + 0x00000140)
#define CIF_ISP_WP_CNT_REGION0_V12 (CIF_ISP_BASE + 0x00000160)
#define CIF_ISP_WP_CNT_REGION1_V12 (CIF_ISP_BASE + 0x00000164)
#define CIF_ISP_WP_CNT_REGION2_V12 (CIF_ISP_BASE + 0x00000168)
#define CIF_ISP_WP_CNT_REGION3_V12 (CIF_ISP_BASE + 0x0000016C)
#define CIF_ISP_CC_COEFF_0 (CIF_ISP_BASE + 0x00000170)
#define CIF_ISP_CC_COEFF_1 (CIF_ISP_BASE + 0x00000174)
#define CIF_ISP_CC_COEFF_2 (CIF_ISP_BASE + 0x00000178)
@ -741,30 +843,32 @@
#define CIF_ISP_CT_COEFF_6 (CIF_ISP_BASE + 0x000001E8)
#define CIF_ISP_CT_COEFF_7 (CIF_ISP_BASE + 0x000001EC)
#define CIF_ISP_CT_COEFF_8 (CIF_ISP_BASE + 0x000001F0)
#define CIF_ISP_GAMMA_OUT_MODE (CIF_ISP_BASE + 0x000001F4)
#define CIF_ISP_GAMMA_OUT_Y_0 (CIF_ISP_BASE + 0x000001F8)
#define CIF_ISP_GAMMA_OUT_Y_1 (CIF_ISP_BASE + 0x000001FC)
#define CIF_ISP_GAMMA_OUT_Y_2 (CIF_ISP_BASE + 0x00000200)
#define CIF_ISP_GAMMA_OUT_Y_3 (CIF_ISP_BASE + 0x00000204)
#define CIF_ISP_GAMMA_OUT_Y_4 (CIF_ISP_BASE + 0x00000208)
#define CIF_ISP_GAMMA_OUT_Y_5 (CIF_ISP_BASE + 0x0000020C)
#define CIF_ISP_GAMMA_OUT_Y_6 (CIF_ISP_BASE + 0x00000210)
#define CIF_ISP_GAMMA_OUT_Y_7 (CIF_ISP_BASE + 0x00000214)
#define CIF_ISP_GAMMA_OUT_Y_8 (CIF_ISP_BASE + 0x00000218)
#define CIF_ISP_GAMMA_OUT_Y_9 (CIF_ISP_BASE + 0x0000021C)
#define CIF_ISP_GAMMA_OUT_Y_10 (CIF_ISP_BASE + 0x00000220)
#define CIF_ISP_GAMMA_OUT_Y_11 (CIF_ISP_BASE + 0x00000224)
#define CIF_ISP_GAMMA_OUT_Y_12 (CIF_ISP_BASE + 0x00000228)
#define CIF_ISP_GAMMA_OUT_Y_13 (CIF_ISP_BASE + 0x0000022C)
#define CIF_ISP_GAMMA_OUT_Y_14 (CIF_ISP_BASE + 0x00000230)
#define CIF_ISP_GAMMA_OUT_Y_15 (CIF_ISP_BASE + 0x00000234)
#define CIF_ISP_GAMMA_OUT_Y_16 (CIF_ISP_BASE + 0x00000238)
#define CIF_ISP_GAMMA_OUT_MODE_V10 (CIF_ISP_BASE + 0x000001F4)
#define CIF_ISP_GAMMA_OUT_Y_0_V10 (CIF_ISP_BASE + 0x000001F8)
#define CIF_ISP_GAMMA_OUT_Y_1_V10 (CIF_ISP_BASE + 0x000001FC)
#define CIF_ISP_GAMMA_OUT_Y_2_V10 (CIF_ISP_BASE + 0x00000200)
#define CIF_ISP_GAMMA_OUT_Y_3_V10 (CIF_ISP_BASE + 0x00000204)
#define CIF_ISP_GAMMA_OUT_Y_4_V10 (CIF_ISP_BASE + 0x00000208)
#define CIF_ISP_GAMMA_OUT_Y_5_V10 (CIF_ISP_BASE + 0x0000020C)
#define CIF_ISP_GAMMA_OUT_Y_6_V10 (CIF_ISP_BASE + 0x00000210)
#define CIF_ISP_GAMMA_OUT_Y_7_V10 (CIF_ISP_BASE + 0x00000214)
#define CIF_ISP_GAMMA_OUT_Y_8_V10 (CIF_ISP_BASE + 0x00000218)
#define CIF_ISP_GAMMA_OUT_Y_9_V10 (CIF_ISP_BASE + 0x0000021C)
#define CIF_ISP_GAMMA_OUT_Y_10_V10 (CIF_ISP_BASE + 0x00000220)
#define CIF_ISP_GAMMA_OUT_Y_11_V10 (CIF_ISP_BASE + 0x00000224)
#define CIF_ISP_GAMMA_OUT_Y_12_V10 (CIF_ISP_BASE + 0x00000228)
#define CIF_ISP_GAMMA_OUT_Y_13_V10 (CIF_ISP_BASE + 0x0000022C)
#define CIF_ISP_GAMMA_OUT_Y_14_V10 (CIF_ISP_BASE + 0x00000230)
#define CIF_ISP_GAMMA_OUT_Y_15_V10 (CIF_ISP_BASE + 0x00000234)
#define CIF_ISP_GAMMA_OUT_Y_16_V10 (CIF_ISP_BASE + 0x00000238)
#define CIF_ISP_ERR (CIF_ISP_BASE + 0x0000023C)
#define CIF_ISP_ERR_CLR (CIF_ISP_BASE + 0x00000240)
#define CIF_ISP_FRAME_COUNT (CIF_ISP_BASE + 0x00000244)
#define CIF_ISP_CT_OFFSET_R (CIF_ISP_BASE + 0x00000248)
#define CIF_ISP_CT_OFFSET_G (CIF_ISP_BASE + 0x0000024C)
#define CIF_ISP_CT_OFFSET_B (CIF_ISP_BASE + 0x00000250)
#define CIF_ISP_GAMMA_OUT_MODE_V12 (CIF_ISP_BASE + 0x00000300)
#define CIF_ISP_GAMMA_OUT_Y_0_V12 (CIF_ISP_BASE + 0x00000304)
#define CIF_ISP_FLASH_BASE 0x00000660
#define CIF_ISP_FLASH_CMD (CIF_ISP_FLASH_BASE + 0x00000000)
@ -1034,36 +1138,35 @@
#define CIF_ISP_IS_H_SIZE_SHD (CIF_ISP_IS_BASE + 0x0000002C)
#define CIF_ISP_IS_V_SIZE_SHD (CIF_ISP_IS_BASE + 0x00000030)
#define CIF_ISP_HIST_BASE 0x00002400
#define CIF_ISP_HIST_PROP (CIF_ISP_HIST_BASE + 0x00000000)
#define CIF_ISP_HIST_H_OFFS (CIF_ISP_HIST_BASE + 0x00000004)
#define CIF_ISP_HIST_V_OFFS (CIF_ISP_HIST_BASE + 0x00000008)
#define CIF_ISP_HIST_H_SIZE (CIF_ISP_HIST_BASE + 0x0000000C)
#define CIF_ISP_HIST_V_SIZE (CIF_ISP_HIST_BASE + 0x00000010)
#define CIF_ISP_HIST_BIN_0 (CIF_ISP_HIST_BASE + 0x00000014)
#define CIF_ISP_HIST_BIN_1 (CIF_ISP_HIST_BASE + 0x00000018)
#define CIF_ISP_HIST_BIN_2 (CIF_ISP_HIST_BASE + 0x0000001C)
#define CIF_ISP_HIST_BIN_3 (CIF_ISP_HIST_BASE + 0x00000020)
#define CIF_ISP_HIST_BIN_4 (CIF_ISP_HIST_BASE + 0x00000024)
#define CIF_ISP_HIST_BIN_5 (CIF_ISP_HIST_BASE + 0x00000028)
#define CIF_ISP_HIST_BIN_6 (CIF_ISP_HIST_BASE + 0x0000002C)
#define CIF_ISP_HIST_BIN_7 (CIF_ISP_HIST_BASE + 0x00000030)
#define CIF_ISP_HIST_BIN_8 (CIF_ISP_HIST_BASE + 0x00000034)
#define CIF_ISP_HIST_BIN_9 (CIF_ISP_HIST_BASE + 0x00000038)
#define CIF_ISP_HIST_BIN_10 (CIF_ISP_HIST_BASE + 0x0000003C)
#define CIF_ISP_HIST_BIN_11 (CIF_ISP_HIST_BASE + 0x00000040)
#define CIF_ISP_HIST_BIN_12 (CIF_ISP_HIST_BASE + 0x00000044)
#define CIF_ISP_HIST_BIN_13 (CIF_ISP_HIST_BASE + 0x00000048)
#define CIF_ISP_HIST_BIN_14 (CIF_ISP_HIST_BASE + 0x0000004C)
#define CIF_ISP_HIST_BIN_15 (CIF_ISP_HIST_BASE + 0x00000050)
#define CIF_ISP_HIST_WEIGHT_00TO30 (CIF_ISP_HIST_BASE + 0x00000054)
#define CIF_ISP_HIST_WEIGHT_40TO21 (CIF_ISP_HIST_BASE + 0x00000058)
#define CIF_ISP_HIST_WEIGHT_31TO12 (CIF_ISP_HIST_BASE + 0x0000005C)
#define CIF_ISP_HIST_WEIGHT_22TO03 (CIF_ISP_HIST_BASE + 0x00000060)
#define CIF_ISP_HIST_WEIGHT_13TO43 (CIF_ISP_HIST_BASE + 0x00000064)
#define CIF_ISP_HIST_WEIGHT_04TO34 (CIF_ISP_HIST_BASE + 0x00000068)
#define CIF_ISP_HIST_WEIGHT_44 (CIF_ISP_HIST_BASE + 0x0000006C)
#define CIF_ISP_HIST_BASE_V10 0x00002400
#define CIF_ISP_HIST_PROP_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000000)
#define CIF_ISP_HIST_H_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000004)
#define CIF_ISP_HIST_V_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000008)
#define CIF_ISP_HIST_H_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000000C)
#define CIF_ISP_HIST_V_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000010)
#define CIF_ISP_HIST_BIN_0_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000014)
#define CIF_ISP_HIST_BIN_1_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000018)
#define CIF_ISP_HIST_BIN_2_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000001C)
#define CIF_ISP_HIST_BIN_3_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000020)
#define CIF_ISP_HIST_BIN_4_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000024)
#define CIF_ISP_HIST_BIN_5_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000028)
#define CIF_ISP_HIST_BIN_6_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000002C)
#define CIF_ISP_HIST_BIN_7_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000030)
#define CIF_ISP_HIST_BIN_8_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000034)
#define CIF_ISP_HIST_BIN_9_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000038)
#define CIF_ISP_HIST_BIN_10_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000003C)
#define CIF_ISP_HIST_BIN_11_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000040)
#define CIF_ISP_HIST_BIN_12_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000044)
#define CIF_ISP_HIST_BIN_13_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000048)
#define CIF_ISP_HIST_BIN_14_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000004C)
#define CIF_ISP_HIST_BIN_15_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000050)
#define CIF_ISP_HIST_WEIGHT_00TO30_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000054)
#define CIF_ISP_HIST_WEIGHT_40TO21_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000058)
#define CIF_ISP_HIST_WEIGHT_31TO12_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000005C)
#define CIF_ISP_HIST_WEIGHT_22TO03_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000060)
#define CIF_ISP_HIST_WEIGHT_13TO43_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000064)
#define CIF_ISP_HIST_WEIGHT_04TO34_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000068)
#define CIF_ISP_HIST_WEIGHT_44_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000006C)
#define CIF_ISP_FILT_BASE 0x00002500
#define CIF_ISP_FILT_MODE (CIF_ISP_FILT_BASE + 0x00000000)
@ -1089,35 +1192,38 @@
#define CIF_ISP_EXP_BASE 0x00002600
#define CIF_ISP_EXP_CTRL (CIF_ISP_EXP_BASE + 0x00000000)
#define CIF_ISP_EXP_H_OFFSET (CIF_ISP_EXP_BASE + 0x00000004)
#define CIF_ISP_EXP_V_OFFSET (CIF_ISP_EXP_BASE + 0x00000008)
#define CIF_ISP_EXP_H_SIZE (CIF_ISP_EXP_BASE + 0x0000000C)
#define CIF_ISP_EXP_V_SIZE (CIF_ISP_EXP_BASE + 0x00000010)
#define CIF_ISP_EXP_MEAN_00 (CIF_ISP_EXP_BASE + 0x00000014)
#define CIF_ISP_EXP_MEAN_10 (CIF_ISP_EXP_BASE + 0x00000018)
#define CIF_ISP_EXP_MEAN_20 (CIF_ISP_EXP_BASE + 0x0000001c)
#define CIF_ISP_EXP_MEAN_30 (CIF_ISP_EXP_BASE + 0x00000020)
#define CIF_ISP_EXP_MEAN_40 (CIF_ISP_EXP_BASE + 0x00000024)
#define CIF_ISP_EXP_MEAN_01 (CIF_ISP_EXP_BASE + 0x00000028)
#define CIF_ISP_EXP_MEAN_11 (CIF_ISP_EXP_BASE + 0x0000002c)
#define CIF_ISP_EXP_MEAN_21 (CIF_ISP_EXP_BASE + 0x00000030)
#define CIF_ISP_EXP_MEAN_31 (CIF_ISP_EXP_BASE + 0x00000034)
#define CIF_ISP_EXP_MEAN_41 (CIF_ISP_EXP_BASE + 0x00000038)
#define CIF_ISP_EXP_MEAN_02 (CIF_ISP_EXP_BASE + 0x0000003c)
#define CIF_ISP_EXP_MEAN_12 (CIF_ISP_EXP_BASE + 0x00000040)
#define CIF_ISP_EXP_MEAN_22 (CIF_ISP_EXP_BASE + 0x00000044)
#define CIF_ISP_EXP_MEAN_32 (CIF_ISP_EXP_BASE + 0x00000048)
#define CIF_ISP_EXP_MEAN_42 (CIF_ISP_EXP_BASE + 0x0000004c)
#define CIF_ISP_EXP_MEAN_03 (CIF_ISP_EXP_BASE + 0x00000050)
#define CIF_ISP_EXP_MEAN_13 (CIF_ISP_EXP_BASE + 0x00000054)
#define CIF_ISP_EXP_MEAN_23 (CIF_ISP_EXP_BASE + 0x00000058)
#define CIF_ISP_EXP_MEAN_33 (CIF_ISP_EXP_BASE + 0x0000005c)
#define CIF_ISP_EXP_MEAN_43 (CIF_ISP_EXP_BASE + 0x00000060)
#define CIF_ISP_EXP_MEAN_04 (CIF_ISP_EXP_BASE + 0x00000064)
#define CIF_ISP_EXP_MEAN_14 (CIF_ISP_EXP_BASE + 0x00000068)
#define CIF_ISP_EXP_MEAN_24 (CIF_ISP_EXP_BASE + 0x0000006c)
#define CIF_ISP_EXP_MEAN_34 (CIF_ISP_EXP_BASE + 0x00000070)
#define CIF_ISP_EXP_MEAN_44 (CIF_ISP_EXP_BASE + 0x00000074)
#define CIF_ISP_EXP_H_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000004)
#define CIF_ISP_EXP_V_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000008)
#define CIF_ISP_EXP_H_SIZE_V10 (CIF_ISP_EXP_BASE + 0x0000000C)
#define CIF_ISP_EXP_V_SIZE_V10 (CIF_ISP_EXP_BASE + 0x00000010)
#define CIF_ISP_EXP_SIZE_V12 (CIF_ISP_EXP_BASE + 0x00000004)
#define CIF_ISP_EXP_OFFS_V12 (CIF_ISP_EXP_BASE + 0x00000008)
#define CIF_ISP_EXP_MEAN_V12 (CIF_ISP_EXP_BASE + 0x0000000c)
#define CIF_ISP_EXP_MEAN_00_V10 (CIF_ISP_EXP_BASE + 0x00000014)
#define CIF_ISP_EXP_MEAN_10_V10 (CIF_ISP_EXP_BASE + 0x00000018)
#define CIF_ISP_EXP_MEAN_20_V10 (CIF_ISP_EXP_BASE + 0x0000001c)
#define CIF_ISP_EXP_MEAN_30_V10 (CIF_ISP_EXP_BASE + 0x00000020)
#define CIF_ISP_EXP_MEAN_40_V10 (CIF_ISP_EXP_BASE + 0x00000024)
#define CIF_ISP_EXP_MEAN_01_V10 (CIF_ISP_EXP_BASE + 0x00000028)
#define CIF_ISP_EXP_MEAN_11_V10 (CIF_ISP_EXP_BASE + 0x0000002c)
#define CIF_ISP_EXP_MEAN_21_V10 (CIF_ISP_EXP_BASE + 0x00000030)
#define CIF_ISP_EXP_MEAN_31_V10 (CIF_ISP_EXP_BASE + 0x00000034)
#define CIF_ISP_EXP_MEAN_41_V10 (CIF_ISP_EXP_BASE + 0x00000038)
#define CIF_ISP_EXP_MEAN_02_V10 (CIF_ISP_EXP_BASE + 0x0000003c)
#define CIF_ISP_EXP_MEAN_12_V10 (CIF_ISP_EXP_BASE + 0x00000040)
#define CIF_ISP_EXP_MEAN_22_V10 (CIF_ISP_EXP_BASE + 0x00000044)
#define CIF_ISP_EXP_MEAN_32_V10 (CIF_ISP_EXP_BASE + 0x00000048)
#define CIF_ISP_EXP_MEAN_42_V10 (CIF_ISP_EXP_BASE + 0x0000004c)
#define CIF_ISP_EXP_MEAN_03_V10 (CIF_ISP_EXP_BASE + 0x00000050)
#define CIF_ISP_EXP_MEAN_13_V10 (CIF_ISP_EXP_BASE + 0x00000054)
#define CIF_ISP_EXP_MEAN_23_V10 (CIF_ISP_EXP_BASE + 0x00000058)
#define CIF_ISP_EXP_MEAN_33_V10 (CIF_ISP_EXP_BASE + 0x0000005c)
#define CIF_ISP_EXP_MEAN_43_V10 (CIF_ISP_EXP_BASE + 0x00000060)
#define CIF_ISP_EXP_MEAN_04_V10 (CIF_ISP_EXP_BASE + 0x00000064)
#define CIF_ISP_EXP_MEAN_14_V10 (CIF_ISP_EXP_BASE + 0x00000068)
#define CIF_ISP_EXP_MEAN_24_V10 (CIF_ISP_EXP_BASE + 0x0000006c)
#define CIF_ISP_EXP_MEAN_34_V10 (CIF_ISP_EXP_BASE + 0x00000070)
#define CIF_ISP_EXP_MEAN_44_V10 (CIF_ISP_EXP_BASE + 0x00000074)
#define CIF_ISP_BLS_BASE 0x00002700
#define CIF_ISP_BLS_CTRL (CIF_ISP_BLS_BASE + 0x00000000)
@ -1278,6 +1384,16 @@
#define CIF_ISP_WDR_TONECURVE_YM_31_SHD (CIF_ISP_WDR_BASE + 0x0000012C)
#define CIF_ISP_WDR_TONECURVE_YM_32_SHD (CIF_ISP_WDR_BASE + 0x00000130)
#define CIF_ISP_HIST_BASE_V12 0x00002C00
#define CIF_ISP_HIST_CTRL_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000000)
#define CIF_ISP_HIST_SIZE_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000004)
#define CIF_ISP_HIST_OFFS_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000008)
#define CIF_ISP_HIST_DBG1_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000000C)
#define CIF_ISP_HIST_DBG2_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000001C)
#define CIF_ISP_HIST_DBG3_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000002C)
#define CIF_ISP_HIST_WEIGHT_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000003C)
#define CIF_ISP_HIST_BIN_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000120)
#define CIF_ISP_VSM_BASE 0x00002F00
#define CIF_ISP_VSM_MODE (CIF_ISP_VSM_BASE + 0x00000000)
#define CIF_ISP_VSM_H_OFFS (CIF_ISP_VSM_BASE + 0x00000004)

10
include/uapi/linux/rkisp1-config.h
View File

@ -32,8 +32,8 @@
#define CIFISP_CTK_COEFF_MAX 0x100
#define CIFISP_CTK_OFFSET_MAX 0x800
#define CIFISP_AE_MEAN_MAX 25
#define CIFISP_HIST_BIN_N_MAX 16
#define CIFISP_AE_MEAN_MAX 81
#define CIFISP_HIST_BIN_N_MAX 32
#define CIFISP_AFM_MAX_WINDOWS 3
#define CIFISP_DEGAMMA_CURVE_SIZE 17
@ -69,7 +69,7 @@
* Gamma out
*/
/* Maximum number of color samples supported */
#define CIFISP_GAMMA_OUT_MAX_SAMPLES 17
#define CIFISP_GAMMA_OUT_MAX_SAMPLES 34
/*
* Lens shade correction
@ -87,7 +87,7 @@
* Histogram calculation
*/
/* Last 3 values unused. */
#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28
#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 81
/*
* Defect Pixel Cluster Correction
@ -723,7 +723,7 @@ struct cifisp_af_stat {
* with ISP_HIST_XXX
*/
struct cifisp_hist_stat {
unsigned short hist_bins[CIFISP_HIST_BIN_N_MAX];
unsigned int hist_bins[CIFISP_HIST_BIN_N_MAX];
} __attribute__ ((packed));
/**