From 2ff670508e8fdfefd67318e885effb8cee4a0f4c Mon Sep 17 00:00:00 2001 From: Hu Kejun Date: Sat, 14 Jul 2018 11:58:54 +0800 Subject: [PATCH] media: rockchip: isp1: support for isp new version in rk3326 Change-Id: I226cc2d87053d1951252122c44b570030470ba42 Signed-off-by: Hu Kejun --- drivers/media/platform/rockchip/isp1/Kconfig | 2 +- drivers/media/platform/rockchip/isp1/Makefile | 12 +- .../media/platform/rockchip/isp1/isp_params.c | 714 ++++++++++++++---- .../media/platform/rockchip/isp1/isp_params.h | 59 ++ .../media/platform/rockchip/isp1/isp_stats.c | 122 ++- .../media/platform/rockchip/isp1/isp_stats.h | 21 + drivers/media/platform/rockchip/isp1/regs.h | 384 ++++++---- include/uapi/linux/rkisp1-config.h | 10 +- 8 files changed, 1006 insertions(+), 318 deletions(-) diff --git a/drivers/media/platform/rockchip/isp1/Kconfig b/drivers/media/platform/rockchip/isp1/Kconfig index 014ec160ada7..a2f654bc2fa8 100644 --- a/drivers/media/platform/rockchip/isp1/Kconfig +++ b/drivers/media/platform/rockchip/isp1/Kconfig @@ -12,7 +12,7 @@ config VIDEO_ROCKCHIP_ISP1 Support for ISP1 on the rockchip SoC. config VIDEO_ROCKCHIP_ISP_DPHY_SY - tristate "Rockchip Image Signal Processing v1 Unit driver" + tristate "Rockchip Image Signal Processing v1 Dphy driver" depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API depends on ARCH_ROCKCHIP || COMPILE_TEST default n diff --git a/drivers/media/platform/rockchip/isp1/Makefile b/drivers/media/platform/rockchip/isp1/Makefile index 5cd1b48c0de1..d698660ac500 100644 --- a/drivers/media/platform/rockchip/isp1/Makefile +++ b/drivers/media/platform/rockchip/isp1/Makefile @@ -2,9 +2,9 @@ obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += video_rkisp1.o obj-$(CONFIG_VIDEO_ROCKCHIP_ISP_DPHY_SY) += mipi_dphy_sy.o -video_rkisp1-objs += rkisp1.o \ - dev.o \ - regs.o \ - isp_stats.o \ - isp_params.o \ - capture.o +video_rkisp1-objs += rkisp1.o \ + dev.o \ + regs.o \ + isp_stats.o \ + isp_params.o \ + capture.o diff --git a/drivers/media/platform/rockchip/isp1/isp_params.c b/drivers/media/platform/rockchip/isp1/isp_params.c index 8529413388ee..8fa617a8192d 100644 --- a/drivers/media/platform/rockchip/isp1/isp_params.c +++ b/drivers/media/platform/rockchip/isp1/isp_params.c @@ -93,8 +93,8 @@ static inline void isp_param_clear_bits(struct rkisp1_isp_params_vdev } /* ISP BP interface function */ -static void dpcc_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_dpcc_config *arg) +static void isp_dpcc_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpcc_config *arg) { unsigned int i; u32 mode; @@ -132,8 +132,8 @@ static void dpcc_config(struct rkisp1_isp_params_vdev *params_vdev, } /* ISP black level subtraction interface function */ -static void bls_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_bls_config *arg) +static void isp_bls_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_bls_config *arg) { /* avoid to override the old enable value */ u32 new_control; @@ -224,8 +224,8 @@ static void bls_config(struct rkisp1_isp_params_vdev *params_vdev, /* ISP LS correction interface function */ static void -__lsc_correct_matrix_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_lsc_config *pconfig) +isp_lsc_matrix_config_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_lsc_config *pconfig) { int i, j; unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel; @@ -250,50 +250,50 @@ __lsc_correct_matrix_config(struct rkisp1_isp_params_vdev *params_vdev, * DWORDs (2nd value of last DWORD unused) */ for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) { - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->r_data_tbl[i + j], pconfig->r_data_tbl[i + j + 1]); rkisp1_iowrite32(params_vdev, data, CIF_ISP_LSC_R_TABLE_DATA); - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->gr_data_tbl[i + j], pconfig->gr_data_tbl[i + j + 1]); rkisp1_iowrite32(params_vdev, data, CIF_ISP_LSC_GR_TABLE_DATA); - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->gb_data_tbl[i + j], pconfig->gb_data_tbl[i + j + 1]); rkisp1_iowrite32(params_vdev, data, CIF_ISP_LSC_GB_TABLE_DATA); - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->b_data_tbl[i + j], pconfig->b_data_tbl[i + j + 1]); rkisp1_iowrite32(params_vdev, data, CIF_ISP_LSC_B_TABLE_DATA); } - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->r_data_tbl[i + j], 0); rkisp1_iowrite32(params_vdev, data, CIF_ISP_LSC_R_TABLE_DATA); - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->gr_data_tbl[i + j], 0); rkisp1_iowrite32(params_vdev, data, CIF_ISP_LSC_GR_TABLE_DATA); - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->gb_data_tbl[i + j], 0); rkisp1_iowrite32(params_vdev, data, CIF_ISP_LSC_GB_TABLE_DATA); - data = CIF_ISP_LSC_TABLE_DATA( + data = CIF_ISP_LSC_TABLE_DATA_V10( pconfig->b_data_tbl[i + j], 0); rkisp1_iowrite32(params_vdev, data, @@ -304,8 +304,89 @@ __lsc_correct_matrix_config(struct rkisp1_isp_params_vdev *params_vdev, rkisp1_iowrite32(params_vdev, isp_lsc_table_sel, CIF_ISP_LSC_TABLE_SEL); } -static void lsc_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_lsc_config *arg) +static void +isp_lsc_matrix_config_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_lsc_config *pconfig) +{ + int i, j; + unsigned int isp_lsc_status, sram_addr, isp_lsc_table_sel; + unsigned int data; + + isp_lsc_status = rkisp1_ioread32(params_vdev, CIF_ISP_LSC_STATUS); + + /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */ + sram_addr = (isp_lsc_status & CIF_ISP_LSC_ACTIVE_TABLE) ? + CIF_ISP_LSC_TABLE_ADDRESS_0 : + CIF_ISP_LSC_TABLE_ADDRESS_153; + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_R_TABLE_ADDR); + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_GR_TABLE_ADDR); + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_GB_TABLE_ADDR); + rkisp1_iowrite32(params_vdev, sram_addr, CIF_ISP_LSC_B_TABLE_ADDR); + + /* program data tables (table size is 9 * 17 = 153) */ + for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX; + i += CIF_ISP_LSC_SECTORS_MAX) { + /* + * 17 sectors with 2 values in one DWORD = 9 + * DWORDs (2nd value of last DWORD unused) + */ + for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) { + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->r_data_tbl[i + j], + pconfig->r_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_R_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->gr_data_tbl[i + j], + pconfig->gr_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GR_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->gb_data_tbl[i + j], + pconfig->gb_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GB_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->b_data_tbl[i + j], + pconfig->b_data_tbl[i + j + 1]); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_B_TABLE_DATA); + } + + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->r_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_R_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->gr_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GR_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->gb_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_GB_TABLE_DATA); + + data = CIF_ISP_LSC_TABLE_DATA_V12( + pconfig->b_data_tbl[i + j], + 0); + rkisp1_iowrite32(params_vdev, data, + CIF_ISP_LSC_B_TABLE_DATA); + } + isp_lsc_table_sel = (isp_lsc_status & CIF_ISP_LSC_ACTIVE_TABLE) ? + CIF_ISP_LSC_TABLE_0 : CIF_ISP_LSC_TABLE_1; + rkisp1_iowrite32(params_vdev, isp_lsc_table_sel, CIF_ISP_LSC_TABLE_SEL); +} + +static void isp_lsc_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_lsc_config *arg) { int i; u32 lsc_ctrl; @@ -315,7 +396,7 @@ static void lsc_config(struct rkisp1_isp_params_vdev *params_vdev, lsc_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_LSC_CTRL); isp_param_clear_bits(params_vdev, CIF_ISP_LSC_CTRL, CIF_ISP_LSC_CTRL_ENA); - __lsc_correct_matrix_config(params_vdev, arg); + params_vdev->ops->lsc_matrix_config(params_vdev, arg); for (i = 0; i < 4; i++) { /* program x size tables */ @@ -356,8 +437,8 @@ static void lsc_config(struct rkisp1_isp_params_vdev *params_vdev, } /* ISP Filtering function */ -static void flt_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_flt_config *arg) +static void isp_flt_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_flt_config *arg) { u32 filt_mode; @@ -372,12 +453,6 @@ static void flt_config(struct rkisp1_isp_params_vdev *params_vdev, rkisp1_iowrite32(params_vdev, arg->fac_sh1, CIF_ISP_FILT_FAC_SH1); rkisp1_iowrite32(params_vdev, arg->lum_weight, CIF_ISP_FILT_LUM_WEIGHT); - rkisp1_iowrite32(params_vdev, (arg->mode ? CIF_ISP_FLT_MODE_DNR : 0) | - CIF_ISP_FLT_CHROMA_V_MODE(arg->chr_v_mode) | - CIF_ISP_FLT_CHROMA_H_MODE(arg->chr_h_mode) | - CIF_ISP_FLT_GREEN_STAGE1(arg->grn_stage1), - CIF_ISP_FILT_MODE); - /* avoid to override the old enable value */ filt_mode = rkisp1_ioread32(params_vdev, CIF_ISP_FILT_MODE); filt_mode &= CIF_ISP_FLT_ENA; @@ -390,8 +465,8 @@ static void flt_config(struct rkisp1_isp_params_vdev *params_vdev, } /* ISP demosaic interface function */ -static int bdm_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_bdm_config *arg) +static void isp_bdm_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_bdm_config *arg) { u32 bdm_th; @@ -401,12 +476,11 @@ static int bdm_config(struct rkisp1_isp_params_vdev *params_vdev, bdm_th |= arg->demosaic_th & ~CIF_ISP_DEMOSAIC_BYPASS; /* set demosaic threshold */ rkisp1_iowrite32(params_vdev, bdm_th, CIF_ISP_DEMOSAIC); - return 0; } /* ISP GAMMA correction interface function */ -static void sdg_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_sdg_config *arg) +static void isp_sdg_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_sdg_config *arg) { int i; @@ -426,23 +500,42 @@ static void sdg_config(struct rkisp1_isp_params_vdev *params_vdev, } /* ISP GAMMA correction interface function */ -static void goc_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_goc_config *arg) +static void isp_goc_config_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_goc_config *arg) { int i; isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA); - rkisp1_iowrite32(params_vdev, arg->mode, CIF_ISP_GAMMA_OUT_MODE); + rkisp1_iowrite32(params_vdev, arg->mode, CIF_ISP_GAMMA_OUT_MODE_V10); - for (i = 0; i < CIFISP_GAMMA_OUT_MAX_SAMPLES; i++) + for (i = 0; i < params_vdev->config->gamma_out_max_samples; i++) rkisp1_iowrite32(params_vdev, arg->gamma_y[i], - CIF_ISP_GAMMA_OUT_Y_0 + i * 4); + CIF_ISP_GAMMA_OUT_Y_0_V10 + i * 4); +} + +static void isp_goc_config_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_goc_config *arg) +{ + int i; + u32 value; + + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA); + rkisp1_iowrite32(params_vdev, arg->mode, CIF_ISP_GAMMA_OUT_MODE_V12); + + for (i = 0; i < params_vdev->config->gamma_out_max_samples / 2; i++) { + value = CIF_ISP_GAMMA_REG_VALUE_V12( + arg->gamma_y[2 * i + 1], + arg->gamma_y[2 * i]); + rkisp1_iowrite32(params_vdev, value, + CIF_ISP_GAMMA_OUT_Y_0_V12 + i * 4); + } } /* ISP Cross Talk */ -static void ctk_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_ctk_config *arg) +static void isp_ctk_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_ctk_config *arg) { rkisp1_iowrite32(params_vdev, arg->coeff0, CIF_ISP_CT_COEFF_0); rkisp1_iowrite32(params_vdev, arg->coeff1, CIF_ISP_CT_COEFF_1); @@ -458,7 +551,7 @@ static void ctk_config(struct rkisp1_isp_params_vdev *params_vdev, rkisp1_iowrite32(params_vdev, arg->ct_offset_b, CIF_ISP_CT_OFFSET_B); } -static void ctk_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) +static void isp_ctk_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) { if (en) return; @@ -480,8 +573,8 @@ static void ctk_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) } /* ISP White Balance Mode */ -static void awb_meas_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_awb_meas_config *arg) +static void isp_awb_meas_config_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg) { u32 reg_val = 0; /* based on the mode,configure the awb module */ @@ -489,41 +582,80 @@ static void awb_meas_config(struct rkisp1_isp_params_vdev *params_vdev, /* Reference Cb and Cr */ rkisp1_iowrite32(params_vdev, CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) | - arg->awb_ref_cb, CIF_ISP_AWB_REF); + arg->awb_ref_cb, CIF_ISP_AWB_REF_V10); /* Yc Threshold */ rkisp1_iowrite32(params_vdev, CIF_ISP_AWB_MAX_Y_SET(arg->max_y) | CIF_ISP_AWB_MIN_Y_SET(arg->min_y) | CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) | - arg->min_c, CIF_ISP_AWB_THRESH); + arg->min_c, CIF_ISP_AWB_THRESH_V10); } - reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP); + reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP_V10); if (arg->enable_ymax_cmp) reg_val |= CIF_ISP_AWB_YMAX_CMP_EN; else reg_val &= ~CIF_ISP_AWB_YMAX_CMP_EN; - rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP); + rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP_V10); /* window offset */ rkisp1_iowrite32(params_vdev, - arg->awb_wnd.v_offs, CIF_ISP_AWB_WND_V_OFFS); + arg->awb_wnd.v_offs, CIF_ISP_AWB_WND_V_OFFS_V10); rkisp1_iowrite32(params_vdev, - arg->awb_wnd.h_offs, CIF_ISP_AWB_WND_H_OFFS); + arg->awb_wnd.h_offs, CIF_ISP_AWB_WND_H_OFFS_V10); /* AWB window size */ rkisp1_iowrite32(params_vdev, - arg->awb_wnd.v_size, CIF_ISP_AWB_WND_V_SIZE); + arg->awb_wnd.v_size, CIF_ISP_AWB_WND_V_SIZE_V10); rkisp1_iowrite32(params_vdev, - arg->awb_wnd.h_size, CIF_ISP_AWB_WND_H_SIZE); + arg->awb_wnd.h_size, CIF_ISP_AWB_WND_H_SIZE_V10); /* Number of frames */ rkisp1_iowrite32(params_vdev, - arg->frames, CIF_ISP_AWB_FRAMES); + arg->frames, CIF_ISP_AWB_FRAMES_V10); } -static void awb_meas_enable(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_awb_meas_config *arg, bool en) +static void isp_awb_meas_config_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg) { - u32 reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP); + u32 reg_val = 0; + /* based on the mode,configure the awb module */ + if (arg->awb_mode == CIFISP_AWB_MODE_YCBCR) { + /* Reference Cb and Cr */ + rkisp1_iowrite32(params_vdev, + CIF_ISP_AWB_REF_CR_SET(arg->awb_ref_cr) | + arg->awb_ref_cb, CIF_ISP_AWB_REF_V12); + /* Yc Threshold */ + rkisp1_iowrite32(params_vdev, + CIF_ISP_AWB_MAX_Y_SET(arg->max_y) | + CIF_ISP_AWB_MIN_Y_SET(arg->min_y) | + CIF_ISP_AWB_MAX_CS_SET(arg->max_csum) | + arg->min_c, CIF_ISP_AWB_THRESH_V12); + } + + reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP_V12); + if (arg->enable_ymax_cmp) + reg_val |= CIF_ISP_AWB_YMAX_CMP_EN; + else + reg_val &= ~CIF_ISP_AWB_YMAX_CMP_EN; + reg_val &= ~CIF_ISP_AWB_SET_FRAMES_MASK_V12; + reg_val |= CIF_ISP_AWB_SET_FRAMES_V12(arg->frames); + rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP_V12); + + /* window offset */ + rkisp1_iowrite32(params_vdev, + arg->awb_wnd.v_offs << 16 | + arg->awb_wnd.h_offs, + CIF_ISP_AWB_OFFS_V12); + /* AWB window size */ + rkisp1_iowrite32(params_vdev, + arg->awb_wnd.v_size << 16 | + arg->awb_wnd.h_size, + CIF_ISP_AWB_SIZE_V12); +} + +static void isp_awb_meas_enable_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg, bool en) +{ + u32 reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP_V10); /* switch off */ reg_val &= CIF_ISP_AWB_MODE_MASK_NONE; @@ -534,7 +666,7 @@ static void awb_meas_enable(struct rkisp1_isp_params_vdev *params_vdev, else reg_val |= CIF_ISP_AWB_MODE_YCBCR_EN; - rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP); + rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP_V10); /* Measurements require AWB block be active. */ /* TODO: need to enable here ? awb_gain_enable has done this */ @@ -542,25 +674,64 @@ static void awb_meas_enable(struct rkisp1_isp_params_vdev *params_vdev, CIF_ISP_CTRL_ISP_AWB_ENA); } else { rkisp1_iowrite32(params_vdev, - reg_val, CIF_ISP_AWB_PROP); + reg_val, CIF_ISP_AWB_PROP_V10); isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_AWB_ENA); } } -static void awb_gain_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_awb_gain_config *arg) +static void isp_awb_meas_enable_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg, bool en) +{ + u32 reg_val = rkisp1_ioread32(params_vdev, CIF_ISP_AWB_PROP_V12); + + /* switch off */ + reg_val &= CIF_ISP_AWB_MODE_MASK_NONE; + + if (en) { + if (arg->awb_mode == CIFISP_AWB_MODE_RGB) + reg_val |= CIF_ISP_AWB_MODE_RGB_EN; + else + reg_val |= CIF_ISP_AWB_MODE_YCBCR_EN; + + rkisp1_iowrite32(params_vdev, reg_val, CIF_ISP_AWB_PROP_V12); + + /* Measurements require AWB block be active. */ + /* TODO: need to enable here ? awb_gain_enable has done this */ + isp_param_set_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_AWB_ENA); + } else { + rkisp1_iowrite32(params_vdev, + reg_val, CIF_ISP_AWB_PROP_V12); + isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, + CIF_ISP_CTRL_ISP_AWB_ENA); + } +} + +static void isp_awb_gain_config_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_gain_config *arg) { rkisp1_iowrite32(params_vdev, CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) | - arg->gain_green_b, CIF_ISP_AWB_GAIN_G); + arg->gain_green_b, CIF_ISP_AWB_GAIN_G_V10); rkisp1_iowrite32(params_vdev, CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) | - arg->gain_blue, CIF_ISP_AWB_GAIN_RB); + arg->gain_blue, CIF_ISP_AWB_GAIN_RB_V10); } -static void aec_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_aec_config *arg) +static void isp_awb_gain_config_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_gain_config *arg) +{ + rkisp1_iowrite32(params_vdev, + CIF_ISP_AWB_GAIN_R_SET(arg->gain_green_r) | + arg->gain_green_b, CIF_ISP_AWB_GAIN_G_V12); + + rkisp1_iowrite32(params_vdev, CIF_ISP_AWB_GAIN_R_SET(arg->gain_red) | + arg->gain_blue, CIF_ISP_AWB_GAIN_RB_V12); +} + +static void isp_aec_config_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_aec_config *arg) { unsigned int block_hsize, block_vsize; u32 exp_ctrl; @@ -575,21 +746,55 @@ static void aec_config(struct rkisp1_isp_params_vdev *params_vdev, rkisp1_iowrite32(params_vdev, exp_ctrl, CIF_ISP_EXP_CTRL); rkisp1_iowrite32(params_vdev, - arg->meas_window.h_offs, CIF_ISP_EXP_H_OFFSET); + arg->meas_window.h_offs, CIF_ISP_EXP_H_OFFSET_V10); rkisp1_iowrite32(params_vdev, - arg->meas_window.v_offs, CIF_ISP_EXP_V_OFFSET); + arg->meas_window.v_offs, CIF_ISP_EXP_V_OFFSET_V10); - block_hsize = arg->meas_window.h_size / CIF_ISP_EXP_COLUMN_NUM - 1; - block_vsize = arg->meas_window.v_size / CIF_ISP_EXP_ROW_NUM - 1; + block_hsize = arg->meas_window.h_size / CIF_ISP_EXP_COLUMN_NUM_V10 - 1; + block_vsize = arg->meas_window.v_size / CIF_ISP_EXP_ROW_NUM_V10 - 1; - rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_H_SIZE_SET(block_hsize), - CIF_ISP_EXP_H_SIZE); - rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_V_SIZE_SET(block_vsize), - CIF_ISP_EXP_V_SIZE); + rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_H_SIZE_SET_V10(block_hsize), + CIF_ISP_EXP_H_SIZE_V10); + rkisp1_iowrite32(params_vdev, CIF_ISP_EXP_V_SIZE_SET_V10(block_vsize), + CIF_ISP_EXP_V_SIZE_V10); } -static void cproc_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_cproc_config *arg) +static void isp_aec_config_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_aec_config *arg) +{ + u32 exp_ctrl; + u32 block_hsize, block_vsize; + u32 wnd_num_idx = 1; + const u32 ae_wnd_num[] = { + 5, 9, 15, 15 + }; + + /* avoid to override the old enable value */ + exp_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_EXP_CTRL); + exp_ctrl &= CIF_ISP_EXP_ENA; + if (arg->autostop) + exp_ctrl |= CIF_ISP_EXP_CTRL_AUTOSTOP; + if (arg->mode == CIFISP_EXP_MEASURING_MODE_1) + exp_ctrl |= CIF_ISP_EXP_CTRL_MEASMODE_1; + exp_ctrl |= CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(wnd_num_idx); + rkisp1_iowrite32(params_vdev, exp_ctrl, CIF_ISP_EXP_CTRL); + + rkisp1_iowrite32(params_vdev, + CIF_ISP_EXP_V_OFFSET_SET_V12(arg->meas_window.v_offs) | + CIF_ISP_EXP_H_OFFSET_SET_V12(arg->meas_window.h_offs), + CIF_ISP_EXP_OFFS_V12); + + block_hsize = arg->meas_window.h_size / ae_wnd_num[wnd_num_idx] - 1; + block_vsize = arg->meas_window.v_size / ae_wnd_num[wnd_num_idx] - 1; + + rkisp1_iowrite32(params_vdev, + CIF_ISP_EXP_V_SIZE_SET_V12(block_vsize) | + CIF_ISP_EXP_H_SIZE_SET_V12(block_hsize), + CIF_ISP_EXP_SIZE_V12); +} + +static void isp_cproc_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_cproc_config *arg) { struct cifisp_isp_other_cfg *cur_other_cfg = ¶ms_vdev->cur_params.others; struct cifisp_ie_config *cur_ie_config = &cur_other_cfg->ie_config; @@ -615,62 +820,142 @@ static void cproc_config(struct rkisp1_isp_params_vdev *params_vdev, } } -static void hst_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_hst_config *arg) +static void isp_hst_config_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg) { unsigned int block_hsize, block_vsize; - static const u32 hist_weight_regs[] = { - CIF_ISP_HIST_WEIGHT_00TO30, CIF_ISP_HIST_WEIGHT_40TO21, - CIF_ISP_HIST_WEIGHT_31TO12, CIF_ISP_HIST_WEIGHT_22TO03, - CIF_ISP_HIST_WEIGHT_13TO43, CIF_ISP_HIST_WEIGHT_04TO34, - CIF_ISP_HIST_WEIGHT_44, + const u32 hist_weight_regs[] = { + CIF_ISP_HIST_WEIGHT_00TO30_V10, CIF_ISP_HIST_WEIGHT_40TO21_V10, + CIF_ISP_HIST_WEIGHT_31TO12_V10, CIF_ISP_HIST_WEIGHT_22TO03_V10, + CIF_ISP_HIST_WEIGHT_13TO43_V10, CIF_ISP_HIST_WEIGHT_04TO34_V10, + CIF_ISP_HIST_WEIGHT_44_V10, }; int i; const u8 *weight; u32 hist_prop; /* avoid to override the old enable value */ - hist_prop = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_PROP); - hist_prop &= CIF_ISP_HIST_PROP_MODE_MASK; - hist_prop |= CIF_ISP_HIST_PREDIV_SET(arg->histogram_predivider); - rkisp1_iowrite32(params_vdev, hist_prop, CIF_ISP_HIST_PROP); + hist_prop = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_PROP_V10); + hist_prop &= CIF_ISP_HIST_PROP_MODE_MASK_V10; + hist_prop |= CIF_ISP_HIST_PREDIV_SET_V10(arg->histogram_predivider); + rkisp1_iowrite32(params_vdev, hist_prop, CIF_ISP_HIST_PROP_V10); rkisp1_iowrite32(params_vdev, arg->meas_window.h_offs, - CIF_ISP_HIST_H_OFFS); + CIF_ISP_HIST_H_OFFS_V10); rkisp1_iowrite32(params_vdev, arg->meas_window.v_offs, - CIF_ISP_HIST_V_OFFS); + CIF_ISP_HIST_V_OFFS_V10); - block_hsize = arg->meas_window.h_size / CIF_ISP_HIST_COLUMN_NUM - 1; - block_vsize = arg->meas_window.v_size / CIF_ISP_HIST_ROW_NUM - 1; + block_hsize = arg->meas_window.h_size / CIF_ISP_HIST_COLUMN_NUM_V10 - 1; + block_vsize = arg->meas_window.v_size / CIF_ISP_HIST_ROW_NUM_V10 - 1; - rkisp1_iowrite32(params_vdev, block_hsize, CIF_ISP_HIST_H_SIZE); - rkisp1_iowrite32(params_vdev, block_vsize, CIF_ISP_HIST_V_SIZE); + rkisp1_iowrite32(params_vdev, block_hsize, CIF_ISP_HIST_H_SIZE_V10); + rkisp1_iowrite32(params_vdev, block_vsize, CIF_ISP_HIST_V_SIZE_V10); weight = arg->hist_weight; for (i = 0; i < ARRAY_SIZE(hist_weight_regs); ++i, weight += 4) - rkisp1_iowrite32(params_vdev, CIF_ISP_HIST_WEIGHT_SET( + rkisp1_iowrite32(params_vdev, CIF_ISP_HIST_WEIGHT_SET_V10( weight[0], weight[1], weight[2], weight[3]), hist_weight_regs[i]); } -static void hst_enable(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_hst_config *arg, bool en) +static void isp_hst_config_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg) { - if (en) { - u32 hist_prop = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_PROP); + u32 i, j; + u32 value; + u32 hist_ctrl; + u32 block_hsize, block_vsize; + u32 wnd_num_idx, hist_weight_num; + u8 weight15x15[CIF_ISP_HIST_WEIGHT_REG_SIZE_V12]; + const u32 hist_wnd_num[] = { + 5, 9, 15, 15 + }; - hist_prop &= ~CIF_ISP_HIST_PROP_MODE_MASK; + /* now we just support 9x9 window */ + wnd_num_idx = 1; + memset(weight15x15, 0x00, sizeof(weight15x15)); + /* avoid to override the old enable value */ + hist_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_CTRL_V12); + hist_ctrl &= CIF_ISP_HIST_CTRL_MODE_MASK_V12 | + CIF_ISP_HIST_CTRL_EN_MASK_V12; + hist_ctrl = hist_ctrl | + CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(1) | + CIF_ISP_HIST_CTRL_DATASEL_SET_V12(0) | + CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(0) | + CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(0) | + CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(1) | + CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(arg->histogram_predivider); + rkisp1_iowrite32(params_vdev, hist_ctrl, CIF_ISP_HIST_CTRL_V12); + + rkisp1_iowrite32(params_vdev, + CIF_ISP_HIST_OFFS_SET_V12(arg->meas_window.h_offs, + arg->meas_window.v_offs), + CIF_ISP_HIST_OFFS_V12); + + block_hsize = arg->meas_window.h_size / hist_wnd_num[wnd_num_idx] - 1; + block_vsize = arg->meas_window.v_size / hist_wnd_num[wnd_num_idx] - 1; + rkisp1_iowrite32(params_vdev, + CIF_ISP_HIST_SIZE_SET_V12(block_hsize, block_vsize), + CIF_ISP_HIST_SIZE_V12); + + for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) { + for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) { + weight15x15[i * CIF_ISP_HIST_ROW_NUM_V12 + j] = + arg->hist_weight[i * hist_wnd_num[wnd_num_idx] + j]; + } + } + + hist_weight_num = CIF_ISP_HIST_WEIGHT_REG_SIZE_V12; + for (i = 0; i < (hist_weight_num / 4); i++) { + value = CIF_ISP_HIST_WEIGHT_SET_V12( + weight15x15[4 * i + 0], + weight15x15[4 * i + 1], + weight15x15[4 * i + 2], + weight15x15[4 * i + 3]); + rkisp1_iowrite32(params_vdev, value, + CIF_ISP_HIST_WEIGHT_V12 + 4 * i); + } + value = CIF_ISP_HIST_WEIGHT_SET_V12( + weight15x15[4 * i + 0], 0, 0, 0); + rkisp1_iowrite32(params_vdev, value, + CIF_ISP_HIST_WEIGHT_V12 + 4 * i); +} + +static void isp_hst_enable_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg, bool en) +{ + if (en) { + u32 hist_prop = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_PROP_V10); + + hist_prop &= ~CIF_ISP_HIST_PROP_MODE_MASK_V10; hist_prop |= arg->mode; - isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP, hist_prop); + isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP_V10, hist_prop); } else { - isp_param_clear_bits(params_vdev, CIF_ISP_HIST_PROP, - CIF_ISP_HIST_PROP_MODE_MASK); + isp_param_clear_bits(params_vdev, CIF_ISP_HIST_PROP_V10, + CIF_ISP_HIST_PROP_MODE_MASK_V10); } } -static void afm_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_afc_config *arg) +static void isp_hst_enable_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg, bool en) +{ + if (en) { + u32 hist_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_HIST_CTRL_V12); + + hist_ctrl &= ~CIF_ISP_HIST_CTRL_MODE_MASK_V12; + hist_ctrl |= CIF_ISP_HIST_CTRL_MODE_SET_V12(arg->mode); + hist_ctrl |= CIF_ISP_HIST_CTRL_EN_SET_V12(1); + isp_param_set_bits(params_vdev, CIF_ISP_HIST_CTRL_V12, hist_ctrl); + } else { + isp_param_clear_bits(params_vdev, CIF_ISP_HIST_CTRL_V12, + CIF_ISP_HIST_CTRL_MODE_MASK_V12 | + CIF_ISP_HIST_CTRL_EN_MASK_V12); + } +} + +static void isp_afm_config_v10(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_afc_config *arg) { int i; size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win), @@ -698,8 +983,46 @@ static void afm_config(struct rkisp1_isp_params_vdev *params_vdev, rkisp1_iowrite32(params_vdev, afm_ctrl, CIF_ISP_AFM_CTRL); } -static void ie_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_ie_config *arg) +static void isp_afm_config_v12(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_afc_config *arg) +{ + unsigned int i; + u32 lum_var_shift, afm_var_shift; + size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->afm_win), + arg->num_afm_win); + u32 afm_ctrl = rkisp1_ioread32(params_vdev, CIF_ISP_AFM_CTRL); + + /* Switch off to configure. */ + isp_param_clear_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA); + + for (i = 0; i < num_of_win; i++) { + rkisp1_iowrite32(params_vdev, + CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_offs) | + CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_offs), + CIF_ISP_AFM_LT_A + i * 8); + rkisp1_iowrite32(params_vdev, + CIF_ISP_AFM_WINDOW_X(arg->afm_win[i].h_size + + arg->afm_win[i].h_offs) | + CIF_ISP_AFM_WINDOW_Y(arg->afm_win[i].v_size + + arg->afm_win[i].v_offs), + CIF_ISP_AFM_RB_A + i * 8); + } + rkisp1_iowrite32(params_vdev, arg->thres, CIF_ISP_AFM_THRES); + + lum_var_shift = CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(arg->var_shift); + afm_var_shift = CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(arg->var_shift); + rkisp1_iowrite32(params_vdev, + CIF_ISP_AFM_SET_SHIFT_a_V12(lum_var_shift, afm_var_shift) | + CIF_ISP_AFM_SET_SHIFT_b_V12(lum_var_shift, afm_var_shift) | + CIF_ISP_AFM_SET_SHIFT_c_V12(lum_var_shift, afm_var_shift), + CIF_ISP_AFM_VAR_SHIFT); + + /* restore afm status */ + rkisp1_iowrite32(params_vdev, afm_ctrl, CIF_ISP_AFM_CTRL); +} + +static void isp_ie_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_ie_config *arg) { u32 eff_ctrl; @@ -757,7 +1080,7 @@ static void ie_config(struct rkisp1_isp_params_vdev *params_vdev, rkisp1_iowrite32(params_vdev, eff_ctrl, CIF_IMG_EFF_CTRL); } -static void ie_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) +static void isp_ie_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) { if (en) { isp_param_set_bits(params_vdev, CIF_ICCL, CIF_ICCL_IE_CLK); @@ -772,20 +1095,20 @@ static void ie_enable(struct rkisp1_isp_params_vdev *params_vdev, bool en) } } -static void csm_config(struct rkisp1_isp_params_vdev *params_vdev, - bool full_range) +static void isp_csm_config(struct rkisp1_isp_params_vdev *params_vdev, + bool full_range) { - static const u16 full_range_coeff[] = { + const u16 full_range_coeff[] = { 0x0026, 0x004b, 0x000f, 0x01ea, 0x01d6, 0x0040, 0x0040, 0x01ca, 0x01f6 }; - static const u16 limited_range_coeff[] = { + const u16 limited_range_coeff[] = { 0x0021, 0x0040, 0x000d, 0x01ed, 0x01db, 0x0038, 0x0038, 0x01d1, 0x01f7, }; - int i; + unsigned int i; if (full_range) { for (i = 0; i < ARRAY_SIZE(full_range_coeff); i++) @@ -807,8 +1130,8 @@ static void csm_config(struct rkisp1_isp_params_vdev *params_vdev, } /* ISP De-noise Pre-Filter(DPF) function */ -static void dpf_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_dpf_config *arg) +static void isp_dpf_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpf_config *arg) { unsigned int isp_dpf_mode; unsigned int spatial_coeff; @@ -893,19 +1216,82 @@ static void dpf_config(struct rkisp1_isp_params_vdev *params_vdev, CIF_ISP_DPF_S_WEIGHT_RB_5_6); } -static void dpf_strength_config(struct rkisp1_isp_params_vdev *params_vdev, - const struct cifisp_dpf_strength_config *arg) +static void isp_dpf_strength_config(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpf_strength_config *arg) { rkisp1_iowrite32(params_vdev, arg->b, CIF_ISP_DPF_STRENGTH_B); rkisp1_iowrite32(params_vdev, arg->g, CIF_ISP_DPF_STRENGTH_G); rkisp1_iowrite32(params_vdev, arg->r, CIF_ISP_DPF_STRENGTH_R); } +static struct rkisp1_isp_params_ops rkisp1_v10_isp_params_ops = { + .dpcc_config = isp_dpcc_config, + .bls_config = isp_bls_config, + .lsc_config = isp_lsc_config, + .lsc_matrix_config = isp_lsc_matrix_config_v10, + .flt_config = isp_flt_config, + .bdm_config = isp_bdm_config, + .sdg_config = isp_sdg_config, + .goc_config = isp_goc_config_v10, + .ctk_config = isp_ctk_config, + .ctk_enable = isp_ctk_enable, + .awb_meas_config = isp_awb_meas_config_v10, + .awb_meas_enable = isp_awb_meas_enable_v10, + .awb_gain_config = isp_awb_gain_config_v10, + .aec_config = isp_aec_config_v10, + .cproc_config = isp_cproc_config, + .hst_config = isp_hst_config_v10, + .hst_enable = isp_hst_enable_v10, + .afm_config = isp_afm_config_v10, + .ie_config = isp_ie_config, + .ie_enable = isp_ie_enable, + .csm_config = isp_csm_config, + .dpf_config = isp_dpf_config, + .dpf_strength_config = isp_dpf_strength_config, +}; + +static struct rkisp1_isp_params_ops rkisp1_v12_isp_params_ops = { + .dpcc_config = isp_dpcc_config, + .bls_config = isp_bls_config, + .lsc_config = isp_lsc_config, + .lsc_matrix_config = isp_lsc_matrix_config_v12, + .flt_config = isp_flt_config, + .bdm_config = isp_bdm_config, + .sdg_config = isp_sdg_config, + .goc_config = isp_goc_config_v12, + .ctk_config = isp_ctk_config, + .ctk_enable = isp_ctk_enable, + .awb_meas_config = isp_awb_meas_config_v12, + .awb_meas_enable = isp_awb_meas_enable_v12, + .awb_gain_config = isp_awb_gain_config_v12, + .aec_config = isp_aec_config_v12, + .cproc_config = isp_cproc_config, + .hst_config = isp_hst_config_v12, + .hst_enable = isp_hst_enable_v12, + .afm_config = isp_afm_config_v12, + .ie_config = isp_ie_config, + .ie_enable = isp_ie_enable, + .csm_config = isp_csm_config, + .dpf_config = isp_dpf_config, + .dpf_strength_config = isp_dpf_strength_config, +}; + +static struct rkisp1_isp_params_config rkisp1_v10_isp_params_config = { + .gamma_out_max_samples = 17, + .hst_weight_grids_size = 28, +}; + +static struct rkisp1_isp_params_config rkisp1_v12_isp_params_config = { + .gamma_out_max_samples = 34, + .hst_weight_grids_size = 81, +}; + static __maybe_unused void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, const struct rkisp1_isp_params_cfg *new_params) { unsigned int module_en_update, module_cfg_update, module_ens; + struct rkisp1_isp_params_ops *ops = params_vdev->ops; module_en_update = new_params->module_en_update; module_cfg_update = new_params->module_cfg_update; @@ -915,8 +1301,8 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_DPCC)) { /*update dpc config */ if ((module_cfg_update & CIFISP_MODULE_DPCC)) - dpcc_config(params_vdev, - &new_params->others.dpcc_config); + ops->dpcc_config(params_vdev, + &new_params->others.dpcc_config); if (module_en_update & CIFISP_MODULE_DPCC) { if (!!(module_ens & CIFISP_MODULE_DPCC)) @@ -934,7 +1320,7 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_BLS)) { /* update bls config */ if ((module_cfg_update & CIFISP_MODULE_BLS)) - bls_config(params_vdev, &new_params->others.bls_config); + ops->bls_config(params_vdev, &new_params->others.bls_config); if (module_en_update & CIFISP_MODULE_BLS) { if (!!(module_ens & CIFISP_MODULE_BLS)) @@ -952,7 +1338,7 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_SDG)) { /* update sdg config */ if ((module_cfg_update & CIFISP_MODULE_SDG)) - sdg_config(params_vdev, &new_params->others.sdg_config); + ops->sdg_config(params_vdev, &new_params->others.sdg_config); if (module_en_update & CIFISP_MODULE_SDG) { if (!!(module_ens & CIFISP_MODULE_SDG)) @@ -970,7 +1356,7 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_LSC)) { /* update lsc config */ if ((module_cfg_update & CIFISP_MODULE_LSC)) - lsc_config(params_vdev, &new_params->others.lsc_config); + ops->lsc_config(params_vdev, &new_params->others.lsc_config); if (module_en_update & CIFISP_MODULE_LSC) { if (!!(module_ens & CIFISP_MODULE_LSC)) @@ -988,8 +1374,8 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_AWB_GAIN)) { /* update awb gains */ if ((module_cfg_update & CIFISP_MODULE_AWB_GAIN)) - awb_gain_config(params_vdev, - &new_params->others.awb_gain_config); + ops->awb_gain_config(params_vdev, + &new_params->others.awb_gain_config); if (module_en_update & CIFISP_MODULE_AWB_GAIN) { if (!!(module_ens & CIFISP_MODULE_AWB_GAIN)) @@ -1007,7 +1393,7 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_BDM)) { /* update bdm config */ if ((module_cfg_update & CIFISP_MODULE_BDM)) - bdm_config(params_vdev, &new_params->others.bdm_config); + ops->bdm_config(params_vdev, &new_params->others.bdm_config); if (module_en_update & CIFISP_MODULE_BDM) { if (!!(module_ens & CIFISP_MODULE_BDM)) @@ -1025,7 +1411,7 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_FLT)) { /* update filter config */ if ((module_cfg_update & CIFISP_MODULE_FLT)) - flt_config(params_vdev, &new_params->others.flt_config); + ops->flt_config(params_vdev, &new_params->others.flt_config); if (module_en_update & CIFISP_MODULE_FLT) { if (!!(module_ens & CIFISP_MODULE_FLT)) @@ -1043,18 +1429,18 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_CTK)) { /* update ctk config */ if ((module_cfg_update & CIFISP_MODULE_CTK)) - ctk_config(params_vdev, &new_params->others.ctk_config); + ops->ctk_config(params_vdev, &new_params->others.ctk_config); if (module_en_update & CIFISP_MODULE_CTK) - ctk_enable(params_vdev, - !!(module_ens & CIFISP_MODULE_CTK)); + ops->ctk_enable(params_vdev, + !!(module_ens & CIFISP_MODULE_CTK)); } if ((module_en_update & CIFISP_MODULE_GOC) || (module_cfg_update & CIFISP_MODULE_GOC)) { /* update goc config */ if ((module_cfg_update & CIFISP_MODULE_GOC)) - goc_config(params_vdev, &new_params->others.goc_config); + ops->goc_config(params_vdev, &new_params->others.goc_config); if (module_en_update & CIFISP_MODULE_GOC) { if (!!(module_ens & CIFISP_MODULE_GOC)) @@ -1072,8 +1458,8 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_CPROC)) { /* update cproc config */ if ((module_cfg_update & CIFISP_MODULE_CPROC)) { - cproc_config(params_vdev, - &new_params->others.cproc_config); + ops->cproc_config(params_vdev, + &new_params->others.cproc_config); } @@ -1094,18 +1480,18 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_IE)) { /* update ie config */ if ((module_cfg_update & CIFISP_MODULE_IE)) - ie_config(params_vdev, &new_params->others.ie_config); + ops->ie_config(params_vdev, &new_params->others.ie_config); if (module_en_update & CIFISP_MODULE_IE) - ie_enable(params_vdev, - !!(module_ens & CIFISP_MODULE_IE)); + ops->ie_enable(params_vdev, + !!(module_ens & CIFISP_MODULE_IE)); } if ((module_en_update & CIFISP_MODULE_DPF) || (module_cfg_update & CIFISP_MODULE_DPF)) { /* update dpf config */ if ((module_cfg_update & CIFISP_MODULE_DPF)) - dpf_config(params_vdev, &new_params->others.dpf_config); + ops->dpf_config(params_vdev, &new_params->others.dpf_config); if (module_en_update & CIFISP_MODULE_DPF) { if (!!(module_ens & CIFISP_MODULE_DPF)) @@ -1122,8 +1508,8 @@ void __isp_isr_other_config(struct rkisp1_isp_params_vdev *params_vdev, if ((module_en_update & CIFISP_MODULE_DPF_STRENGTH) || (module_cfg_update & CIFISP_MODULE_DPF_STRENGTH)) { /* update dpf strength config */ - dpf_strength_config(params_vdev, - &new_params->others.dpf_strength_config); + ops->dpf_strength_config(params_vdev, + &new_params->others.dpf_strength_config); } } @@ -1132,6 +1518,7 @@ void __isp_isr_meas_config(struct rkisp1_isp_params_vdev *params_vdev, struct rkisp1_isp_params_cfg *new_params) { unsigned int module_en_update, module_cfg_update, module_ens; + struct rkisp1_isp_params_ops *ops = params_vdev->ops; module_en_update = new_params->module_en_update; module_cfg_update = new_params->module_cfg_update; @@ -1141,20 +1528,20 @@ void __isp_isr_meas_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_AWB)) { /* update awb config */ if ((module_cfg_update & CIFISP_MODULE_AWB)) - awb_meas_config(params_vdev, - &new_params->meas.awb_meas_config); + ops->awb_meas_config(params_vdev, + &new_params->meas.awb_meas_config); if (module_en_update & CIFISP_MODULE_AWB) - awb_meas_enable(params_vdev, - &new_params->meas.awb_meas_config, - !!(module_ens & CIFISP_MODULE_AWB)); + ops->awb_meas_enable(params_vdev, + &new_params->meas.awb_meas_config, + !!(module_ens & CIFISP_MODULE_AWB)); } if ((module_en_update & CIFISP_MODULE_AFC) || (module_cfg_update & CIFISP_MODULE_AFC)) { /* update afc config */ if ((module_cfg_update & CIFISP_MODULE_AFC)) - afm_config(params_vdev, &new_params->meas.afc_config); + ops->afm_config(params_vdev, &new_params->meas.afc_config); if (module_en_update & CIFISP_MODULE_AFC) { if (!!(module_ens & CIFISP_MODULE_AFC)) @@ -1172,19 +1559,19 @@ void __isp_isr_meas_config(struct rkisp1_isp_params_vdev *params_vdev, (module_cfg_update & CIFISP_MODULE_HST)) { /* update hst config */ if ((module_cfg_update & CIFISP_MODULE_HST)) - hst_config(params_vdev, &new_params->meas.hst_config); + ops->hst_config(params_vdev, &new_params->meas.hst_config); if (module_en_update & CIFISP_MODULE_HST) - hst_enable(params_vdev, - &new_params->meas.hst_config, - !!(module_ens & CIFISP_MODULE_HST)); + ops->hst_enable(params_vdev, + &new_params->meas.hst_config, + !!(module_ens & CIFISP_MODULE_HST)); } if ((module_en_update & CIFISP_MODULE_AEC) || (module_cfg_update & CIFISP_MODULE_AEC)) { /* update aec config */ if ((module_cfg_update & CIFISP_MODULE_AEC)) - aec_config(params_vdev, &new_params->meas.aec_config); + ops->aec_config(params_vdev, &new_params->meas.aec_config); if (module_en_update & CIFISP_MODULE_AEC) { if (!!(module_ens & CIFISP_MODULE_AEC)) @@ -1285,30 +1672,37 @@ static const struct cifisp_afc_config afc_params_default_config = { static void rkisp1_params_config_parameter(struct rkisp1_isp_params_vdev *params_vdev) { + struct rkisp1_isp_params_ops *ops = params_vdev->ops; struct cifisp_hst_config hst = hst_params_default_config; spin_lock(¶ms_vdev->config_lock); - awb_meas_config(params_vdev, &awb_params_default_config); - awb_meas_enable(params_vdev, &awb_params_default_config, true); + ops->awb_meas_config(params_vdev, &awb_params_default_config); + ops->awb_meas_enable(params_vdev, &awb_params_default_config, true); - aec_config(params_vdev, &aec_params_default_config); + ops->aec_config(params_vdev, &aec_params_default_config); isp_param_set_bits(params_vdev, CIF_ISP_EXP_CTRL, CIF_ISP_EXP_ENA); - afm_config(params_vdev, &afc_params_default_config); + ops->afm_config(params_vdev, &afc_params_default_config); isp_param_set_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA); memset(hst.hist_weight, 0x01, sizeof(hst.hist_weight)); - hst_config(params_vdev, &hst); - isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP, - ~CIF_ISP_HIST_PROP_MODE_MASK | + ops->hst_config(params_vdev, &hst); + if (params_vdev->dev->isp_ver == ISP_V12) { + isp_param_set_bits(params_vdev, CIF_ISP_HIST_CTRL_V12, + ~CIF_ISP_HIST_CTRL_MODE_MASK_V12 | hst_params_default_config.mode); + } else { + isp_param_set_bits(params_vdev, CIF_ISP_HIST_PROP_V10, + ~CIF_ISP_HIST_PROP_MODE_MASK_V10 | + hst_params_default_config.mode); + } /* set the range */ if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE) - csm_config(params_vdev, true); + ops->csm_config(params_vdev, true); else - csm_config(params_vdev, false); + ops->csm_config(params_vdev, false); /* override the default things */ __isp_isr_other_config(params_vdev, ¶ms_vdev->cur_params); @@ -1330,6 +1724,8 @@ void rkisp1_params_configure_isp(struct rkisp1_isp_params_vdev *params_vdev, /* Not called when the camera active, thus not isr protection. */ void rkisp1_params_disable_isp(struct rkisp1_isp_params_vdev *params_vdev) { + struct rkisp1_isp_params_ops *ops = params_vdev->ops; + isp_param_clear_bits(params_vdev, CIF_ISP_DPCC_MODE, CIF_ISP_DPCC_ENA); isp_param_clear_bits(params_vdev, CIF_ISP_LSC_CTRL, CIF_ISP_LSC_CTRL_ENA); @@ -1341,16 +1737,16 @@ void rkisp1_params_disable_isp(struct rkisp1_isp_params_vdev *params_vdev) isp_param_clear_bits(params_vdev, CIF_ISP_DEMOSAIC, CIF_ISP_DEMOSAIC_BYPASS); isp_param_clear_bits(params_vdev, CIF_ISP_FILT_MODE, CIF_ISP_FLT_ENA); - awb_meas_enable(params_vdev, NULL, false); + ops->awb_meas_enable(params_vdev, NULL, false); isp_param_clear_bits(params_vdev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_AWB_ENA); isp_param_clear_bits(params_vdev, CIF_ISP_EXP_CTRL, CIF_ISP_EXP_ENA); - ctk_enable(params_vdev, false); + ops->ctk_enable(params_vdev, false); isp_param_clear_bits(params_vdev, CIF_C_PROC_CTRL, CIF_C_PROC_CTR_ENABLE); - hst_enable(params_vdev, NULL, false); + ops->hst_enable(params_vdev, NULL, false); isp_param_clear_bits(params_vdev, CIF_ISP_AFM_CTRL, CIF_ISP_AFM_ENA); - ie_enable(params_vdev, false); + ops->ie_enable(params_vdev, false); isp_param_clear_bits(params_vdev, CIF_ISP_DPF_MODE, CIF_ISP_DPF_MODE_EN); } @@ -1560,6 +1956,14 @@ static void rkisp1_init_params_vdev(struct rkisp1_isp_params_vdev *params_vdev) V4L2_META_FMT_RK_ISP1_PARAMS; params_vdev->vdev_fmt.fmt.meta.buffersize = sizeof(struct rkisp1_isp_params_cfg); + + if (params_vdev->dev->isp_ver == ISP_V12) { + params_vdev->ops = &rkisp1_v12_isp_params_ops; + params_vdev->config = &rkisp1_v12_isp_params_config; + } else { + params_vdev->ops = &rkisp1_v10_isp_params_ops; + params_vdev->config = &rkisp1_v10_isp_params_config; + } } int rkisp1_register_params_vdev(struct rkisp1_isp_params_vdev *params_vdev, diff --git a/drivers/media/platform/rockchip/isp1/isp_params.h b/drivers/media/platform/rockchip/isp1/isp_params.h index 9ecdcd21525a..efea6567bded 100644 --- a/drivers/media/platform/rockchip/isp1/isp_params.h +++ b/drivers/media/platform/rockchip/isp1/isp_params.h @@ -38,6 +38,62 @@ #include #include "common.h" +struct rkisp1_isp_params_vdev; +struct rkisp1_isp_params_ops { + void (*dpcc_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpcc_config *arg); + void (*bls_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_bls_config *arg); + void (*lsc_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_lsc_config *arg); + void (*lsc_matrix_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_lsc_config *pconfig); + void (*flt_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_flt_config *arg); + void (*bdm_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_bdm_config *arg); + void (*sdg_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_sdg_config *arg); + void (*goc_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_goc_config *arg); + void (*ctk_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_ctk_config *arg); + void (*ctk_enable)(struct rkisp1_isp_params_vdev *params_vdev, + bool en); + void (*awb_meas_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg); + void (*awb_meas_enable)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_meas_config *arg, + bool en); + void (*awb_gain_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_awb_gain_config *arg); + void (*aec_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_aec_config *arg); + void (*cproc_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_cproc_config *arg); + void (*hst_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg); + void (*hst_enable)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_hst_config *arg, bool en); + void (*afm_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_afc_config *arg); + void (*ie_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_ie_config *arg); + void (*ie_enable)(struct rkisp1_isp_params_vdev *params_vdev, + bool en); + void (*csm_config)(struct rkisp1_isp_params_vdev *params_vdev, + bool full_range); + void (*dpf_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpf_config *arg); + void (*dpf_strength_config)(struct rkisp1_isp_params_vdev *params_vdev, + const struct cifisp_dpf_strength_config *arg); +}; + +struct rkisp1_isp_params_config { + const int gamma_out_max_samples; + const int hst_weight_grids_size; +}; + /* * struct rkisp1_isp_subdev - ISP input parameters device * @@ -57,6 +113,9 @@ struct rkisp1_isp_params_vdev { enum v4l2_quantization quantization; enum rkisp1_fmt_raw_pat_type raw_type; + + struct rkisp1_isp_params_ops *ops; + struct rkisp1_isp_params_config *config; }; /* config params before ISP streaming */ diff --git a/drivers/media/platform/rockchip/isp1/isp_stats.c b/drivers/media/platform/rockchip/isp1/isp_stats.c index 23cdcb5e570b..5f8f46b98e3a 100644 --- a/drivers/media/platform/rockchip/isp1/isp_stats.c +++ b/drivers/media/platform/rockchip/isp1/isp_stats.c @@ -213,16 +213,16 @@ static int rkisp1_stats_init_vb2_queue(struct vb2_queue *q, return vb2_queue_init(q); } -static void rkisp1_stats_get_awb_meas(struct rkisp1_isp_stats_vdev *stats_vdev, - struct rkisp1_stat_buffer *pbuf) +static void rkisp1_stats_get_awb_meas_v10(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) { /* Protect against concurrent access from ISR? */ u32 reg_val; pbuf->meas_type |= CIFISP_STAT_AWB; - reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT); + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V10); pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val); - reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN); + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V10); pbuf->params.awb.awb_mean[0].mean_cr_or_r = CIF_ISP_AWB_GET_MEAN_CR_R(reg_val); @@ -232,17 +232,55 @@ static void rkisp1_stats_get_awb_meas(struct rkisp1_isp_stats_vdev *stats_vdev, CIF_ISP_AWB_GET_MEAN_Y_G(reg_val); } -static void rkisp1_stats_get_aec_meas(struct rkisp1_isp_stats_vdev *stats_vdev, - struct rkisp1_stat_buffer *pbuf) +static void rkisp1_stats_get_awb_meas_v12(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + /* Protect against concurrent access from ISR? */ + u32 reg_val; + + pbuf->meas_type |= CIFISP_STAT_AWB; + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_WHITE_CNT_V12); + pbuf->params.awb.awb_mean[0].cnt = CIF_ISP_AWB_GET_PIXEL_CNT(reg_val); + reg_val = readl(stats_vdev->dev->base_addr + CIF_ISP_AWB_MEAN_V12); + + pbuf->params.awb.awb_mean[0].mean_cr_or_r = + CIF_ISP_AWB_GET_MEAN_CR_R(reg_val); + pbuf->params.awb.awb_mean[0].mean_cb_or_b = + CIF_ISP_AWB_GET_MEAN_CB_B(reg_val); + pbuf->params.awb.awb_mean[0].mean_y_or_g = + CIF_ISP_AWB_GET_MEAN_Y_G(reg_val); +} + +static void rkisp1_stats_get_aec_meas_v10(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) { unsigned int i; - void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00; + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_00_V10; pbuf->meas_type |= CIFISP_STAT_AUTOEXP; - for (i = 0; i < CIFISP_AE_MEAN_MAX; i++) + for (i = 0; i < stats_vdev->config->ae_mean_max; i++) pbuf->params.ae.exp_mean[i] = (u8)readl(addr + i * 4); } +static void rkisp1_stats_get_aec_meas_v12(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + int i; + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_EXP_MEAN_V12; + u32 value; + + pbuf->meas_type |= CIFISP_STAT_AUTOEXP; + for (i = 0; i < stats_vdev->config->ae_mean_max / 4; i++) { + value = readl(addr + i * 4); + pbuf->params.ae.exp_mean[4 * i + 0] = CIF_ISP_EXP_GET_MEAN_xy0_V12(value); + pbuf->params.ae.exp_mean[4 * i + 1] = CIF_ISP_EXP_GET_MEAN_xy1_V12(value); + pbuf->params.ae.exp_mean[4 * i + 2] = CIF_ISP_EXP_GET_MEAN_xy2_V12(value); + pbuf->params.ae.exp_mean[4 * i + 3] = CIF_ISP_EXP_GET_MEAN_xy3_V12(value); + } + value = readl(addr + i * 4); + pbuf->params.ae.exp_mean[4 * i + 0] = CIF_ISP_EXP_GET_MEAN_xy0_V12(value); +} + static void rkisp1_stats_get_afc_meas(struct rkisp1_isp_stats_vdev *stats_vdev, struct rkisp1_stat_buffer *pbuf) { @@ -261,17 +299,32 @@ static void rkisp1_stats_get_afc_meas(struct rkisp1_isp_stats_vdev *stats_vdev, af->window[2].lum = readl(base_addr + CIF_ISP_AFM_LUM_C); } -static void rkisp1_stats_get_hst_meas(struct rkisp1_isp_stats_vdev *stats_vdev, - struct rkisp1_stat_buffer *pbuf) +static void rkisp1_stats_get_hst_meas_v10(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) { int i; - void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_0; + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_0_V10; pbuf->meas_type |= CIFISP_STAT_HIST; - for (i = 0; i < CIFISP_HIST_BIN_N_MAX; i++) + for (i = 0; i < stats_vdev->config->hist_bin_n_max; i++) pbuf->params.hist.hist_bins[i] = readl(addr + (i * 4)); } +static void rkisp1_stats_get_hst_meas_v12(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf) +{ + int i; + void __iomem *addr = stats_vdev->dev->base_addr + CIF_ISP_HIST_BIN_V12; + u32 value; + + pbuf->meas_type |= CIFISP_STAT_HIST; + for (i = 0; i < stats_vdev->config->hist_bin_n_max / 2; i++) { + value = readl(addr + (i * 4)); + pbuf->params.hist.hist_bins[2 * i] = CIF_ISP_HIST_GET_BIN0_V12(value); + pbuf->params.hist.hist_bins[2 * i + 1] = CIF_ISP_HIST_GET_BIN1_V12(value); + } +} + static void rkisp1_stats_get_bls_meas(struct rkisp1_isp_stats_vdev *stats_vdev, struct rkisp1_stat_buffer *pbuf) { @@ -305,6 +358,32 @@ static void rkisp1_stats_get_bls_meas(struct rkisp1_isp_stats_vdev *stats_vdev, } } +static struct rkisp1_stats_ops rkisp1_v10_stats_ops = { + .get_awb_meas = rkisp1_stats_get_awb_meas_v10, + .get_aec_meas = rkisp1_stats_get_aec_meas_v10, + .get_afc_meas = rkisp1_stats_get_afc_meas, + .get_hst_meas = rkisp1_stats_get_hst_meas_v10, + .get_bls_meas = rkisp1_stats_get_bls_meas, +}; + +static struct rkisp1_stats_ops rkisp1_v12_stats_ops = { + .get_awb_meas = rkisp1_stats_get_awb_meas_v12, + .get_aec_meas = rkisp1_stats_get_aec_meas_v12, + .get_afc_meas = rkisp1_stats_get_afc_meas, + .get_hst_meas = rkisp1_stats_get_hst_meas_v12, + .get_bls_meas = rkisp1_stats_get_bls_meas, +}; + +static struct rkisp1_stats_config rkisp1_v10_stats_config = { + .ae_mean_max = 25, + .hist_bin_n_max = 16, +}; + +static struct rkisp1_stats_config rkisp1_v12_stats_config = { + .ae_mean_max = 81, + .hist_bin_n_max = 32, +}; + static void rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev, struct rkisp1_isp_readout_work *meas_work) @@ -312,6 +391,7 @@ rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev, unsigned int cur_frame_id = -1; struct rkisp1_stat_buffer *cur_stat_buf; struct rkisp1_buffer *cur_buf = NULL; + struct rkisp1_stats_ops *ops = stats_vdev->ops; cur_frame_id = atomic_read(&stats_vdev->dev->isp_sdev.frm_sync_seq) - 1; if (cur_frame_id != meas_work->frame_id) { @@ -337,23 +417,23 @@ rkisp1_stats_send_measurement(struct rkisp1_isp_stats_vdev *stats_vdev, (struct rkisp1_stat_buffer *)(cur_buf->vaddr[0]); if (meas_work->isp_ris & CIF_ISP_AWB_DONE) { - rkisp1_stats_get_awb_meas(stats_vdev, cur_stat_buf); + ops->get_awb_meas(stats_vdev, cur_stat_buf); cur_stat_buf->meas_type |= CIFISP_STAT_AWB; } if (meas_work->isp_ris & CIF_ISP_AFM_FIN) { - rkisp1_stats_get_afc_meas(stats_vdev, cur_stat_buf); + ops->get_afc_meas(stats_vdev, cur_stat_buf); cur_stat_buf->meas_type |= CIFISP_STAT_AFM_FIN; } if (meas_work->isp_ris & CIF_ISP_EXP_END) { - rkisp1_stats_get_aec_meas(stats_vdev, cur_stat_buf); - rkisp1_stats_get_bls_meas(stats_vdev, cur_stat_buf); + ops->get_aec_meas(stats_vdev, cur_stat_buf); + ops->get_bls_meas(stats_vdev, cur_stat_buf); cur_stat_buf->meas_type |= CIFISP_STAT_AUTOEXP; } if (meas_work->isp_ris & CIF_ISP_HIST_MEASURE_RDY) { - rkisp1_stats_get_hst_meas(stats_vdev, cur_stat_buf); + ops->get_hst_meas(stats_vdev, cur_stat_buf); cur_stat_buf->meas_type |= CIFISP_STAT_HIST; } @@ -449,6 +529,14 @@ static void rkisp1_init_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev) V4L2_META_FMT_RK_ISP1_STAT_3A; stats_vdev->vdev_fmt.fmt.meta.buffersize = sizeof(struct rkisp1_stat_buffer); + + if (stats_vdev->dev->isp_ver == ISP_V12) { + stats_vdev->ops = &rkisp1_v12_stats_ops; + stats_vdev->config = &rkisp1_v12_stats_config; + } else { + stats_vdev->ops = &rkisp1_v10_stats_ops; + stats_vdev->config = &rkisp1_v10_stats_config; + } } int rkisp1_register_stats_vdev(struct rkisp1_isp_stats_vdev *stats_vdev, diff --git a/drivers/media/platform/rockchip/isp1/isp_stats.h b/drivers/media/platform/rockchip/isp1/isp_stats.h index c78d66fc4f45..54fec490a53e 100644 --- a/drivers/media/platform/rockchip/isp1/isp_stats.h +++ b/drivers/media/platform/rockchip/isp1/isp_stats.h @@ -55,6 +55,24 @@ struct rkisp1_isp_readout_work { struct vb2_buffer *vb; }; +struct rkisp1_stats_ops { + void (*get_awb_meas)(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf); + void (*get_aec_meas)(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf); + void (*get_afc_meas)(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf); + void (*get_hst_meas)(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf); + void (*get_bls_meas)(struct rkisp1_isp_stats_vdev *stats_vdev, + struct rkisp1_stat_buffer *pbuf); +}; + +struct rkisp1_stats_config { + const int ae_mean_max; + const int hist_bin_n_max; +}; + /* * struct rkisp1_isp_stats_vdev - ISP Statistics device * @@ -73,6 +91,9 @@ struct rkisp1_isp_stats_vdev { struct workqueue_struct *readout_wq; struct mutex wq_lock; + + struct rkisp1_stats_ops *ops; + struct rkisp1_stats_config *config; }; int rkisp1_stats_isr(struct rkisp1_isp_stats_vdev *stats_vdev, u32 isp_ris); diff --git a/drivers/media/platform/rockchip/isp1/regs.h b/drivers/media/platform/rockchip/isp1/regs.h index 53977bc7e879..a18a7b52e1bb 100644 --- a/drivers/media/platform/rockchip/isp1/regs.h +++ b/drivers/media/platform/rockchip/isp1/regs.h @@ -374,25 +374,57 @@ #define CIF_SUPER_IMP_CTRL_TRANSP_DIS BIT(2) /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */ -#define CIF_ISP_HIST_PROP_MODE_DIS (0 << 0) -#define CIF_ISP_HIST_PROP_MODE_RGB (1 << 0) -#define CIF_ISP_HIST_PROP_MODE_RED (2 << 0) -#define CIF_ISP_HIST_PROP_MODE_GREEN (3 << 0) -#define CIF_ISP_HIST_PROP_MODE_BLUE (4 << 0) -#define CIF_ISP_HIST_PROP_MODE_LUM (5 << 0) -#define CIF_ISP_HIST_PROP_MODE_MASK 0x7 -#define CIF_ISP_HIST_PREDIV_SET(x) (((x) & 0x7F) << 3) -#define CIF_ISP_HIST_WEIGHT_SET(v0, v1, v2, v3) \ +#define CIF_ISP_HIST_PROP_MODE_DIS_V10 (0 << 0) +#define CIF_ISP_HIST_PROP_MODE_RGB_V10 (1 << 0) +#define CIF_ISP_HIST_PROP_MODE_RED_V10 (2 << 0) +#define CIF_ISP_HIST_PROP_MODE_GREEN_V10 (3 << 0) +#define CIF_ISP_HIST_PROP_MODE_BLUE_V10 (4 << 0) +#define CIF_ISP_HIST_PROP_MODE_LUM_V10 (5 << 0) +#define CIF_ISP_HIST_PROP_MODE_MASK_V10 0x7 +#define CIF_ISP_HIST_PREDIV_SET_V10(x) (((x) & 0x7F) << 3) +#define CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3) \ (((v0) & 0x1F) | (((v1) & 0x1F) << 8) |\ (((v2) & 0x1F) << 16) | \ (((v3) & 0x1F) << 24)) -#define CIF_ISP_HIST_WINDOW_OFFSET_RESERVED 0xFFFFF000 -#define CIF_ISP_HIST_WINDOW_SIZE_RESERVED 0xFFFFF800 -#define CIF_ISP_HIST_WEIGHT_RESERVED 0xE0E0E0E0 -#define CIF_ISP_MAX_HIST_PREDIVIDER 0x0000007F -#define CIF_ISP_HIST_ROW_NUM 5 -#define CIF_ISP_HIST_COLUMN_NUM 5 +#define CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10 0xFFFFF000 +#define CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10 0xFFFFF800 +#define CIF_ISP_HIST_WEIGHT_RESERVED_V10 0xE0E0E0E0 +#define CIF_ISP_MAX_HIST_PREDIVIDER_V10 0x0000007F +#define CIF_ISP_HIST_ROW_NUM_V10 5 +#define CIF_ISP_HIST_COLUMN_NUM_V10 5 + +/* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */ +#define CIF_ISP_HIST_CTRL_EN_SET_V12(x) (((x) & 0x01) << 0) +#define CIF_ISP_HIST_CTRL_EN_MASK_V12 CIF_ISP_HIST_CTRL_EN_SET_V12(0x01) +#define CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x) (((x) & 0x7F) << 1) +#define CIF_ISP_HIST_CTRL_MODE_SET_V12(x) (((x) & 0x07) << 8) +#define CIF_ISP_HIST_CTRL_MODE_MASK_V12 CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07) +#define CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x) (((x) & 0x01) << 11) +#define CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x) (((x) & 0xFFF) << 12) +#define CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x) (((x) & 0x07) << 24) +#define CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x) (((x) & 0x01) << 27) +#define CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 28) +#define CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x) (((x) & 0x01) << 30) +#define CIF_ISP_HIST_ROW_NUM_V12 15 +#define CIF_ISP_HIST_COLUMN_NUM_V12 15 +#define CIF_ISP_HIST_WEIGHT_REG_SIZE_V12 \ + (CIF_ISP_HIST_ROW_NUM_V12 * CIF_ISP_HIST_COLUMN_NUM_V12) + +#define CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3) \ + (((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\ + (((v2) & 0x3F) << 16) |\ + (((v3) & 0x3F) << 24)) + +#define CIF_ISP_HIST_OFFS_SET_V12(v0, v1) \ + (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16)) +#define CIF_ISP_HIST_SIZE_SET_V12(v0, v1) \ + (((v0) & 0x7FF) | (((v1) & 0x7FF) << 16)) + +#define CIF_ISP_HIST_GET_BIN0_V12(x) \ + ((x) & 0xFFFF) +#define CIF_ISP_HIST_GET_BIN1_V12(x) \ + (((x) >> 16) & 0xFFFF) /* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */ #define ISP_AFM_CTRL_ENABLE BIT(0) @@ -423,17 +455,18 @@ /* AWB */ /* ISP_AWB_PROP */ #define CIF_ISP_AWB_YMAX_CMP_EN BIT(2) -#define CIFISP_AWB_YMAX_READ(x) (((x) >> 2) & 1) +#define CIF_ISP_AWB_YMAX_READ(x) (((x) >> 2) & 1) #define CIF_ISP_AWB_MODE_RGB_EN ((1 << 31) | (0x2 << 0)) #define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0)) -#define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0)) #define CIF_ISP_AWB_MODE_MASK_NONE 0xFFFFFFFC #define CIF_ISP_AWB_MODE_READ(x) ((x) & 3) +#define CIF_ISP_AWB_SET_FRAMES_V12(x) (((x) & 0x07) << 28) +#define CIF_ISP_AWB_SET_FRAMES_MASK_V12 CIF_ISP_AWB_SET_FRAMES_V12(0x07) /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G */ #define CIF_ISP_AWB_GAIN_R_SET(x) (((x) & 0x3FF) << 16) #define CIF_ISP_AWB_GAIN_R_READ(x) (((x) >> 16) & 0x3FF) -#define CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FFF) -#define CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FFF) +#define CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FF) +#define CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FF) /* ISP_AWB_REF */ #define CIF_ISP_AWB_REF_CR_SET(x) (((x) & 0xFF) << 8) #define CIF_ISP_AWB_REF_CR_READ(x) (((x) >> 8) & 0xFF) @@ -463,6 +496,7 @@ /* ISP_EXP_CTRL */ #define CIF_ISP_EXP_ENA BIT(0) #define CIF_ISP_EXP_CTRL_AUTOSTOP BIT(1) +#define CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 2) /* *'1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256) *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B @@ -470,43 +504,82 @@ #define CIF_ISP_EXP_CTRL_MEASMODE_1 BIT(31) /* ISP_EXP_H_SIZE */ -#define CIF_ISP_EXP_H_SIZE_SET(x) ((x) & 0x7FF) -#define CIF_ISP_EXP_HEIGHT_MASK 0x000007FF +#define CIF_ISP_EXP_H_SIZE_SET_V10(x) ((x) & 0x7FF) +#define CIF_ISP_EXP_HEIGHT_MASK_V10 0x000007FF /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */ -#define CIF_ISP_EXP_V_SIZE_SET(x) ((x) & 0x7FE) +#define CIF_ISP_EXP_V_SIZE_SET_V10(x) ((x) & 0x7FE) /* ISP_EXP_H_OFFSET */ -#define CIF_ISP_EXP_H_OFFSET_SET(x) ((x) & 0x1FFF) -#define CIF_ISP_EXP_MAX_HOFFS 2424 +#define CIF_ISP_EXP_H_OFFSET_SET_V10(x) ((x) & 0x1FFF) +#define CIF_ISP_EXP_MAX_HOFFS_V10 2424 /* ISP_EXP_V_OFFSET */ -#define CIF_ISP_EXP_V_OFFSET_SET(x) ((x) & 0x1FFF) -#define CIF_ISP_EXP_MAX_VOFFS 1806 +#define CIF_ISP_EXP_V_OFFSET_SET_V10(x) ((x) & 0x1FFF) +#define CIF_ISP_EXP_MAX_VOFFS_V10 1806 -#define CIF_ISP_EXP_ROW_NUM 5 -#define CIF_ISP_EXP_COLUMN_NUM 5 -#define CIF_ISP_EXP_NUM_LUMA_REGS \ - (CIF_ISP_EXP_ROW_NUM * CIF_ISP_EXP_COLUMN_NUM) -#define CIF_ISP_EXP_BLOCK_MAX_HSIZE 516 -#define CIF_ISP_EXP_BLOCK_MIN_HSIZE 35 -#define CIF_ISP_EXP_BLOCK_MAX_VSIZE 390 -#define CIF_ISP_EXP_BLOCK_MIN_VSIZE 28 -#define CIF_ISP_EXP_MAX_HSIZE \ - (CIF_ISP_EXP_BLOCK_MAX_HSIZE * CIF_ISP_EXP_COLUMN_NUM + 1) -#define CIF_ISP_EXP_MIN_HSIZE \ - (CIF_ISP_EXP_BLOCK_MIN_HSIZE * CIF_ISP_EXP_COLUMN_NUM + 1) -#define CIF_ISP_EXP_MAX_VSIZE \ - (CIF_ISP_EXP_BLOCK_MAX_VSIZE * CIF_ISP_EXP_ROW_NUM + 1) -#define CIF_ISP_EXP_MIN_VSIZE \ - (CIF_ISP_EXP_BLOCK_MIN_VSIZE * CIF_ISP_EXP_ROW_NUM + 1) +#define CIF_ISP_EXP_ROW_NUM_V10 5 +#define CIF_ISP_EXP_COLUMN_NUM_V10 5 +#define CIF_ISP_EXP_NUM_LUMA_REGS_V10 \ + (CIF_ISP_EXP_ROW_NUM_V10 * CIF_ISP_EXP_COLUMN_NUM_V10) +#define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 516 +#define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 35 +#define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 390 +#define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 28 +#define CIF_ISP_EXP_MAX_HSIZE_V10 \ + (CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1) +#define CIF_ISP_EXP_MIN_HSIZE_V10 \ + (CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1) +#define CIF_ISP_EXP_MAX_VSIZE_V10 \ + (CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1) +#define CIF_ISP_EXP_MIN_VSIZE_V10 \ + (CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1) + +/* ISP_EXP_H_SIZE */ +#define CIF_ISP_EXP_H_SIZE_SET_V12(x) ((x) & 0x7FF) +#define CIF_ISP_EXP_HEIGHT_MASK_V12 0x000007FF +/* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */ +#define CIF_ISP_EXP_V_SIZE_SET_V12(x) (((x) & 0x7FE) << 16) + +/* ISP_EXP_H_OFFSET */ +#define CIF_ISP_EXP_H_OFFSET_SET_V12(x) ((x) & 0x1FFF) +#define CIF_ISP_EXP_MAX_HOFFS_V12 0x1FFF +/* ISP_EXP_V_OFFSET */ +#define CIF_ISP_EXP_V_OFFSET_SET_V12(x) (((x) & 0x1FFF) << 16) +#define CIF_ISP_EXP_MAX_VOFFS_V12 0x1FFF + +#define CIF_ISP_EXP_ROW_NUM_V12 15 +#define CIF_ISP_EXP_COLUMN_NUM_V12 15 +#define CIF_ISP_EXP_NUM_LUMA_REGS_V12 \ + (CIF_ISP_EXP_ROW_NUM_V12 * CIF_ISP_EXP_COLUMN_NUM_V12) +#define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 0x7FF +#define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 0xE +#define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 0x7FE +#define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 0xE +#define CIF_ISP_EXP_MAX_HSIZE_V12 \ + (CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1) +#define CIF_ISP_EXP_MIN_HSIZE_V12 \ + (CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1) +#define CIF_ISP_EXP_MAX_VSIZE_V12 \ + (CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1) +#define CIF_ISP_EXP_MIN_VSIZE_V12 \ + (CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1) + +#define CIF_ISP_EXP_GET_MEAN_xy0_V12(x) ((x) & 0xFF) +#define CIF_ISP_EXP_GET_MEAN_xy1_V12(x) (((x) >> 8) & 0xFF) +#define CIF_ISP_EXP_GET_MEAN_xy2_V12(x) (((x) >> 16) & 0xFF) +#define CIF_ISP_EXP_GET_MEAN_xy3_V12(x) (((x) >> 24) & 0xFF) /* LSC: ISP_LSC_CTRL */ #define CIF_ISP_LSC_CTRL_ENA BIT(0) #define CIF_ISP_LSC_SECT_SIZE_RESERVED 0xFC00FC00 -#define CIF_ISP_LSC_GRAD_RESERVED 0xF000F000 -#define CIF_ISP_LSC_SAMPLE_RESERVED 0xF000F000 +#define CIF_ISP_LSC_GRAD_RESERVED_V10 0xF000F000 +#define CIF_ISP_LSC_SAMPLE_RESERVED_V10 0xF000F000 +#define CIF_ISP_LSC_GRAD_RESERVED_V12 0xE000E000 +#define CIF_ISP_LSC_SAMPLE_RESERVED_V12 0xE000E000 #define CIF_ISP_LSC_SECTORS_MAX 17 -#define CIF_ISP_LSC_TABLE_DATA(v0, v1) \ +#define CIF_ISP_LSC_TABLE_DATA_V10(v0, v1) \ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 12)) +#define CIF_ISP_LSC_TABLE_DATA_V12(v0, v1) \ + (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13)) #define CIF_ISP_LSC_SECT_SIZE(v0, v1) \ (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16)) #define CIF_ISP_LSC_GRAD_SIZE(v0, v1) \ @@ -579,6 +652,10 @@ (1 << 15) | (1 << 11) | (1 << 7) | (1 << 3)) #define CIFISP_DEGAMMA_Y_RESERVED 0xFFFFF000 +/* GAMMA-OUT */ +#define CIF_ISP_GAMMA_REG_VALUE_V12(x, y) \ + (((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0) + /* AFM */ #define CIF_ISP_AFM_ENA BIT(0) #define CIF_ISP_AFM_THRES_RESERVED 0xFFFF0000 @@ -589,6 +666,11 @@ #define CIF_ISP_AFM_WINDOW_Y_MIN 0x2 #define CIF_ISP_AFM_WINDOW_X(x) (((x) & 0x1FFF) << 16) #define CIF_ISP_AFM_WINDOW_Y(x) ((x) & 0x1FFF) +#define CIF_ISP_AFM_SET_SHIFT_a_V12(x, y) (((x) & 0x7) << 16 | ((y) & 0x7) << 0) +#define CIF_ISP_AFM_SET_SHIFT_b_V12(x, y) (((x) & 0x7) << 20 | ((y) & 0x7) << 4) +#define CIF_ISP_AFM_SET_SHIFT_c_V12(x, y) (((x) & 0x7) << 24 | ((y) & 0x7) << 8) +#define CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x) (((x) & 0x70000) >> 16) +#define CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x) ((x) & 0x7) /* DPF */ #define CIF_ISP_DPF_MODE_EN BIT(0) @@ -696,18 +778,38 @@ #define CIF_ISP_GAMMA_B_Y14 (CIF_ISP_BASE + 0x000000E4) #define CIF_ISP_GAMMA_B_Y15 (CIF_ISP_BASE + 0x000000E8) #define CIF_ISP_GAMMA_B_Y16 (CIF_ISP_BASE + 0x000000EC) -#define CIF_ISP_AWB_PROP (CIF_ISP_BASE + 0x00000110) -#define CIF_ISP_AWB_WND_H_OFFS (CIF_ISP_BASE + 0x00000114) -#define CIF_ISP_AWB_WND_V_OFFS (CIF_ISP_BASE + 0x00000118) -#define CIF_ISP_AWB_WND_H_SIZE (CIF_ISP_BASE + 0x0000011C) -#define CIF_ISP_AWB_WND_V_SIZE (CIF_ISP_BASE + 0x00000120) -#define CIF_ISP_AWB_FRAMES (CIF_ISP_BASE + 0x00000124) -#define CIF_ISP_AWB_REF (CIF_ISP_BASE + 0x00000128) -#define CIF_ISP_AWB_THRESH (CIF_ISP_BASE + 0x0000012C) -#define CIF_ISP_AWB_GAIN_G (CIF_ISP_BASE + 0x00000138) -#define CIF_ISP_AWB_GAIN_RB (CIF_ISP_BASE + 0x0000013C) -#define CIF_ISP_AWB_WHITE_CNT (CIF_ISP_BASE + 0x00000140) -#define CIF_ISP_AWB_MEAN (CIF_ISP_BASE + 0x00000144) + +#define CIF_ISP_AWB_PROP_V10 (CIF_ISP_BASE + 0x00000110) +#define CIF_ISP_AWB_WND_H_OFFS_V10 (CIF_ISP_BASE + 0x00000114) +#define CIF_ISP_AWB_WND_V_OFFS_V10 (CIF_ISP_BASE + 0x00000118) +#define CIF_ISP_AWB_WND_H_SIZE_V10 (CIF_ISP_BASE + 0x0000011C) +#define CIF_ISP_AWB_WND_V_SIZE_V10 (CIF_ISP_BASE + 0x00000120) +#define CIF_ISP_AWB_FRAMES_V10 (CIF_ISP_BASE + 0x00000124) +#define CIF_ISP_AWB_REF_V10 (CIF_ISP_BASE + 0x00000128) +#define CIF_ISP_AWB_THRESH_V10 (CIF_ISP_BASE + 0x0000012C) +#define CIF_ISP_AWB_GAIN_G_V10 (CIF_ISP_BASE + 0x00000138) +#define CIF_ISP_AWB_GAIN_RB_V10 (CIF_ISP_BASE + 0x0000013C) +#define CIF_ISP_AWB_WHITE_CNT_V10 (CIF_ISP_BASE + 0x00000140) +#define CIF_ISP_AWB_MEAN_V10 (CIF_ISP_BASE + 0x00000144) + +#define CIF_ISP_AWB_PROP_V12 (CIF_ISP_BASE + 0x00000110) +#define CIF_ISP_AWB_SIZE_V12 (CIF_ISP_BASE + 0x00000114) +#define CIF_ISP_AWB_OFFS_V12 (CIF_ISP_BASE + 0x00000118) +#define CIF_ISP_AWB_REF_V12 (CIF_ISP_BASE + 0x0000011C) +#define CIF_ISP_AWB_THRESH_V12 (CIF_ISP_BASE + 0x00000120) +#define CIF_ISP_X_COOR12_V12 (CIF_ISP_BASE + 0x00000124) +#define CIF_ISP_X_COOR34_V12 (CIF_ISP_BASE + 0x00000128) +#define CIF_ISP_AWB_WHITE_CNT_V12 (CIF_ISP_BASE + 0x0000012C) +#define CIF_ISP_AWB_MEAN_V12 (CIF_ISP_BASE + 0x00000130) +#define CIF_ISP_DEGAIN_V12 (CIF_ISP_BASE + 0x00000134) +#define CIF_ISP_AWB_GAIN_G_V12 (CIF_ISP_BASE + 0x00000138) +#define CIF_ISP_AWB_GAIN_RB_V12 (CIF_ISP_BASE + 0x0000013C) +#define CIF_ISP_REGION_LINE_V12 (CIF_ISP_BASE + 0x00000140) +#define CIF_ISP_WP_CNT_REGION0_V12 (CIF_ISP_BASE + 0x00000160) +#define CIF_ISP_WP_CNT_REGION1_V12 (CIF_ISP_BASE + 0x00000164) +#define CIF_ISP_WP_CNT_REGION2_V12 (CIF_ISP_BASE + 0x00000168) +#define CIF_ISP_WP_CNT_REGION3_V12 (CIF_ISP_BASE + 0x0000016C) + #define CIF_ISP_CC_COEFF_0 (CIF_ISP_BASE + 0x00000170) #define CIF_ISP_CC_COEFF_1 (CIF_ISP_BASE + 0x00000174) #define CIF_ISP_CC_COEFF_2 (CIF_ISP_BASE + 0x00000178) @@ -741,30 +843,32 @@ #define CIF_ISP_CT_COEFF_6 (CIF_ISP_BASE + 0x000001E8) #define CIF_ISP_CT_COEFF_7 (CIF_ISP_BASE + 0x000001EC) #define CIF_ISP_CT_COEFF_8 (CIF_ISP_BASE + 0x000001F0) -#define CIF_ISP_GAMMA_OUT_MODE (CIF_ISP_BASE + 0x000001F4) -#define CIF_ISP_GAMMA_OUT_Y_0 (CIF_ISP_BASE + 0x000001F8) -#define CIF_ISP_GAMMA_OUT_Y_1 (CIF_ISP_BASE + 0x000001FC) -#define CIF_ISP_GAMMA_OUT_Y_2 (CIF_ISP_BASE + 0x00000200) -#define CIF_ISP_GAMMA_OUT_Y_3 (CIF_ISP_BASE + 0x00000204) -#define CIF_ISP_GAMMA_OUT_Y_4 (CIF_ISP_BASE + 0x00000208) -#define CIF_ISP_GAMMA_OUT_Y_5 (CIF_ISP_BASE + 0x0000020C) -#define CIF_ISP_GAMMA_OUT_Y_6 (CIF_ISP_BASE + 0x00000210) -#define CIF_ISP_GAMMA_OUT_Y_7 (CIF_ISP_BASE + 0x00000214) -#define CIF_ISP_GAMMA_OUT_Y_8 (CIF_ISP_BASE + 0x00000218) -#define CIF_ISP_GAMMA_OUT_Y_9 (CIF_ISP_BASE + 0x0000021C) -#define CIF_ISP_GAMMA_OUT_Y_10 (CIF_ISP_BASE + 0x00000220) -#define CIF_ISP_GAMMA_OUT_Y_11 (CIF_ISP_BASE + 0x00000224) -#define CIF_ISP_GAMMA_OUT_Y_12 (CIF_ISP_BASE + 0x00000228) -#define CIF_ISP_GAMMA_OUT_Y_13 (CIF_ISP_BASE + 0x0000022C) -#define CIF_ISP_GAMMA_OUT_Y_14 (CIF_ISP_BASE + 0x00000230) -#define CIF_ISP_GAMMA_OUT_Y_15 (CIF_ISP_BASE + 0x00000234) -#define CIF_ISP_GAMMA_OUT_Y_16 (CIF_ISP_BASE + 0x00000238) +#define CIF_ISP_GAMMA_OUT_MODE_V10 (CIF_ISP_BASE + 0x000001F4) +#define CIF_ISP_GAMMA_OUT_Y_0_V10 (CIF_ISP_BASE + 0x000001F8) +#define CIF_ISP_GAMMA_OUT_Y_1_V10 (CIF_ISP_BASE + 0x000001FC) +#define CIF_ISP_GAMMA_OUT_Y_2_V10 (CIF_ISP_BASE + 0x00000200) +#define CIF_ISP_GAMMA_OUT_Y_3_V10 (CIF_ISP_BASE + 0x00000204) +#define CIF_ISP_GAMMA_OUT_Y_4_V10 (CIF_ISP_BASE + 0x00000208) +#define CIF_ISP_GAMMA_OUT_Y_5_V10 (CIF_ISP_BASE + 0x0000020C) +#define CIF_ISP_GAMMA_OUT_Y_6_V10 (CIF_ISP_BASE + 0x00000210) +#define CIF_ISP_GAMMA_OUT_Y_7_V10 (CIF_ISP_BASE + 0x00000214) +#define CIF_ISP_GAMMA_OUT_Y_8_V10 (CIF_ISP_BASE + 0x00000218) +#define CIF_ISP_GAMMA_OUT_Y_9_V10 (CIF_ISP_BASE + 0x0000021C) +#define CIF_ISP_GAMMA_OUT_Y_10_V10 (CIF_ISP_BASE + 0x00000220) +#define CIF_ISP_GAMMA_OUT_Y_11_V10 (CIF_ISP_BASE + 0x00000224) +#define CIF_ISP_GAMMA_OUT_Y_12_V10 (CIF_ISP_BASE + 0x00000228) +#define CIF_ISP_GAMMA_OUT_Y_13_V10 (CIF_ISP_BASE + 0x0000022C) +#define CIF_ISP_GAMMA_OUT_Y_14_V10 (CIF_ISP_BASE + 0x00000230) +#define CIF_ISP_GAMMA_OUT_Y_15_V10 (CIF_ISP_BASE + 0x00000234) +#define CIF_ISP_GAMMA_OUT_Y_16_V10 (CIF_ISP_BASE + 0x00000238) #define CIF_ISP_ERR (CIF_ISP_BASE + 0x0000023C) #define CIF_ISP_ERR_CLR (CIF_ISP_BASE + 0x00000240) #define CIF_ISP_FRAME_COUNT (CIF_ISP_BASE + 0x00000244) #define CIF_ISP_CT_OFFSET_R (CIF_ISP_BASE + 0x00000248) #define CIF_ISP_CT_OFFSET_G (CIF_ISP_BASE + 0x0000024C) #define CIF_ISP_CT_OFFSET_B (CIF_ISP_BASE + 0x00000250) +#define CIF_ISP_GAMMA_OUT_MODE_V12 (CIF_ISP_BASE + 0x00000300) +#define CIF_ISP_GAMMA_OUT_Y_0_V12 (CIF_ISP_BASE + 0x00000304) #define CIF_ISP_FLASH_BASE 0x00000660 #define CIF_ISP_FLASH_CMD (CIF_ISP_FLASH_BASE + 0x00000000) @@ -1034,36 +1138,35 @@ #define CIF_ISP_IS_H_SIZE_SHD (CIF_ISP_IS_BASE + 0x0000002C) #define CIF_ISP_IS_V_SIZE_SHD (CIF_ISP_IS_BASE + 0x00000030) -#define CIF_ISP_HIST_BASE 0x00002400 - -#define CIF_ISP_HIST_PROP (CIF_ISP_HIST_BASE + 0x00000000) -#define CIF_ISP_HIST_H_OFFS (CIF_ISP_HIST_BASE + 0x00000004) -#define CIF_ISP_HIST_V_OFFS (CIF_ISP_HIST_BASE + 0x00000008) -#define CIF_ISP_HIST_H_SIZE (CIF_ISP_HIST_BASE + 0x0000000C) -#define CIF_ISP_HIST_V_SIZE (CIF_ISP_HIST_BASE + 0x00000010) -#define CIF_ISP_HIST_BIN_0 (CIF_ISP_HIST_BASE + 0x00000014) -#define CIF_ISP_HIST_BIN_1 (CIF_ISP_HIST_BASE + 0x00000018) -#define CIF_ISP_HIST_BIN_2 (CIF_ISP_HIST_BASE + 0x0000001C) -#define CIF_ISP_HIST_BIN_3 (CIF_ISP_HIST_BASE + 0x00000020) -#define CIF_ISP_HIST_BIN_4 (CIF_ISP_HIST_BASE + 0x00000024) -#define CIF_ISP_HIST_BIN_5 (CIF_ISP_HIST_BASE + 0x00000028) -#define CIF_ISP_HIST_BIN_6 (CIF_ISP_HIST_BASE + 0x0000002C) -#define CIF_ISP_HIST_BIN_7 (CIF_ISP_HIST_BASE + 0x00000030) -#define CIF_ISP_HIST_BIN_8 (CIF_ISP_HIST_BASE + 0x00000034) -#define CIF_ISP_HIST_BIN_9 (CIF_ISP_HIST_BASE + 0x00000038) -#define CIF_ISP_HIST_BIN_10 (CIF_ISP_HIST_BASE + 0x0000003C) -#define CIF_ISP_HIST_BIN_11 (CIF_ISP_HIST_BASE + 0x00000040) -#define CIF_ISP_HIST_BIN_12 (CIF_ISP_HIST_BASE + 0x00000044) -#define CIF_ISP_HIST_BIN_13 (CIF_ISP_HIST_BASE + 0x00000048) -#define CIF_ISP_HIST_BIN_14 (CIF_ISP_HIST_BASE + 0x0000004C) -#define CIF_ISP_HIST_BIN_15 (CIF_ISP_HIST_BASE + 0x00000050) -#define CIF_ISP_HIST_WEIGHT_00TO30 (CIF_ISP_HIST_BASE + 0x00000054) -#define CIF_ISP_HIST_WEIGHT_40TO21 (CIF_ISP_HIST_BASE + 0x00000058) -#define CIF_ISP_HIST_WEIGHT_31TO12 (CIF_ISP_HIST_BASE + 0x0000005C) -#define CIF_ISP_HIST_WEIGHT_22TO03 (CIF_ISP_HIST_BASE + 0x00000060) -#define CIF_ISP_HIST_WEIGHT_13TO43 (CIF_ISP_HIST_BASE + 0x00000064) -#define CIF_ISP_HIST_WEIGHT_04TO34 (CIF_ISP_HIST_BASE + 0x00000068) -#define CIF_ISP_HIST_WEIGHT_44 (CIF_ISP_HIST_BASE + 0x0000006C) +#define CIF_ISP_HIST_BASE_V10 0x00002400 +#define CIF_ISP_HIST_PROP_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000000) +#define CIF_ISP_HIST_H_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000004) +#define CIF_ISP_HIST_V_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000008) +#define CIF_ISP_HIST_H_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000000C) +#define CIF_ISP_HIST_V_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000010) +#define CIF_ISP_HIST_BIN_0_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000014) +#define CIF_ISP_HIST_BIN_1_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000018) +#define CIF_ISP_HIST_BIN_2_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000001C) +#define CIF_ISP_HIST_BIN_3_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000020) +#define CIF_ISP_HIST_BIN_4_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000024) +#define CIF_ISP_HIST_BIN_5_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000028) +#define CIF_ISP_HIST_BIN_6_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000002C) +#define CIF_ISP_HIST_BIN_7_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000030) +#define CIF_ISP_HIST_BIN_8_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000034) +#define CIF_ISP_HIST_BIN_9_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000038) +#define CIF_ISP_HIST_BIN_10_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000003C) +#define CIF_ISP_HIST_BIN_11_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000040) +#define CIF_ISP_HIST_BIN_12_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000044) +#define CIF_ISP_HIST_BIN_13_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000048) +#define CIF_ISP_HIST_BIN_14_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000004C) +#define CIF_ISP_HIST_BIN_15_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000050) +#define CIF_ISP_HIST_WEIGHT_00TO30_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000054) +#define CIF_ISP_HIST_WEIGHT_40TO21_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000058) +#define CIF_ISP_HIST_WEIGHT_31TO12_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000005C) +#define CIF_ISP_HIST_WEIGHT_22TO03_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000060) +#define CIF_ISP_HIST_WEIGHT_13TO43_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000064) +#define CIF_ISP_HIST_WEIGHT_04TO34_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000068) +#define CIF_ISP_HIST_WEIGHT_44_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000006C) #define CIF_ISP_FILT_BASE 0x00002500 #define CIF_ISP_FILT_MODE (CIF_ISP_FILT_BASE + 0x00000000) @@ -1089,35 +1192,38 @@ #define CIF_ISP_EXP_BASE 0x00002600 #define CIF_ISP_EXP_CTRL (CIF_ISP_EXP_BASE + 0x00000000) -#define CIF_ISP_EXP_H_OFFSET (CIF_ISP_EXP_BASE + 0x00000004) -#define CIF_ISP_EXP_V_OFFSET (CIF_ISP_EXP_BASE + 0x00000008) -#define CIF_ISP_EXP_H_SIZE (CIF_ISP_EXP_BASE + 0x0000000C) -#define CIF_ISP_EXP_V_SIZE (CIF_ISP_EXP_BASE + 0x00000010) -#define CIF_ISP_EXP_MEAN_00 (CIF_ISP_EXP_BASE + 0x00000014) -#define CIF_ISP_EXP_MEAN_10 (CIF_ISP_EXP_BASE + 0x00000018) -#define CIF_ISP_EXP_MEAN_20 (CIF_ISP_EXP_BASE + 0x0000001c) -#define CIF_ISP_EXP_MEAN_30 (CIF_ISP_EXP_BASE + 0x00000020) -#define CIF_ISP_EXP_MEAN_40 (CIF_ISP_EXP_BASE + 0x00000024) -#define CIF_ISP_EXP_MEAN_01 (CIF_ISP_EXP_BASE + 0x00000028) -#define CIF_ISP_EXP_MEAN_11 (CIF_ISP_EXP_BASE + 0x0000002c) -#define CIF_ISP_EXP_MEAN_21 (CIF_ISP_EXP_BASE + 0x00000030) -#define CIF_ISP_EXP_MEAN_31 (CIF_ISP_EXP_BASE + 0x00000034) -#define CIF_ISP_EXP_MEAN_41 (CIF_ISP_EXP_BASE + 0x00000038) -#define CIF_ISP_EXP_MEAN_02 (CIF_ISP_EXP_BASE + 0x0000003c) -#define CIF_ISP_EXP_MEAN_12 (CIF_ISP_EXP_BASE + 0x00000040) -#define CIF_ISP_EXP_MEAN_22 (CIF_ISP_EXP_BASE + 0x00000044) -#define CIF_ISP_EXP_MEAN_32 (CIF_ISP_EXP_BASE + 0x00000048) -#define CIF_ISP_EXP_MEAN_42 (CIF_ISP_EXP_BASE + 0x0000004c) -#define CIF_ISP_EXP_MEAN_03 (CIF_ISP_EXP_BASE + 0x00000050) -#define CIF_ISP_EXP_MEAN_13 (CIF_ISP_EXP_BASE + 0x00000054) -#define CIF_ISP_EXP_MEAN_23 (CIF_ISP_EXP_BASE + 0x00000058) -#define CIF_ISP_EXP_MEAN_33 (CIF_ISP_EXP_BASE + 0x0000005c) -#define CIF_ISP_EXP_MEAN_43 (CIF_ISP_EXP_BASE + 0x00000060) -#define CIF_ISP_EXP_MEAN_04 (CIF_ISP_EXP_BASE + 0x00000064) -#define CIF_ISP_EXP_MEAN_14 (CIF_ISP_EXP_BASE + 0x00000068) -#define CIF_ISP_EXP_MEAN_24 (CIF_ISP_EXP_BASE + 0x0000006c) -#define CIF_ISP_EXP_MEAN_34 (CIF_ISP_EXP_BASE + 0x00000070) -#define CIF_ISP_EXP_MEAN_44 (CIF_ISP_EXP_BASE + 0x00000074) +#define CIF_ISP_EXP_H_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000004) +#define CIF_ISP_EXP_V_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000008) +#define CIF_ISP_EXP_H_SIZE_V10 (CIF_ISP_EXP_BASE + 0x0000000C) +#define CIF_ISP_EXP_V_SIZE_V10 (CIF_ISP_EXP_BASE + 0x00000010) +#define CIF_ISP_EXP_SIZE_V12 (CIF_ISP_EXP_BASE + 0x00000004) +#define CIF_ISP_EXP_OFFS_V12 (CIF_ISP_EXP_BASE + 0x00000008) +#define CIF_ISP_EXP_MEAN_V12 (CIF_ISP_EXP_BASE + 0x0000000c) +#define CIF_ISP_EXP_MEAN_00_V10 (CIF_ISP_EXP_BASE + 0x00000014) +#define CIF_ISP_EXP_MEAN_10_V10 (CIF_ISP_EXP_BASE + 0x00000018) +#define CIF_ISP_EXP_MEAN_20_V10 (CIF_ISP_EXP_BASE + 0x0000001c) +#define CIF_ISP_EXP_MEAN_30_V10 (CIF_ISP_EXP_BASE + 0x00000020) +#define CIF_ISP_EXP_MEAN_40_V10 (CIF_ISP_EXP_BASE + 0x00000024) +#define CIF_ISP_EXP_MEAN_01_V10 (CIF_ISP_EXP_BASE + 0x00000028) +#define CIF_ISP_EXP_MEAN_11_V10 (CIF_ISP_EXP_BASE + 0x0000002c) +#define CIF_ISP_EXP_MEAN_21_V10 (CIF_ISP_EXP_BASE + 0x00000030) +#define CIF_ISP_EXP_MEAN_31_V10 (CIF_ISP_EXP_BASE + 0x00000034) +#define CIF_ISP_EXP_MEAN_41_V10 (CIF_ISP_EXP_BASE + 0x00000038) +#define CIF_ISP_EXP_MEAN_02_V10 (CIF_ISP_EXP_BASE + 0x0000003c) +#define CIF_ISP_EXP_MEAN_12_V10 (CIF_ISP_EXP_BASE + 0x00000040) +#define CIF_ISP_EXP_MEAN_22_V10 (CIF_ISP_EXP_BASE + 0x00000044) +#define CIF_ISP_EXP_MEAN_32_V10 (CIF_ISP_EXP_BASE + 0x00000048) +#define CIF_ISP_EXP_MEAN_42_V10 (CIF_ISP_EXP_BASE + 0x0000004c) +#define CIF_ISP_EXP_MEAN_03_V10 (CIF_ISP_EXP_BASE + 0x00000050) +#define CIF_ISP_EXP_MEAN_13_V10 (CIF_ISP_EXP_BASE + 0x00000054) +#define CIF_ISP_EXP_MEAN_23_V10 (CIF_ISP_EXP_BASE + 0x00000058) +#define CIF_ISP_EXP_MEAN_33_V10 (CIF_ISP_EXP_BASE + 0x0000005c) +#define CIF_ISP_EXP_MEAN_43_V10 (CIF_ISP_EXP_BASE + 0x00000060) +#define CIF_ISP_EXP_MEAN_04_V10 (CIF_ISP_EXP_BASE + 0x00000064) +#define CIF_ISP_EXP_MEAN_14_V10 (CIF_ISP_EXP_BASE + 0x00000068) +#define CIF_ISP_EXP_MEAN_24_V10 (CIF_ISP_EXP_BASE + 0x0000006c) +#define CIF_ISP_EXP_MEAN_34_V10 (CIF_ISP_EXP_BASE + 0x00000070) +#define CIF_ISP_EXP_MEAN_44_V10 (CIF_ISP_EXP_BASE + 0x00000074) #define CIF_ISP_BLS_BASE 0x00002700 #define CIF_ISP_BLS_CTRL (CIF_ISP_BLS_BASE + 0x00000000) @@ -1278,6 +1384,16 @@ #define CIF_ISP_WDR_TONECURVE_YM_31_SHD (CIF_ISP_WDR_BASE + 0x0000012C) #define CIF_ISP_WDR_TONECURVE_YM_32_SHD (CIF_ISP_WDR_BASE + 0x00000130) +#define CIF_ISP_HIST_BASE_V12 0x00002C00 +#define CIF_ISP_HIST_CTRL_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000000) +#define CIF_ISP_HIST_SIZE_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000004) +#define CIF_ISP_HIST_OFFS_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000008) +#define CIF_ISP_HIST_DBG1_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000000C) +#define CIF_ISP_HIST_DBG2_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000001C) +#define CIF_ISP_HIST_DBG3_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000002C) +#define CIF_ISP_HIST_WEIGHT_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000003C) +#define CIF_ISP_HIST_BIN_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000120) + #define CIF_ISP_VSM_BASE 0x00002F00 #define CIF_ISP_VSM_MODE (CIF_ISP_VSM_BASE + 0x00000000) #define CIF_ISP_VSM_H_OFFS (CIF_ISP_VSM_BASE + 0x00000004) diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h index b471f01a8459..fbeb6b5dba03 100644 --- a/include/uapi/linux/rkisp1-config.h +++ b/include/uapi/linux/rkisp1-config.h @@ -32,8 +32,8 @@ #define CIFISP_CTK_COEFF_MAX 0x100 #define CIFISP_CTK_OFFSET_MAX 0x800 -#define CIFISP_AE_MEAN_MAX 25 -#define CIFISP_HIST_BIN_N_MAX 16 +#define CIFISP_AE_MEAN_MAX 81 +#define CIFISP_HIST_BIN_N_MAX 32 #define CIFISP_AFM_MAX_WINDOWS 3 #define CIFISP_DEGAMMA_CURVE_SIZE 17 @@ -69,7 +69,7 @@ * Gamma out */ /* Maximum number of color samples supported */ -#define CIFISP_GAMMA_OUT_MAX_SAMPLES 17 +#define CIFISP_GAMMA_OUT_MAX_SAMPLES 34 /* * Lens shade correction @@ -87,7 +87,7 @@ * Histogram calculation */ /* Last 3 values unused. */ -#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 28 +#define CIFISP_HISTOGRAM_WEIGHT_GRIDS_SIZE 81 /* * Defect Pixel Cluster Correction @@ -723,7 +723,7 @@ struct cifisp_af_stat { * with ISP_HIST_XXX */ struct cifisp_hist_stat { - unsigned short hist_bins[CIFISP_HIST_BIN_N_MAX]; + unsigned int hist_bins[CIFISP_HIST_BIN_N_MAX]; } __attribute__ ((packed)); /**