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KVM: selftests: Verify that L0's TPR doesn't get clobbered

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Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-ID: <20260813223610.2043560-5-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Sean Christopherson 2026-08-13 15:36:08 -07:00 committed by Paolo Bonzini
parent 0c19bc0ef1
commit 2f00ba93cc
1 changed files with 16 additions and 0 deletions
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16
tools/testing/selftests/kvm/x86/nested_x2apic_test.c
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@ -28,6 +28,10 @@ static void l2_guest_code(void)
{
if (inhibit_apicv)
wrmsr(MSR_IA32_APICBASE, rdmsr(MSR_IA32_APICBASE) & GENMASK_ULL(11, 0));
x2apic_write_reg(APIC_TASKPRI, 0xf0);
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_TASKPRI), 0xf0);
asm volatile("cpuid" ::: "eax", "ebx", "ecx", "edx");
}
@ -73,10 +77,22 @@ static void l1_guest_code(void *test_data)
sti_nop();
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_TASKPRI), 0xf0);
x2apic_write_reg(APIC_ICR, APIC_DEST_SELF | APIC_INT_ASSERT | POSTED_INTR_VECTOR);
GUEST_ASSERT_EQ(nr_irqs, 0);
x2apic_write_reg(APIC_TASKPRI, 0xff);
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_TASKPRI), 0xff);
x2apic_write_reg(APIC_ICR, APIC_DEST_SELF | APIC_INT_ASSERT | POSTED_INTR_WAKEUP_VECTOR);
GUEST_ASSERT_EQ(nr_irqs, 0);
x2apic_write_reg(APIC_TASKPRI, 0);
GUEST_ASSERT_EQ(x2apic_read_reg(APIC_TASKPRI), 0);
x2apic_write_reg(APIC_ICR, APIC_DEST_SELF | APIC_INT_ASSERT | POSTED_INTR_NESTED_VECTOR);
GUEST_ASSERT_EQ(nr_irqs, 3);
GUEST_DONE();
}