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dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID

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Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2025-06-25 15:17:03 +01:00 committed by Geert Uytterhoeven
parent 292bf6c5b8
commit 2a76193f7c
2 changed files with 2 additions and 0 deletions
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1
include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
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@ -24,5 +24,6 @@
#define R9A09G077_CLK_PCLKH 12
#define R9A09G077_CLK_PCLKM 13
#define R9A09G077_CLK_PCLKL 14
#define R9A09G077_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */

1
include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
View File

@ -24,5 +24,6 @@
#define R9A09G087_CLK_PCLKH 12
#define R9A09G087_CLK_PCLKM 13
#define R9A09G087_CLK_PCLKL 14
#define R9A09G087_SDHI_CLKHS 15
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */