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arm64: dts: qcom: ipq5424: Move PHYs and PERST# to Root Port node

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Follow the new binding style by defining PHYs and PERST# (now RESET#)
under the Root Port node. Avoid mixing styles and move these properties
to the RP node.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260609-move_perst_to_rp-v2-2-6c731523d08c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Kathiravan Thirumoorthy 2026-06-09 22:34:06 +05:30 committed by Bjorn Andersson
parent f662fca3dc
commit 29609eb2d9
2 changed files with 20 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
View File

@ -86,8 +86,6 @@ &pcie2 {
pinctrl-0 = <&pcie2_default_state>;
pinctrl-names = "default";
perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -95,12 +93,14 @@ &pcie2_phy {
status = "okay";
};
&pcie2_port0 {
reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
&pcie3 {
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";
perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
status = "okay";
};
@ -108,6 +108,10 @@ &pcie3_phy {
status = "okay";
};
&pcie3_port0 {
reset-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
};
&qusb_phy_0 {
vdd-supply = <&vreg_misc_0p925>;
vdda-pll-supply = <&vreg_misc_1p8>;

24
arch/arm64/boot/dts/qcom/ipq5424.dtsi
View File

@ -968,19 +968,19 @@ pcie3: pcie@40000000 {
"aux",
"ahb";
phys = <&pcie3_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
<&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie3_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie3_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -1071,19 +1071,19 @@ pcie2: pcie@50000000 {
"aux",
"ahb";
phys = <&pcie2_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
<&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie2_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -1174,19 +1174,19 @@ pcie1: pcie@60000000 {
"aux",
"ahb";
phys = <&pcie1_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
<&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie1_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@ -1277,19 +1277,19 @@ pcie0: pcie@70000000 {
"aux",
"ahb";
phys = <&pcie0_phy>;
phy-names = "pciephy";
interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
<&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>;
interconnect-names = "pcie-mem", "cpu-pcie";
status = "disabled";
pcie@0 {
pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;