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PCI: rcar-gen4: Add Application/Local register reset control
The R-Car Gen4 PCIe controller does contain core reset, which puts the
controller back into well-defined state, but it does also tear down the
PCIe link. This is called Application/Local register reset in the
documentation.
Deassert the core reset after the core clock has been enabled, and assert
the core reset in case of error or when shutting down the controller.
This also fixes reinitialization failure of the controller, where if the
controller driver is unbound and bound again via sysfs attributes, the
controller driver will fail to probe the second time because it fails to
access the controller DBI, which returns all zeroes unless the core reset
is toggled. The following commands trigger this fault on R-Car V4H:
$ echo e65d0000.pcie > /sys/bus/platform/drivers/pcie-rcar-gen4/unbind
$ echo e65d0000.pcie > /sys/bus/platform/drivers/pcie-rcar-gen4/bind
Fixes: faf5a975ee ("PCI: rcar-gen4: Add support for R-Car V4H")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[mani: added fixes tag and cced noautosel]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: <stable+noautosel@kernel.org> # DTS dependency
Link: https://patch.msgid.link/20260903205153.283553-3-marek.vasut+renesas@mailbox.org
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@ -237,6 +237,8 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
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return ret;
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}
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reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
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if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
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reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
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/*
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@ -284,6 +286,7 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
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return 0;
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err_unprepare:
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reset_control_assert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
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clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
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return ret;
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@ -362,6 +365,7 @@ static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
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struct dw_pcie *dw = &rcar->dw;
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reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
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reset_control_assert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
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clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
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}
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