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misc: qcom-coincell: Migrate to devm_spmi_subdevice_alloc_and_add()
Some Qualcomm PMICs integrate a charger for coincells, usually powering an RTC when external (or main battery) power is missing. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -256,6 +256,8 @@ config HP_ILO
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config QCOM_COINCELL
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tristate "Qualcomm coincell charger support"
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depends on MFD_SPMI_PMIC || COMPILE_TEST
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depends on SPMI
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select REGMAP_SPMI
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help
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This driver supports the coincell block found inside of
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Qualcomm PMICs. The coincell charger provides a means to
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@ -9,11 +9,11 @@
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/platform_device.h>
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#include <linux/spmi.h>
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struct qcom_coincell {
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struct device *dev;
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struct regmap *regmap;
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u32 base_addr;
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};
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#define QCOM_COINCELL_REG_RSET 0x44
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@ -35,7 +35,7 @@ static int qcom_coincell_chgr_config(struct qcom_coincell *chgr, int rset,
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/* if disabling, just do that and skip other operations */
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if (!enable)
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return regmap_write(chgr->regmap,
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chgr->base_addr + QCOM_COINCELL_REG_ENABLE, 0);
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QCOM_COINCELL_REG_ENABLE, 0);
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/* find index for current-limiting resistor */
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for (i = 0; i < ARRAY_SIZE(qcom_rset_map); i++)
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@ -58,7 +58,7 @@ static int qcom_coincell_chgr_config(struct qcom_coincell *chgr, int rset,
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}
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rc = regmap_write(chgr->regmap,
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chgr->base_addr + QCOM_COINCELL_REG_RSET, i);
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QCOM_COINCELL_REG_RSET, i);
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if (rc) {
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/*
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* This is mainly to flag a bad base_addr (reg) from dts.
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@ -71,19 +71,28 @@ static int qcom_coincell_chgr_config(struct qcom_coincell *chgr, int rset,
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}
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rc = regmap_write(chgr->regmap,
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chgr->base_addr + QCOM_COINCELL_REG_VSET, j);
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QCOM_COINCELL_REG_VSET, j);
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if (rc)
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return rc;
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/* set 'enable' register */
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return regmap_write(chgr->regmap,
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chgr->base_addr + QCOM_COINCELL_REG_ENABLE,
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QCOM_COINCELL_REG_ENABLE,
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QCOM_COINCELL_ENABLE);
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}
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static int qcom_coincell_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct regmap_config qcom_coincell_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0xff,
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.fast_io = true,
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};
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct spmi_subdevice *sub_sdev;
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struct spmi_device *sparent;
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struct qcom_coincell chgr;
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u32 rset = 0;
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u32 vset = 0;
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@ -92,16 +101,25 @@ static int qcom_coincell_probe(struct platform_device *pdev)
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chgr.dev = &pdev->dev;
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chgr.regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!chgr.regmap) {
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dev_err(chgr.dev, "Unable to get regmap\n");
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return -EINVAL;
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}
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rc = of_property_read_u32(node, "reg", &chgr.base_addr);
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rc = device_property_read_u32(dev, "reg", &qcom_coincell_regmap_config.reg_base);
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if (rc)
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return rc;
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sparent = spmi_get_parent_spmi_device(dev);
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if (!sparent)
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return -ENODEV;
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sub_sdev = devm_spmi_subdevice_alloc_and_add(dev, sparent);
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if (IS_ERR(sub_sdev))
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return PTR_ERR(sub_sdev);
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chgr.regmap = devm_regmap_init_spmi_ext(&sub_sdev->sdev,
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&qcom_coincell_regmap_config);
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if (IS_ERR(chgr.regmap)) {
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dev_err(chgr.dev, "Unable to get regmap\n");
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return PTR_ERR(chgr.regmap);
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}
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enable = !of_property_read_bool(node, "qcom,charger-disable");
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if (enable) {
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@ -142,3 +160,4 @@ module_platform_driver(qcom_coincell_driver);
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MODULE_DESCRIPTION("Qualcomm PMIC coincell charger driver");
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS("SPMI");
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