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intel_idle: Introduce a helper for checking PC6
Introduce the skx_is_pc6_disabled() for checking if PC6 is disabled and switch the following functions to use it: - skx_idle_state_table_update() - spr_idle_state_table_update() At the same time, clean them up improving the commentary and moving it to the function kernel-doc. Purely a clean up, no functional changes intended. Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Link: https://patch.msgid.link/20260425072532.358365-4-dedekind1@gmail.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -2079,12 +2079,13 @@ static void __init sklh_idle_state_table_update(void)
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}
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/**
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* skx_idle_state_table_update - Adjust the Sky Lake/Cascade Lake
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* idle states table.
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* skx_is_pc6_disabled() - Check if PC6 is disabled in BIOS.
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*
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* Return: %true if PC6 is disabled, %false otherwise.
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*/
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static void __init skx_idle_state_table_update(void)
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static bool __init skx_is_pc6_disabled(void)
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{
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unsigned long long msr;
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u64 msr;
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rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr);
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@ -2095,35 +2096,34 @@ static void __init skx_idle_state_table_update(void)
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* 011b: C6 (retention)
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* 111b: No Package C state limits.
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*/
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if ((msr & SKX_PKG_CST_LIMIT_MASK) < SKX_PKG_CST_LIMIT_PC6) {
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/*
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* Uses the CC6 + PC0 latency and 3 times of
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* latency for target_residency if the PC6
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* is disabled in BIOS. This is consistent
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* with how intel_idle driver uses _CST
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* to set the target_residency.
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*/
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return (msr & SKX_PKG_CST_LIMIT_MASK) < SKX_PKG_CST_LIMIT_PC6;
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}
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/**
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* skx_idle_state_table_update - Adjust the SKX/CLX idle states table.
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*
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* Adjust Sky Lake or Cascade Lake Xeon idle states if PC6 is disabled in BIOS.
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* Use the CC6 + PC0 latency and 3 times of that latency for target_residency.
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* This is consistent with how the intel_idle driver uses _CST to set the
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* target_residency.
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*/
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static void __init skx_idle_state_table_update(void)
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{
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if (skx_is_pc6_disabled()) {
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skx_cstates[2].exit_latency = 92;
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skx_cstates[2].target_residency = 276;
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}
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}
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/**
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* spr_idle_state_table_update - Adjust Sapphire Rapids idle states table.
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* spr_idle_state_table_update - Adjust Sapphire Rapids Xeon idle states table.
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*
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* By default, the C6 state assumes the worst-case scenario of package C6.
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* However, if PC6 is disabled in BIOS, update the numbers to match core C6.
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*/
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static void __init spr_idle_state_table_update(void)
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{
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unsigned long long msr;
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/*
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* By default, the C6 state assumes the worst-case scenario of package
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* C6. However, if PC6 is disabled, we update the numbers to match
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* core C6.
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*/
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rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr);
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/* Limit value 2 and above allow for PC6. */
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if ((msr & SKX_PKG_CST_LIMIT_MASK) < SKX_PKG_CST_LIMIT_PC6) {
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if (skx_is_pc6_disabled()) {
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spr_cstates[2].exit_latency = 190;
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spr_cstates[2].target_residency = 600;
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}
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