intel_idle: Add constants for MSR_PKG_CST_CONFIG_CONTROL

Add two constants for the package C-state limit fields in
MSR_PKG_CST_CONFIG_CONTROL.

The SKX_ prefix stands for "Skylake Xeon" and makes it explicit that
the mask is CPU model-specific. The same values have applied to all
Xeon platforms starting from SKX.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Link: https://patch.msgid.link/20260425072532.358365-2-dedekind1@gmail.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Artem Bityutskiy 2026-04-25 10:25:29 +03:00 committed by Rafael J. Wysocki
parent 5200f5f493
commit 06dbe26280

View File

@ -81,6 +81,11 @@ static bool ibrs_off __read_mostly;
/* Maximum allowed C-state target residency */
#define MAX_CMDLINE_RESIDENCY_US (100 * USEC_PER_MSEC)
/* The Package C-State Limit bits in MSR_PKG_CST_CONFIG_CONTROL */
#define SKX_PKG_CST_LIMIT_MASK GENMASK(2, 0)
/* PC6 is enabled when Package C-State Limit >= this value */
#define SKX_PKG_CST_LIMIT_PC6 2
static char cmdline_table_str[MAX_CMDLINE_TABLE_LEN] __read_mostly;
static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
@ -2090,7 +2095,7 @@ static void __init skx_idle_state_table_update(void)
* 011b: C6 (retention)
* 111b: No Package C state limits.
*/
if ((msr & 0x7) < 2) {
if ((msr & SKX_PKG_CST_LIMIT_MASK) < SKX_PKG_CST_LIMIT_PC6) {
/*
* Uses the CC6 + PC0 latency and 3 times of
* latency for target_residency if the PC6
@ -2118,7 +2123,7 @@ static void __init spr_idle_state_table_update(void)
rdmsrq(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Limit value 2 and above allow for PC6. */
if ((msr & 0x7) < 2) {
if ((msr & SKX_PKG_CST_LIMIT_MASK) < SKX_PKG_CST_LIMIT_PC6) {
spr_cstates[2].exit_latency = 190;
spr_cstates[2].target_residency = 600;
}