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riscv: dts: microchip: convert clock and reset to use syscon

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The "subblock" clocks and reset registers on PolarFire SoC are located
in the mss-top-sysreg region, alongside pinctrl and interrupt control
functionality. Re-write the devicetree to describe the sys explicitly,
as its own node, rather than as a region of the clock node.
Correspondingly, the phandles to the reset controller must be updated to
the new provider. The drivers will continue to support the old way of
doing things.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley 2025-11-10 11:23:52 +00:00
parent 6f86a41d21
commit 26535e8444
1 changed files with 12 additions and 7 deletions
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19
arch/riscv/boot/dts/microchip/mpfs.dtsi
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@ -251,11 +251,9 @@ pdma: dma-controller@3000000 {
#dma-cells = <1>;
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
mss_top_sysreg: syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
reg = <0x0 0x20002000 0x0 0x1000>;
#reset-cells = <1>;
};
@ -452,7 +450,7 @@ mac0: ethernet@20110000 {
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
resets = <&clkcfg CLK_MAC0>;
resets = <&mss_top_sysreg CLK_MAC0>;
status = "disabled";
};
@ -466,7 +464,7 @@ mac1: ethernet@20112000 {
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
resets = <&clkcfg CLK_MAC1>;
resets = <&mss_top_sysreg CLK_MAC1>;
status = "disabled";
};
@ -550,5 +548,12 @@ syscontroller_qspi: spi@37020100 {
clocks = <&scbclk>;
status = "disabled";
};
clkcfg: clkcfg@3e001000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x3e001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
};
};
};