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riscv: dts: microchip: fix mailbox description

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When the binding for the mailbox on PolarFire SoC was originally
written, and later modified, mistakes were made - and the precise
nature of the later modification should have been a giveaway, but alas
I was naive at the time.

A more correct modelling of the hardware is to use two syscons and have
a single reg entry for the mailbox, containing the mailbox region. The
two syscons contain the general control/status registers for the mailbox
and the interrupt related registers respectively. The reason for two
syscons is that the same mailbox is present on the non-SoC version of
the FPGA, which has no interrupt controller, and the shared part of the
rtl was unchanged between devices.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley 2025-11-10 11:23:51 +00:00
parent 8f0b4cce44
commit 6f86a41d21
1 changed files with 12 additions and 3 deletions
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15
arch/riscv/boot/dts/microchip/mpfs.dtsi
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@ -259,6 +259,11 @@ clkcfg: clkcfg@20002000 {
#reset-cells = <1>;
};
sysreg_scb: syscon@20003000 {
compatible = "microchip,mpfs-sysreg-scb", "syscon";
reg = <0x0 0x20003000 0x0 0x1000>;
};
ccc_se: clock-controller@38010000 {
compatible = "microchip,mpfs-ccc";
reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
@ -521,10 +526,14 @@ usb: usb@20201000 {
status = "disabled";
};
mbox: mailbox@37020000 {
control_scb: syscon@37020000 {
compatible = "microchip,mpfs-control-scb", "syscon";
reg = <0x0 0x37020000 0x0 0x100>;
};
mbox: mailbox@37020800 {
compatible = "microchip,mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
<0x0 0x37020800 0x0 0x100>;
reg = <0x0 0x37020800 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <96>;
#mbox-cells = <1>;