mirror of
https://github.com/torvalds/linux.git
synced 2026-06-06 05:27:07 +02:00
Renesas ARM DT updates for v5.12
- Timer (CMT/TMU) support for R-Car Gen3 SoCs,
- Watchdog (RWDT), pincontrol (PFC), GPIO, and DMA (SYS-DMAC) support
for the R-Car V3U SoC,
- USB2 clock selector and SPI Multi I/O Bus Controller (RPC-IF)
support for RZ/G2 SoCs,
- Support for the Beacon EmbeddedWorks RZ/G2H and RZ/G2N kits,
- Various fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.12
- Timer (CMT/TMU) support for R-Car Gen3 SoCs,
- Watchdog (RWDT), pincontrol (PFC), GPIO, and DMA (SYS-DMAC) support
for the R-Car V3U SoC,
- USB2 clock selector and SPI Multi I/O Bus Controller (RPC-IF)
support for RZ/G2 SoCs,
- Support for the Beacon EmbeddedWorks RZ/G2H and RZ/G2N kits,
- Various fixes and improvements.
* tag 'renesas-arm-dt-for-v5.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (24 commits)
arm64: dts: renesas: r8a779a0: Add SYS-DMAC nodes
arm64: dts: renesas: r8a779a0: Add GPIO nodes
arm64: dts: renesas: r8a779a0: Add pinctrl device node
arm64: dts: renesas: rzg2: Add RPC-IF Support
arm64: dts: renesas: rzg2: Add usb2_clksel to RZ/G2 M/N/H
arm64: dts: renesas: r8a774e1: Introduce beacon-rzg2h-kit
arm64: dts: renesas: r8a774b1: Introduce beacon-rzg2n-kit
arm64: dts: renesas: beacon-rzg2m-kit: Rearrange SoC unique functions
arm64: dts: renesas: beacon: Better describe keys
arm64: dts: renesas: beacon: Configure Audio CODEC clocks
arm64: dts: renesas: beacon kit: Fix Audio Clock sources
arm64: dts: renesas: beacon: Configure programmable clocks
arm64: dts: renesas: falcon: Enable watchdog timer
arm64: dts: renesas: r8a779a0: Add RWDT node
arm64: dts: renesas: beacon: Correct I2C bus speeds
arm64: dts: renesas: beacon: Enable SPI
arm64: dts: renesas: beacon: Don't make vccq_sdhi0 always on
arm64: dts: renesas: beacon: Fix RGB Display PWM Backlight
arm64: dts: renesas: beacon: Fix LVDS PWM Backlight
arm64: dts: renesas: beacon: Fix audio-1.8V pin enable
...
Link: https://lore.kernel.org/r/20210115094610.2334058-2-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
2555a61090
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|
@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb
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|||
dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb
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dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb
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dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb
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dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb
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dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb
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dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb
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@ -21,6 +22,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb
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dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-idk-2121wr.dtb
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dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb
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dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-beacon-rzg2h-kit.dtb
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dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb
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dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb
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dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb
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@ -5,23 +5,24 @@
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/clk/versaclock.h>
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/ {
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backlight_lvds: backlight-lvds {
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compatible = "pwm-backlight";
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power-supply = <®_lcd>;
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enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_LOW>;
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pwms = <&pwm2 0 50000>;
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enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>;
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pwms = <&pwm2 0 25000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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};
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backlight_rgb: backlight-rgb {
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backlight_dpi: backlight-dpi {
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compatible = "pwm-backlight";
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power-supply = <®_lcd>;
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enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>;
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pwms = <&pwm0 0 50000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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pwms = <&pwm0 0 25000>;
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brightness-levels = <0 25 33 50 63 75 88 100>;
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default-brightness-level = <6>;
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};
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@ -39,38 +40,38 @@ hdmi0_con: endpoint {
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keys {
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compatible = "gpio-keys";
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key-1 {
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key-1 { /* S19 */
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gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_1>;
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label = "Switch-1";
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linux,code = <KEY_UP>;
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label = "Up";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-2 {
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key-2 { /*S20 */
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gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_2>;
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label = "Switch-2";
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linux,code = <KEY_LEFT>;
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label = "Left";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-3 {
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key-3 { /* S21 */
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gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_3>;
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label = "Switch-3";
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linux,code = <KEY_DOWN>;
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label = "Down";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-4 {
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key-4 { /* S22 */
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gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_4>;
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label = "Switch-4";
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linux,code = <KEY_RIGHT>;
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label = "Right";
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wakeup-source;
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debounce-interval = <20>;
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};
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key-5 {
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key-5 { /* S23 */
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gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_5>;
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label = "Switch-4";
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linux,code = <KEY_ENTER>;
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label = "Center";
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wakeup-source;
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debounce-interval = <20>;
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};
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@ -118,9 +119,9 @@ panel-timing {
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hback-porch = <40>;
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vfront-porch = <13>;
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vback-porch = <29>;
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vsync-len = <3>;
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vsync-len = <1>;
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hsync-active = <1>;
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vsync-active = <1>;
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vsync-active = <3>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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@ -135,7 +136,7 @@ panel_in: endpoint {
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rgb {
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/* Different LCD with compatible timings */
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compatible = "rocktech,rk070er9427";
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backlight = <&backlight_rgb>;
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backlight = <&backlight_dpi>;
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enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
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power-supply = <®_lcd>;
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port {
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||||
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@ -150,7 +151,7 @@ reg_audio: regulator_audio {
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regulator-name = "audio-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>;
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gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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@ -200,15 +201,12 @@ sound_card {
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|||
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1>, <1800000 0>;
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regulator-always-on;
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};
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|
||||
/* External DU dot clocks */
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||||
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@ -248,12 +246,6 @@ ss_ep: endpoint {
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|||
};
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||||
};
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&audio_clk_a {
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clock-frequency = <24576000>;
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assigned-clocks = <&versaclock6_bb 4>;
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assigned-clock-rates = <24576000>;
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};
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&audio_clk_b {
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clock-frequency = <22579200>;
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};
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@ -272,21 +264,6 @@ &can1 {
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status = "okay";
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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clocks = <&cpg CPG_MOD 724>,
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<&cpg CPG_MOD 723>,
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<&cpg CPG_MOD 722>,
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<&versaclock5 1>,
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<&x302_clk>,
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<&versaclock5 2>;
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clock-names = "du.0", "du.1", "du.2",
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"dclkin.0", "dclkin.1", "dclkin.2";
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};
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|
||||
&du_out_rgb {
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remote-endpoint = <&rgb_panel>;
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};
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@ -342,7 +319,7 @@ &hsusb {
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|||
|
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&i2c2 {
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status = "okay";
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clock-frequency = <100000>;
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c2_pins>;
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pinctrl-names = "default";
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||||
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||||
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@ -373,12 +350,36 @@ versaclock6_bb: clock-controller@6a {
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#clock-cells = <1>;
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clocks = <&x304_clk>;
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clock-names = "xin";
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/* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */
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assigned-clocks = <&versaclock6_bb 1>,
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<&versaclock6_bb 2>,
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<&versaclock6_bb 3>,
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<&versaclock6_bb 4>;
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assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>;
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OUT1 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <100>;
|
||||
};
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OUT2 {
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <1800000>;
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idt,slew-percent = <100>;
|
||||
};
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|
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OUT3 {
|
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idt,mode = <VC5_CMOS>;
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idt,voltage-microvolt = <3300000>;
|
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idt,slew-percent = <100>;
|
||||
};
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|
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OUT4 {
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||||
idt,mode = <VC5_CMOS>;
|
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idt,voltage-microvolt = <3300000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
};
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||||
};
|
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@ -392,13 +393,14 @@ &i2c0 {
|
|||
|
||||
&i2c5 {
|
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status = "okay";
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clock-frequency = <100000>;
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-0 = <&i2c5_pins>;
|
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pinctrl-names = "default";
|
||||
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codec: wm8962@1a {
|
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compatible = "wlf,wm8962";
|
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reg = <0x1a>;
|
||||
clocks = <&versaclock6_bb 3>;
|
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DCVDD-supply = <®_audio>;
|
||||
DBVDD-supply = <®_audio>;
|
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AVDD-supply = <®_audio>;
|
||||
|
|
@ -481,6 +483,13 @@ lvds0_out: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
&msiof1 {
|
||||
pinctrl-0 = <&msiof1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
|
|
@ -534,6 +543,11 @@ led_pins: leds {
|
|||
bias-pull-down;
|
||||
};
|
||||
|
||||
msiof1_pins: msiof1 {
|
||||
groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g";
|
||||
function = "msiof1";
|
||||
};
|
||||
|
||||
pwm0_pins: pwm0 {
|
||||
groups = "pwm0";
|
||||
function = "pwm0";
|
||||
|
|
@ -541,7 +555,7 @@ pwm0_pins: pwm0 {
|
|||
|
||||
pwm2_pins: pwm2 {
|
||||
groups = "pwm2_a";
|
||||
function = "pwm2_a";
|
||||
function = "pwm2";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
|
|
@ -562,7 +576,7 @@ sound_pins: sound {
|
|||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a_a";
|
||||
groups = "audio_clk_a_a", "audio_clk_b_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
|
|
@ -613,23 +627,6 @@ &rcar_sound {
|
|||
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/clk/versaclock.h>
|
||||
|
||||
/ {
|
||||
memory@48000000 {
|
||||
|
|
@ -12,11 +13,6 @@ memory@48000000 {
|
|||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
osc_32k: osc_32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
|
|
@ -89,7 +85,6 @@ &hscif0 {
|
|||
pinctrl-names = "default";
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
max-speed = <4000000>;
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
|
|
@ -98,6 +93,7 @@ bluetooth {
|
|||
device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&osc_32k>;
|
||||
clock-names = "extclk";
|
||||
max-speed = <4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -109,7 +105,7 @@ &hscif2 {
|
|||
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pca9654: gpio@20 {
|
||||
compatible = "onnn,pca9654";
|
||||
|
|
@ -170,7 +166,32 @@ versaclock5: versaclock_som@6a {
|
|||
<&versaclock5 2>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 4>;
|
||||
|
||||
assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>;
|
||||
|
||||
OUT1 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
|
||||
OUT2 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
|
||||
OUT3 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <1800000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
|
||||
OUT4 {
|
||||
idt,mode = <VC5_CMOS>;
|
||||
idt,voltage-microvolt = <3300000>;
|
||||
idt,slew-percent = <100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -303,11 +324,3 @@ &usb_extal_clk {
|
|||
&usb3s0_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&vspb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vspi0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,4 +26,45 @@ aliases {
|
|||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@600000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x6 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
/* Reference versaclock instead of audio_clk_a */
|
||||
&rcar_sound {
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&versaclock6_bb 4>, <&audio_clk_b>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774A1_CLK_S0D4>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -835,6 +835,21 @@ hsusb: usb@e6590000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a774a1-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
|
||||
<&usb_extal_clk>, <&usb3s0_clk>;
|
||||
clock-names = "ehci_ohci", "hs-usb-if",
|
||||
"usb_extal", "usb_xtal";
|
||||
#clock-cells = <0>;
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
reset-names = "ehci_ohci", "hs-usb-if";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a774a1-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
|
|
@ -2302,6 +2317,23 @@ sdhi3: mmc@ee160000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a774a1-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
|
|||
66
arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts
Normal file
66
arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020, Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r8a774b1.dtsi"
|
||||
#include "beacon-renesom-som.dtsi"
|
||||
#include "beacon-renesom-baseboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2N Development Kit";
|
||||
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif0;
|
||||
serial2 = &hscif1;
|
||||
serial3 = &scif0;
|
||||
serial4 = &hscif2;
|
||||
serial5 = &scif5;
|
||||
serial6 = &scif4;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
/* Reference versaclock instead of audio_clk_a */
|
||||
&rcar_sound {
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&versaclock6_bb 4>, <&audio_clk_b>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774B1_CLK_S0D4>;
|
||||
};
|
||||
|
|
@ -709,6 +709,21 @@ hsusb: usb@e6590000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a774b1-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
|
||||
<&usb_extal_clk>, <&usb3s0_clk>;
|
||||
clock-names = "ehci_ohci", "hs-usb-if",
|
||||
"usb_extal", "usb_xtal";
|
||||
#clock-cells = <0>;
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
reset-names = "ehci_ohci", "hs-usb-if";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a774b1-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
|
|
@ -2160,6 +2175,23 @@ sdhi3: mmc@ee160000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a774b1-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a774b1",
|
||||
"renesas,rcar-gen3-sata";
|
||||
|
|
|
|||
|
|
@ -1654,6 +1654,23 @@ sdhi3: mmc@ee160000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a774c0-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
|
|||
71
arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts
Normal file
71
arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2020, Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "r8a774e1.dtsi"
|
||||
#include "beacon-renesom-som.dtsi"
|
||||
#include "beacon-renesom-baseboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Beacon Embedded Works RZ/G2H Development Kit";
|
||||
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
|
||||
|
||||
aliases {
|
||||
serial0 = &scif2;
|
||||
serial1 = &hscif0;
|
||||
serial2 = &hscif1;
|
||||
serial3 = &scif0;
|
||||
serial4 = &hscif2;
|
||||
serial5 = &scif5;
|
||||
serial6 = &scif4;
|
||||
ethernet0 = &avb;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@500000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x5 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&x302_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
|
||||
/* Reference versaclock instead of audio_clk_a */
|
||||
&rcar_sound {
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&versaclock6_bb 4>, <&audio_clk_b>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A774E1_CLK_S0D4>;
|
||||
};
|
||||
|
|
@ -890,6 +890,21 @@ hsusb: usb@e6590000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_clksel: clock-controller@e6590630 {
|
||||
compatible = "renesas,r8a774e1-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
|
||||
<&usb_extal_clk>, <&usb3s0_clk>;
|
||||
clock-names = "ehci_ohci", "hs-usb-if",
|
||||
"usb_extal", "usb_xtal";
|
||||
#clock-cells = <0>;
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
reset-names = "ehci_ohci", "hs-usb-if";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a774e1-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
|
|
@ -2393,6 +2408,23 @@ sdhi3: mmc@ee160000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rpc: spi@ee200000 {
|
||||
compatible = "renesas,r8a774e1-rpc-if",
|
||||
"renesas,rcar-gen3-rpc-if";
|
||||
reg = <0 0xee200000 0 0x200>,
|
||||
<0 0x08000000 0 0x4000000>,
|
||||
<0 0xee208000 0 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
clock-names = "rpc";
|
||||
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a774e1",
|
||||
"renesas,rcar-gen3-sata";
|
||||
|
|
|
|||
|
|
@ -616,6 +616,71 @@ intc_ex: interrupt-controller@e61c0000 {
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a7795", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -585,6 +585,71 @@ intc_ex: interrupt-controller@e61c0000 {
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a7796", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -453,6 +453,76 @@ pfc: pinctrl@e6060000 {
|
|||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
||||
cmt0: timer@e60f0000 {
|
||||
compatible = "renesas,r8a77961-cmt0",
|
||||
"renesas,rcar-gen3-cmt0";
|
||||
reg = <0 0xe60f0000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 303>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 303>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a77961-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 302>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 302>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt2: timer@e6140000 {
|
||||
compatible = "renesas,r8a77961-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6140000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 301>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 301>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt3: timer@e6148000 {
|
||||
compatible = "renesas,r8a77961-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6148000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 300>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77961-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
|
|
@ -495,6 +565,71 @@ intc_ex: interrupt-controller@e61c0000 {
|
|||
/* placeholder */
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77961", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77961", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77961", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77961", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77961", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -455,6 +455,71 @@ intc_ex: interrupt-controller@e61c0000 {
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77965", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -420,6 +420,71 @@ intc_ex: interrupt-controller@e61c0000 {
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77990", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -193,6 +193,76 @@ pfc: pinctrl@e6060000 {
|
|||
reg = <0 0xe6060000 0 0x508>;
|
||||
};
|
||||
|
||||
cmt0: timer@e60f0000 {
|
||||
compatible = "renesas,r8a77995-cmt0",
|
||||
"renesas,rcar-gen3-cmt0";
|
||||
reg = <0 0xe60f0000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 303>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 303>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a77995-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 302>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 302>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt2: timer@e6140000 {
|
||||
compatible = "renesas,r8a77995-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6140000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 301>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 301>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt3: timer@e6148000 {
|
||||
compatible = "renesas,r8a77995-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6148000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 300>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77995-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
|
|
@ -242,6 +312,71 @@ intc_ex: interrupt-controller@e61c0000 {
|
|||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -20,3 +20,8 @@ chosen {
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -70,6 +70,165 @@ soc: soc {
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
rwdt: watchdog@e6020000 {
|
||||
compatible = "renesas,r8a779a0-wdt",
|
||||
"renesas,rcar-gen3-wdt";
|
||||
reg = <0 0xe6020000 0 0x0c>;
|
||||
clocks = <&cpg CPG_MOD 907>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 907>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pfc: pin-controller@e6050000 {
|
||||
compatible = "renesas,pfc-r8a779a0";
|
||||
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
|
||||
<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
|
||||
<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
|
||||
<0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
|
||||
<0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
|
||||
};
|
||||
|
||||
gpio0: gpio@e6058180 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6058180 0 0x54>;
|
||||
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 0 28>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@e6050180 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6050180 0 0x54>;
|
||||
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 32 31>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@e6050980 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6050980 0 0x54>;
|
||||
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 64 25>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@e6058980 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6058980 0 0x54>;
|
||||
interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 96 17>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@e6060180 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6060180 0 0x54>;
|
||||
interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 128 27>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@e6060980 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6060980 0 0x54>;
|
||||
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 160 21>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@e6068180 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6068180 0 0x54>;
|
||||
interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 918>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 918>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 192 21>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@e6068980 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6068980 0 0x54>;
|
||||
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 918>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 918>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 224 21>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio8: gpio@e6069180 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6069180 0 0x54>;
|
||||
interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 918>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 918>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 256 21>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio9: gpio@e6069980 {
|
||||
compatible = "renesas,gpio-r8a779a0";
|
||||
reg = <0 0xe6069980 0 0x54>;
|
||||
interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 918>;
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 918>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pfc 0 288 21>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a779a0-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x4000>;
|
||||
|
|
@ -105,6 +264,64 @@ scif0: serial@e6e60000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7350000 {
|
||||
compatible = "renesas,dmac-r8a779a0";
|
||||
reg = <0 0xe7350000 0 0x1000>,
|
||||
<0 0xe7300000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3", "ch4",
|
||||
"ch5", "ch6", "ch7", "ch8", "ch9",
|
||||
"ch10", "ch11", "ch12", "ch13",
|
||||
"ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 709>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 709>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7351000 {
|
||||
compatible = "renesas,dmac-r8a779a0";
|
||||
reg = <0 0xe7351000 0 0x1000>,
|
||||
<0 0xe7310000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3", "ch4",
|
||||
"ch5", "ch6", "ch7";
|
||||
clocks = <&cpg CPG_MOD 710>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 710>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user