From 5edf8bd6f4a225f7ad0501f921f9717df152e7fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 9 Dec 2020 21:07:37 +0100 Subject: [PATCH 01/24] arm64: dts: renesas: rcar-gen3: Add missing CMT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device nodes for the Compare Match Timer (CMT) on the Renesas R-Car M3-W+ (r8a77961) and D3 (r8a77995) SoCs. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201209200738.811173-2-niklas.soderlund+renesas@ragnatech.se [geert: squashed two commits] Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 70 +++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 70 +++++++++++++++++++++++ 2 files changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 4b737c616257..4b5b242d5b25 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -453,6 +453,76 @@ pfc: pinctrl@e6060000 { reg = <0 0xe6060000 0 0x50c>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a77961-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77961-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a77961-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a77961-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77961-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index e1af7c4782f4..aca0b2d015cf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -193,6 +193,76 @@ pfc: pinctrl@e6060000 { reg = <0 0xe6060000 0 0x508>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a77995-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a77995-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a77995-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a77995-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a77995-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; From 4e4c17c6c3907dfc34051cc450a78a38fb371b4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Thu, 10 Dec 2020 16:27:00 +0100 Subject: [PATCH 02/24] arm64: dts: renesas: rcar-gen3: Add missing TMU nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device nodes for the Timer Unit (TMU) on the Renesas R-Car H3 (r8a77951), M3-W (r8a77960), M3-W+ (r8a77961), M3-N (r8a77965), E3 (r8a77990), and D3 (r8a77995) SoCs. Signed-off-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201210152705.1535156-2-niklas.soderlund+renesas@ragnatech.se [geert: squashed six commits] Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 65 +++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 65 +++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 65 +++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 65 +++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 65 +++++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 65 +++++++++++++++++++++++ 6 files changed, 390 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 9d60bcf69e4f..5c39152e4570 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -616,6 +616,71 @@ intc_ex: interrupt-controller@e61c0000 { resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7795", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a7795", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a7795", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a7795", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a7795", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 53b9aa26c9b1..25d947a81b29 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -585,6 +585,71 @@ intc_ex: interrupt-controller@e61c0000 { resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a7796", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 4b5b242d5b25..e8c31ebec097 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -565,6 +565,71 @@ intc_ex: interrupt-controller@e61c0000 { /* placeholder */ }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a77961", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a77961", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a77961", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a77961", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a77961", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4a913df17b1d..657b20d3533b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -455,6 +455,71 @@ intc_ex: interrupt-controller@e61c0000 { resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a77965", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a77965", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a77965", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a77965", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a77965", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 87d41bc076a9..5010f23fafcc 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -420,6 +420,71 @@ intc_ex: interrupt-controller@e61c0000 { resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a77990", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a77990", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a77990", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a77990", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a77990", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index aca0b2d015cf..2319271c881b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -312,6 +312,71 @@ intc_ex: interrupt-controller@e61c0000 { resets = <&cpg 407>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a77995", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a77995", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a77995", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a77995", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a77995", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; From db030c5a9658846a42fbed4d43a8b5f28a2d7ab7 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:42 -0600 Subject: [PATCH 03/24] arm64: dts: renesas: beacon kit: Fix choppy Bluetooth Audio The Bluetooth chip is capable of operating at 4Mbps, but the max-speed setting was on the UART node instead of the Bluetooth node, so the chip didn't operate at the correct speed resulting in choppy audio. Fix this by setting the max-speed in the proper node. Fixes: a1d8a344f1ca ("arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit") Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-3-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 8ac167aa18f0..b93219a95afc 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -89,7 +89,6 @@ &hscif0 { pinctrl-names = "default"; uart-has-rtscts; status = "okay"; - max-speed = <4000000>; bluetooth { compatible = "brcm,bcm43438-bt"; @@ -98,6 +97,7 @@ bluetooth { device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>; clocks = <&osc_32k>; clock-names = "extclk"; + max-speed = <4000000>; }; }; From ac817b5a084dc8005266a748de33eedcbb772e04 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:43 -0600 Subject: [PATCH 04/24] arm64: dts: renesas: beacon kit: Remove unnecessary nodes VSPI0 and VSPB are already enabled by default. There is no need to add extra nodes to enable them. Remove the redundant nodes. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-4-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index b93219a95afc..2a5e95ec9965 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -303,11 +303,3 @@ &usb_extal_clk { &usb3s0_clk { clock-frequency = <100000000>; }; - -&vspb { - status = "okay"; -}; - -&vspi0 { - status = "okay"; -}; From 5a5da0b758b327b727c5392d7f11e046e113a195 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:45 -0600 Subject: [PATCH 05/24] arm64: dts: renesas: beacon: Fix audio-1.8V pin enable The fact the audio worked at all was a coincidence because the wrong gpio enable was used. Use the correct GPIO pin to ensure its operation. Fixes: a1d8a344f1ca ("arm64: dts: renesas: Introduce r8a774a1-beacon-rzg2m-kit") Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-6-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index e66b5b36e489..759734b7715b 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -150,7 +150,7 @@ reg_audio: regulator_audio { regulator-name = "audio-1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&gpio_exp2 7 GPIO_ACTIVE_HIGH>; + gpio = <&gpio_exp4 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; From 012f3e37ca134da45af742a2d7971c513cb761d9 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:47 -0600 Subject: [PATCH 06/24] arm64: dts: renesas: beacon: Fix LVDS PWM Backlight The backlight didn't really work correctly due to some updates that were made in hardware. It should be safe to apply these, because the older hardware was never shipped to anyone, so it shouldn't break anything. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-8-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/beacon-renesom-baseboard.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 759734b7715b..12a9f1434983 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -10,8 +10,8 @@ / { backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; power-supply = <®_lcd>; - enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_LOW>; - pwms = <&pwm2 0 50000>; + enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>; + pwms = <&pwm2 0 25000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; }; @@ -118,9 +118,9 @@ panel-timing { hback-porch = <40>; vfront-porch = <13>; vback-porch = <29>; - vsync-len = <3>; + vsync-len = <1>; hsync-active = <1>; - vsync-active = <1>; + vsync-active = <3>; de-active = <1>; pixelclk-active = <0>; }; @@ -541,7 +541,7 @@ pwm0_pins: pwm0 { pwm2_pins: pwm2 { groups = "pwm2_a"; - function = "pwm2_a"; + function = "pwm2"; }; sdhi0_pins: sd0 { From 7f1cb1579808f97bd211b4ad16c82f2dc191c709 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:49 -0600 Subject: [PATCH 07/24] arm64: dts: renesas: beacon: Fix RGB Display PWM Backlight The backlight didn't really work correctly due to some updates that were made in hardware. It should be safe to apply these, because the older hardware was never shipped to anyone, so it shouldn't break anything. Because the display driver refers to the display as DPI, this also renames the backlight to use DPI for consistency. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-10-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 12a9f1434983..1ab96ecc842b 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -16,12 +16,12 @@ backlight_lvds: backlight-lvds { default-brightness-level = <6>; }; - backlight_rgb: backlight-rgb { + backlight_dpi: backlight-dpi { compatible = "pwm-backlight"; power-supply = <®_lcd>; enable-gpios = <&gpio_exp1 7 GPIO_ACTIVE_LOW>; - pwms = <&pwm0 0 50000>; - brightness-levels = <0 4 8 16 32 64 128 255>; + pwms = <&pwm0 0 25000>; + brightness-levels = <0 25 33 50 63 75 88 100>; default-brightness-level = <6>; }; @@ -135,7 +135,7 @@ panel_in: endpoint { rgb { /* Different LCD with compatible timings */ compatible = "rocktech,rk070er9427"; - backlight = <&backlight_rgb>; + backlight = <&backlight_dpi>; enable-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; power-supply = <®_lcd>; port { From a48f3c13689c65bcf4e7ff1b6a974beeeb9f48e5 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:50 -0600 Subject: [PATCH 08/24] arm64: dts: renesas: beacon: Don't make vccq_sdhi0 always on vccq_sdhi0 is referenced from sdhi0, so there is no need to force this regulator to be always-on. In theory it could help with low power modes in the future. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-11-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 1ab96ecc842b..987df78ec44e 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -200,15 +200,12 @@ sound_card { vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; - regulator-name = "SDHI0 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; - regulator-always-on; }; /* External DU dot clocks */ From 7e0fac6a0da54557230ac3898688f37392404cdf Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:53 -0600 Subject: [PATCH 09/24] arm64: dts: renesas: beacon: Enable SPI The baseboard routes the SPI to a header which can/will be configured at either the kit level or using device tree overlays. Because the baseboard be supporting more than one kit, enable at the baseboard level rather than a bunch of duplicates later. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-14-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/beacon-renesom-baseboard.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 987df78ec44e..cb316e736364 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -478,6 +478,13 @@ lvds0_out: endpoint { }; }; +&msiof1 { + pinctrl-0 = <&msiof1_pins>; + pinctrl-names = "default"; + status = "okay"; + cs-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; +}; + &ohci0 { dr_mode = "otg"; status = "okay"; @@ -531,6 +538,11 @@ led_pins: leds { bias-pull-down; }; + msiof1_pins: msiof1 { + groups = "msiof1_clk_g", "msiof1_rxd_g", "msiof1_txd_g"; + function = "msiof1"; + }; + pwm0_pins: pwm0 { groups = "pwm0"; function = "pwm0"; From 900d9fc3becefd050bf54c1b98e368ce6463580e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 13 Dec 2020 12:37:54 -0600 Subject: [PATCH 10/24] arm64: dts: renesas: beacon: Correct I2C bus speeds For greater compatibility with upcoming kits that will reuse the baseboard and SOM-level files, adjust the I2C speeds to make it the most compatible with all devices. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201213183759.223246-15-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 2 +- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index cb316e736364..9db120ccb58d 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -339,7 +339,7 @@ &hsusb { &i2c2 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 2a5e95ec9965..b475de38ace8 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -109,7 +109,7 @@ &hscif2 { &i2c4 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; pca9654: gpio@20 { compatible = "onnn,pca9654"; From f4b30c0a03a9edb3e70cbd7abe65fc6c3033fb20 Mon Sep 17 00:00:00 2001 From: Hoang Vo Date: Fri, 18 Dec 2020 18:37:28 +0100 Subject: [PATCH 11/24] arm64: dts: renesas: r8a779a0: Add RWDT node Add a device node for the Watchdog Timer (WDT) controller on the R8A779A0 SoC. Signed-off-by: Hoang Vo [wsa: rebased to mainline] Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20201218173731.12839-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 6cf77ce9aa93..f951e6b6f696 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -70,6 +70,16 @@ soc: soc { #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779a0-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779a0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; From d207dc500bbcf8c6e1cbad375b08904f984f9602 Mon Sep 17 00:00:00 2001 From: Hoang Vo Date: Fri, 18 Dec 2020 18:37:29 +0100 Subject: [PATCH 12/24] arm64: dts: renesas: falcon: Enable watchdog timer Enable the watchdog on the Falcon board. Signed-off-by: Hoang Vo [wsa: rebased to mainline] Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20201218173731.12839-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index 8eda70e5a82b..fb9978ea18f4 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -20,3 +20,8 @@ chosen { stdout-path = "serial0:115200n8"; }; }; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; From fe82bb4db5339ebe8175b0ff2d45757472c0415e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 24 Dec 2020 11:04:54 -0600 Subject: [PATCH 13/24] arm64: dts: renesas: beacon: Configure programmable clocks When the board was added, clock drivers were being updated done at the same time to allow the versaclock driver to properly configure the modes. Unfortunately, the updates were not applied to the board files at the time they should have been, so do it now. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201224170502.2254683-1-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/beacon-renesom-baseboard.dtsi | 27 ++++++++++++++++++- .../boot/dts/renesas/beacon-renesom-som.dtsi | 26 ++++++++++++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 9db120ccb58d..c788f294cb09 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { backlight_lvds: backlight-lvds { @@ -370,12 +371,36 @@ versaclock6_bb: clock-controller@6a { #clock-cells = <1>; clocks = <&x304_clk>; clock-names = "xin"; - /* CSI0_MCLK, CSI1_MCLK, AUDIO_CLKIN, USB_HUB_MCLK_BB */ + assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, <&versaclock6_bb 3>, <&versaclock6_bb 4>; assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>; + + OUT1 { + idt,mode = ; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT2 { + idt,mode = ; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT3 { + idt,mode = ; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; + + OUT4 { + idt,mode = ; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; }; }; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index b475de38ace8..6e74c391860c 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { memory@48000000 { @@ -170,7 +171,32 @@ versaclock5: versaclock_som@6a { <&versaclock5 2>, <&versaclock5 3>, <&versaclock5 4>; + assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>; + + OUT1 { + idt,mode = ; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT2 { + idt,mode = ; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT3 { + idt,mode = ; + idt,voltage-microvolt = <1800000>; + idt,slew-percent = <100>; + }; + + OUT4 { + idt,mode = ; + idt,voltage-microvolt = <3300000>; + idt,slew-percent = <100>; + }; }; }; From b29120d6cfa978ae0721af855afbae3137c8e66d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 24 Dec 2020 11:04:55 -0600 Subject: [PATCH 14/24] arm64: dts: renesas: beacon kit: Fix Audio Clock sources The SoC was expecting two clock sources with different frequencies. One to support 44.1KHz and one to support 48KHz. With the newly added ability to configure the programmable clock, configure both clocks. Assign the rcar-sound clocks to reference the versaclock instead of the fixed clock. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201224170502.2254683-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/beacon-renesom-baseboard.dtsi | 25 +------------------ .../dts/renesas/r8a774a1-beacon-rzg2m-kit.dts | 21 ++++++++++++++++ 2 files changed, 22 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index c788f294cb09..e66e302bdccb 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -246,12 +246,6 @@ ss_ep: endpoint { }; }; -&audio_clk_a { - clock-frequency = <24576000>; - assigned-clocks = <&versaclock6_bb 4>; - assigned-clock-rates = <24576000>; -}; - &audio_clk_b { clock-frequency = <22579200>; }; @@ -596,7 +590,7 @@ sound_pins: sound { }; sound_clk_pins: sound_clk { - groups = "audio_clk_a_a"; + groups = "audio_clk_a_a", "audio_clk_b_a"; function = "audio_clk"; }; @@ -647,23 +641,6 @@ &rcar_sound { status = "okay"; - clocks = <&cpg CPG_MOD 1005>, - <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, - <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, - <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, - <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, - <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, - <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, - <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, - <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, - <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, - <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, - <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, - <&cpg CPG_CORE R8A774A1_CLK_S0D4>; - ports { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts index 2c5b057c30c6..25eeac411f12 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts @@ -27,3 +27,24 @@ chosen { stdout-path = "serial0:115200n8"; }; }; + +/* Reference versaclock instead of audio_clk_a */ +&rcar_sound { + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774A1_CLK_S0D4>; +}; From dc3dba98d2d31420a263b726e5c0a25aa7122e85 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 24 Dec 2020 11:04:56 -0600 Subject: [PATCH 15/24] arm64: dts: renesas: beacon: Configure Audio CODEC clocks With the newly added configurable clock options, the audio CODEC can configure the mclk automatically. Add the reference to the versaclock. Since the devices on I2C5 can communicate at 400KHz, let's also increase that too Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201224170502.2254683-3-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index e66e302bdccb..b31a28239fcb 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -408,13 +408,14 @@ &i2c0 { &i2c5 { status = "okay"; - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c5_pins>; pinctrl-names = "default"; codec: wm8962@1a { compatible = "wlf,wm8962"; reg = <0x1a>; + clocks = <&versaclock6_bb 3>; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; From e718d563750db293e84f826be9e7ab49d8e4b97e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 24 Dec 2020 11:04:57 -0600 Subject: [PATCH 16/24] arm64: dts: renesas: beacon: Better describe keys The keys on the baseboard are laid out in an diamond pattern, up, down, left, right and center. Update the descriptions to make it easier to read. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201224170502.2254683-4-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/beacon-renesom-baseboard.dtsi | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index b31a28239fcb..ae0f58eb2be8 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -40,38 +40,38 @@ hdmi0_con: endpoint { keys { compatible = "gpio-keys"; - key-1 { + key-1 { /* S19 */ gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-1"; + linux,code = ; + label = "Up"; wakeup-source; debounce-interval = <20>; }; - key-2 { + key-2 { /*S20 */ gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-2"; + linux,code = ; + label = "Left"; wakeup-source; debounce-interval = <20>; }; - key-3 { + key-3 { /* S21 */ gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-3"; + linux,code = ; + label = "Down"; wakeup-source; debounce-interval = <20>; }; - key-4 { + key-4 { /* S22 */ gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-4"; + linux,code = ; + label = "Right"; wakeup-source; debounce-interval = <20>; }; - key-5 { + key-5 { /* S23 */ gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "Switch-4"; + linux,code = ; + label = "Center"; wakeup-source; debounce-interval = <20>; }; From 33aaab6d5c634784ecf5612e7ac11346adac8d6b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 24 Dec 2020 11:04:59 -0600 Subject: [PATCH 17/24] arm64: dts: renesas: beacon-rzg2m-kit: Rearrange SoC unique functions In preparation for adding new dev kits, move anything specific to the RZ/G2M from the SOM-level and baseboard-levels and move them to the kit-level. This allows the SOM and baseboard to be reused with other SoC's. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201224170502.2254683-6-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/beacon-renesom-baseboard.dtsi | 15 -------------- .../boot/dts/renesas/beacon-renesom-som.dtsi | 5 ----- .../dts/renesas/r8a774a1-beacon-rzg2m-kit.dts | 20 +++++++++++++++++++ 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index ae0f58eb2be8..30c169b08536 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -264,21 +264,6 @@ &can1 { status = "okay"; }; -&du { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - status = "okay"; - - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&versaclock5 1>, - <&x302_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", - "dclkin.0", "dclkin.1", "dclkin.2"; -}; - &du_out_rgb { remote-endpoint = <&rgb_panel>; }; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 6e74c391860c..f4201e1c2226 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -13,11 +13,6 @@ memory@48000000 { reg = <0x0 0x48000000 0x0 0x78000000>; }; - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x80000000>; - }; - osc_32k: osc_32k { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts index 25eeac411f12..501cb05da228 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts @@ -26,6 +26,26 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.2", + "dclkin.0", "dclkin.1", "dclkin.2"; }; /* Reference versaclock instead of audio_clk_a */ From ed6ae131b0e88260d593fb3f02561de25ffc1045 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 24 Dec 2020 11:05:00 -0600 Subject: [PATCH 18/24] arm64: dts: renesas: r8a774b1: Introduce beacon-rzg2n-kit Beacon EmbeddedWorks is introducing a new kit based on the RZ/G2N SoC from Renesas. The SOM supports eMMC, WiFi and Bluetooth, along with a Cat-M1 cellular radio. The Baseboard has Ethernet, USB, HDMI, stereo audio in and out, along with a variety of push buttons and LED's, and support for a parallel RGB and an LVDS display. It uses the same baseboard and SOM as the RZ/G2M. This SOM has only 2GB of DDR, and beacon-renesom-som.dtsi contains the base memory node, so an additional memory node isn't necessary. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201224170502.2254683-7-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../dts/renesas/r8a774b1-beacon-rzg2n-kit.dts | 66 +++++++++++++++++++ 2 files changed, 67 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 3b8b03705917..ea3d7d9bc52e 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-beacon-rzg2n-kit.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts new file mode 100644 index 000000000000..71763f4402a7 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "r8a774b1.dtsi" +#include "beacon-renesom-som.dtsi" +#include "beacon-renesom-baseboard.dtsi" + +/ { + model = "Beacon Embedded Works RZ/G2N Development Kit"; + compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; + + aliases { + serial0 = &scif2; + serial1 = &hscif0; + serial2 = &hscif1; + serial3 = &scif0; + serial4 = &hscif2; + serial5 = &scif5; + serial6 = &scif4; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +/* Reference versaclock instead of audio_clk_a */ +&rcar_sound { + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774B1_CLK_S0D4>; +}; From 4d0e87eb6f54422418a2d985433866535856b6bd Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 24 Dec 2020 11:05:01 -0600 Subject: [PATCH 19/24] arm64: dts: renesas: r8a774e1: Introduce beacon-rzg2h-kit Beacon EmbeddedWorks is introducing a new kit based on the RZ/G2H SoC from Renesas. The SOM supports eMMC, WiFi and Bluetooth, along with a Cat-M1 cellular radio. The Baseboard has Ethernet, USB, HDMI, stereo audio in and out, along with a variety of push buttons and LED's, and support for a parallel RGB and an LVDS display. It uses the same baseboard and SOM files as the RZ/G2M and RZ/G2N kits. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201224170502.2254683-8-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../dts/renesas/r8a774e1-beacon-rzg2h-kit.dts | 71 +++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index ea3d7d9bc52e..f2de2fa0c8b8 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874.dtb dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-idk-2121wr.dtb dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb +dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-beacon-rzg2h-kit.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts new file mode 100644 index 000000000000..273f062f2909 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020, Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "r8a774e1.dtsi" +#include "beacon-renesom-som.dtsi" +#include "beacon-renesom-baseboard.dtsi" + +/ { + model = "Beacon Embedded Works RZ/G2H Development Kit"; + compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; + + aliases { + serial0 = &scif2; + serial1 = &hscif0; + serial2 = &hscif1; + serial3 = &scif0; + serial4 = &hscif2; + serial5 = &scif5; + serial6 = &scif4; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x80000000>; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x302_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +/* Reference versaclock instead of audio_clk_a */ +&rcar_sound { + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&versaclock6_bb 4>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774E1_CLK_S0D4>; +}; From e1076ce07b7736aed269c5d8154f2442970d9137 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 28 Dec 2020 14:22:21 -0600 Subject: [PATCH 20/24] arm64: dts: renesas: rzg2: Add usb2_clksel to RZ/G2 M/N/H Per the reference manual for the RZ/G Series, 2nd Generation, the RZ/G2M, RZ/G2N, and RZ/G2H have a bit that can be set to choose between a crystal oscillator and an external oscillator. Because only boards that need this should enable it, it's marked as disabled by default for backwards compatibility with existing boards. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20201228202221.2327468-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 15 +++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index d37ec42a1caa..60e150320ce8 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -835,6 +835,21 @@ hsusb: usb@e6590000 { status = "disabled"; }; + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a774a1-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0 0xe6590630 0 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal_clk>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a774a1-usb-dmac", "renesas,usb-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 83523916d360..20003a41a706 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -709,6 +709,21 @@ hsusb: usb@e6590000 { status = "disabled"; }; + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a774b1-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0 0xe6590630 0 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal_clk>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a774b1-usb-dmac", "renesas,usb-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 1333b02d623a..2e6c12a46daf 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -890,6 +890,21 @@ hsusb: usb@e6590000 { status = "disabled"; }; + usb2_clksel: clock-controller@e6590630 { + compatible = "renesas,r8a774e1-rcar-usb2-clock-sel", + "renesas,rcar-gen3-usb2-clock-sel"; + reg = <0 0xe6590630 0 0x02>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, + <&usb_extal_clk>, <&usb3s0_clk>; + clock-names = "ehci_ohci", "hs-usb-if", + "usb_extal", "usb_xtal"; + #clock-cells = <0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + reset-names = "ehci_ohci", "hs-usb-if"; + status = "disabled"; + }; + usb_dmac0: dma-controller@e65a0000 { compatible = "renesas,r8a774e1-usb-dmac", "renesas,usb-dmac"; From 8811955d0a6d0abfa3e1c0cee30090fda0015069 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 2 Jan 2021 05:54:12 -0600 Subject: [PATCH 21/24] arm64: dts: renesas: rzg2: Add RPC-IF Support The RZ/G2 series contain the SPI Multi I/O Bus Controller (RPC-IF). Add the nodes, but make them disabled by default. Signed-off-by: Adam Ford Link: https://lore.kernel.org/r/20210102115412.3402059-4-aford173@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 17 +++++++++++++++++ 4 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 60e150320ce8..d64fb8b1b86c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2317,6 +2317,23 @@ sdhi3: mmc@ee160000 { status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774a1-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 20003a41a706..5b05474dc272 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2175,6 +2175,23 @@ sdhi3: mmc@ee160000 { status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774b1-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a774b1", "renesas,rcar-gen3-sata"; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index e0e54342cd4c..20fa3caa050e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1654,6 +1654,23 @@ sdhi3: mmc@ee160000 { status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774c0-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 2e6c12a46daf..8eb006cbd9af 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2408,6 +2408,23 @@ sdhi3: mmc@ee160000 { status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a774e1-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x4000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + clock-names = "rpc"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a774e1", "renesas,rcar-gen3-sata"; From 73feebad9e056cfe5f444acd5b61f3d0d5ec74bb Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Tue, 12 Jan 2021 17:59:48 +0100 Subject: [PATCH 22/24] arm64: dts: renesas: r8a779a0: Add pinctrl device node This patch adds the pinctrl device node for the R8A779A0 (V3U) SoC. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20210112165948.31162-1-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f951e6b6f696..6ac2c9d37acd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -80,6 +80,15 @@ rwdt: watchdog@e6020000 { status = "disabled"; }; + pfc: pin-controller@e6050000 { + compatible = "renesas,pfc-r8a779a0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, + <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, + <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, + <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779a0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; From dfacaef96cbf871be23b4e2613818a9658f23817 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 14 Jan 2021 12:11:17 +0100 Subject: [PATCH 23/24] arm64: dts: renesas: r8a779a0: Add GPIO nodes Add device nodes for the General Purpose Input/Output (GPIO) block on the Renesas R-Car V3U (r8a779a0) SoC. Signed-off-by: Geert Uytterhoeven Tested-by: Wolfram Sang Link: https://lore.kernel.org/r/20210114111117.2214281-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 140 ++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 6ac2c9d37acd..66b47a848443 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -89,6 +89,146 @@ pfc: pin-controller@e6050000 { <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; }; + gpio0: gpio@e6058180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6058180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 28>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6050180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 31>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6050980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6050980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6058980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6058980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 916>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 17>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@e6060180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6060180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 128 27>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@e6060980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6060980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 917>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 160 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@e6068180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6068180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 192 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@e6068980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6068980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 224 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio8: gpio@e6069180 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6069180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 256 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio9: gpio@e6069980 { + compatible = "renesas,gpio-r8a779a0"; + reg = <0 0xe6069980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 918>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 288 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779a0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; From 1f4449e12c5c6682a6f4f8dbc7288c19c1c844f1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 Jan 2021 19:20:45 +0100 Subject: [PATCH 24/24] arm64: dts: renesas: r8a779a0: Add SYS-DMAC nodes Add device nodes for the Direct Memory Access Controller for System (SYS-DMAC) instances on the Renesas R-Car V3U (r8a779a0) SoC. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20210107182045.1948037-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 66b47a848443..3bc15592d000 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -264,6 +264,64 @@ scif0: serial@e6e60000 { status = "disabled"; }; + dmac1: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779a0"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779a0"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <8>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;