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arm64: Sort registers in cpu-feature-registers.rst
In order to make it a bit easier to work with sort the list of registers in cpu-feature-registers.rst lexically. There should be no content changes resulting from this patch. Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Mark Brown
Will Deacon
parent
4788adeca0
commit
21a2ca869e
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@ -170,6 +170,108 @@ infrastructure:
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+------------------------------+---------+---------+
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ID_AA64ISAR1_EL1 - Instruction set attribute register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| LS64 | [63-60] | y |
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+------------------------------+---------+---------+
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| I8MM | [55-52] | y |
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+------------------------------+---------+---------+
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| DGH | [51-48] | y |
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+------------------------------+---------+---------+
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| BF16 | [47-44] | y |
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+------------------------------+---------+---------+
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| SB | [39-36] | y |
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+------------------------------+---------+---------+
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| FRINTTS | [35-32] | y |
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+------------------------------+---------+---------+
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| GPI | [31-28] | y |
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+------------------------------+---------+---------+
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| GPA | [27-24] | y |
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+------------------------------+---------+---------+
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| LRCPC | [23-20] | y |
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+------------------------------+---------+---------+
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| FCMA | [19-16] | y |
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+------------------------------+---------+---------+
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| JSCVT | [15-12] | y |
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+------------------------------+---------+---------+
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| API | [11-8] | y |
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+------------------------------+---------+---------+
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| APA | [7-4] | y |
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+------------------------------+---------+---------+
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| DPB | [3-0] | y |
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+------------------------------+---------+---------+
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ID_AA64ISAR2_EL1 - Instruction set attribute register 2
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| LUT | [59-56] | y |
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+------------------------------+---------+---------+
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| CSSC | [55-52] | y |
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+------------------------------+---------+---------+
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| RPRFM | [51-48] | y |
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+------------------------------+---------+---------+
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| BC | [23-20] | y |
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+------------------------------+---------+---------+
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| MOPS | [19-16] | y |
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+------------------------------+---------+---------+
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| APA3 | [15-12] | y |
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+------------------------------+---------+---------+
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| GPA3 | [11-8] | y |
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+------------------------------+---------+---------+
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| RPRES | [7-4] | y |
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+------------------------------+---------+---------+
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| WFXT | [3-0] | y |
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+------------------------------+---------+---------+
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ID_AA64ISAR3_EL1 - Instruction set attribute register 3
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| FPRCVT | [31-28] | y |
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+------------------------------+---------+---------+
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| LSFE | [19-16] | y |
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+------------------------------+---------+---------+
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| FAMINMAX | [7-4] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR0_EL1 - Memory model feature register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| ECV | [63-60] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR1_EL1 - Memory model feature register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| AFP | [47-44] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR2_EL1 - Memory model feature register 2
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| AT | [35-32] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR3_EL1 - Memory model feature register 3
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| S1POE | [19-16] | y |
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+------------------------------+---------+---------+
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ID_AA64PFR0_EL1 - Processor Feature Register 0
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+------------------------------+---------+---------+
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@ -225,84 +327,6 @@ infrastructure:
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| MTESTOREONLY | [7-4] | y |
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+------------------------------+---------+---------+
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MIDR_EL1 - Main ID Register
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| Implementer | [31-24] | y |
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+------------------------------+---------+---------+
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| Variant | [23-20] | y |
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+------------------------------+---------+---------+
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| Architecture | [19-16] | y |
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+------------------------------+---------+---------+
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| PartNum | [15-4] | y |
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+------------------------------+---------+---------+
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| Revision | [3-0] | y |
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+------------------------------+---------+---------+
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NOTE: The 'visible' fields of MIDR_EL1 will contain the value
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as available on the CPU where it is fetched and is not a system
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wide safe value.
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ID_AA64ISAR1_EL1 - Instruction set attribute register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| LS64 | [63-60] | y |
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+------------------------------+---------+---------+
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| I8MM | [55-52] | y |
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+------------------------------+---------+---------+
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| DGH | [51-48] | y |
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+------------------------------+---------+---------+
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| BF16 | [47-44] | y |
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+------------------------------+---------+---------+
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| SB | [39-36] | y |
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+------------------------------+---------+---------+
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| FRINTTS | [35-32] | y |
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+------------------------------+---------+---------+
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| GPI | [31-28] | y |
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+------------------------------+---------+---------+
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| GPA | [27-24] | y |
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+------------------------------+---------+---------+
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| LRCPC | [23-20] | y |
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+------------------------------+---------+---------+
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| FCMA | [19-16] | y |
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+------------------------------+---------+---------+
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| JSCVT | [15-12] | y |
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+------------------------------+---------+---------+
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| API | [11-8] | y |
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+------------------------------+---------+---------+
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| APA | [7-4] | y |
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+------------------------------+---------+---------+
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| DPB | [3-0] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR0_EL1 - Memory model feature register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| ECV | [63-60] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR2_EL1 - Memory model feature register 2
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| AT | [35-32] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR3_EL1 - Memory model feature register 3
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| S1POE | [19-16] | y |
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+------------------------------+---------+---------+
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ID_AA64SMFR0_EL1 - SME feature ID register 0
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+------------------------------+---------+---------+
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@ -387,76 +411,6 @@ infrastructure:
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| SVEVer | [3-0] | y |
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+------------------------------+---------+---------+
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ID_AA64MMFR1_EL1 - Memory model feature register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| AFP | [47-44] | y |
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+------------------------------+---------+---------+
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ID_AA64ISAR2_EL1 - Instruction set attribute register 2
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| LUT | [59-56] | y |
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+------------------------------+---------+---------+
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| CSSC | [55-52] | y |
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+------------------------------+---------+---------+
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| RPRFM | [51-48] | y |
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+------------------------------+---------+---------+
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| BC | [23-20] | y |
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+------------------------------+---------+---------+
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| MOPS | [19-16] | y |
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+------------------------------+---------+---------+
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| APA3 | [15-12] | y |
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+------------------------------+---------+---------+
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| GPA3 | [11-8] | y |
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+------------------------------+---------+---------+
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| RPRES | [7-4] | y |
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+------------------------------+---------+---------+
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| WFXT | [3-0] | y |
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+------------------------------+---------+---------+
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ID_AA64ISAR3_EL1 - Instruction set attribute register 3
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| FPRCVT | [31-28] | y |
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+------------------------------+---------+---------+
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| LSFE | [19-16] | y |
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+------------------------------+---------+---------+
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| FAMINMAX | [7-4] | y |
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+------------------------------+---------+---------+
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MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| FPDP | [11-8] | y |
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+------------------------------+---------+---------+
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MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| SIMDFMAC | [31-28] | y |
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+------------------------------+---------+---------+
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| FPHP | [27-24] | y |
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+------------------------------+---------+---------+
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| SIMDHP | [23-20] | y |
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+------------------------------+---------+---------+
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| SIMDSP | [19-16] | y |
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+------------------------------+---------+---------+
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| SIMDInt | [15-12] | y |
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+------------------------------+---------+---------+
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| SIMDLS | [11-8] | y |
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+------------------------------+---------+---------+
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ID_ISAR5_EL1 - AArch32 Instruction Set Attribute Register 5
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+------------------------------+---------+---------+
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@ -495,6 +449,53 @@ infrastructure:
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| SSBS | [7-4] | y |
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+------------------------------+---------+---------+
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MIDR_EL1 - Main ID Register
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| Implementer | [31-24] | y |
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+------------------------------+---------+---------+
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| Variant | [23-20] | y |
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+------------------------------+---------+---------+
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| Architecture | [19-16] | y |
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+------------------------------+---------+---------+
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| PartNum | [15-4] | y |
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+------------------------------+---------+---------+
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| Revision | [3-0] | y |
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+------------------------------+---------+---------+
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NOTE: The 'visible' fields of MIDR_EL1 will contain the value
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as available on the CPU where it is fetched and is not a system
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wide safe value.
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MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| FPDP | [11-8] | y |
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+------------------------------+---------+---------+
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MVFR1_EL1 - AArch32 Media and VFP Feature Register 1
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+------------------------------+---------+---------+
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| Name | bits | visible |
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+------------------------------+---------+---------+
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| SIMDFMAC | [31-28] | y |
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+------------------------------+---------+---------+
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| FPHP | [27-24] | y |
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+------------------------------+---------+---------+
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| SIMDHP | [23-20] | y |
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+------------------------------+---------+---------+
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| SIMDSP | [19-16] | y |
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+------------------------------+---------+---------+
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| SIMDInt | [15-12] | y |
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+------------------------------+---------+---------+
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| SIMDLS | [11-8] | y |
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+------------------------------+---------+---------+
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Appendix I: Example
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-------------------
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Reference in New Issue
Block a user