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arm64: Document missing bitfields in cpu-feature-registers.rst

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We have been rather lax in updating the list of visible bitfields in the
ID registers in cpu-feature-registers.rst, it is currently missing several
of the registers and quite a few bitfields in existing registers. Bring it
into sync with current -next.

Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Mark Brown 2026-07-02 20:11:17 +01:00 committed by Will Deacon
parent b6bd4d1a5b
commit 4788adeca0
1 changed files with 146 additions and 0 deletions
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146
Documentation/arch/arm64/cpu-feature-registers.rst
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@ -113,6 +113,30 @@ infrastructure:
4. List of registers with visible features
-------------------------------------------
ID_AA64FPFR0_EL1 - Floating Point feature ID register 0
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| F8CVT | [31] | y |
+------------------------------+---------+---------+
| F8FMA | [30] | y |
+------------------------------+---------+---------+
| F8DP4 | [29] | y |
+------------------------------+---------+---------+
| F8DP2 | [28] | y |
+------------------------------+---------+---------+
| F8MM8 | [27] | y |
+------------------------------+---------+---------+
| F8MM4 | [26] | y |
+------------------------------+---------+---------+
| F16MM2 | [15] | y |
+------------------------------+---------+---------+
| F8E4M3 | [1] | y |
+------------------------------+---------+---------+
| F8E5M2 | [0] | y |
+------------------------------+---------+---------+
ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
+------------------------------+---------+---------+
@ -178,6 +202,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| GCS | [47-44] | y |
+------------------------------+---------+---------+
| SME | [27-24] | y |
+------------------------------+---------+---------+
| MTE | [11-8] | y |
@ -187,6 +213,17 @@ infrastructure:
| BT | [3-0] | y |
+------------------------------+---------+---------+
ID_AA64PFR2_EL1 - Processor Feature Register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| FPMR | [35-32] | y |
+------------------------------+---------+---------+
| MTEFAR | [11-8] | y |
+------------------------------+---------+---------+
| MTESTOREONLY | [7-4] | y |
+------------------------------+---------+---------+
MIDR_EL1 - Main ID Register
@ -213,6 +250,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| LS64 | [63-60] | y |
+------------------------------+---------+---------+
| I8MM | [55-52] | y |
+------------------------------+---------+---------+
| DGH | [51-48] | y |
@ -256,6 +295,68 @@ infrastructure:
| AT | [35-32] | y |
+------------------------------+---------+---------+
ID_AA64MMFR3_EL1 - Memory model feature register 3
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| S1POE | [19-16] | y |
+------------------------------+---------+---------+
ID_AA64SMFR0_EL1 - SME feature ID register 0
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| FA64 | [63] | y |
+------------------------------+---------+---------+
| LUT6 | [61] | y |
+------------------------------+---------+---------+
| LUTv2 | [60] | y |
+------------------------------+---------+---------+
| SMEver | [59-56] | y |
+------------------------------+---------+---------+
| I16I64 | [55-52] | y |
+------------------------------+---------+---------+
| F64F64 | [48] | y |
+------------------------------+---------+---------+
| I16I32 | [47-44] | y |
+------------------------------+---------+---------+
| B16B16 | [43] | y |
+------------------------------+---------+---------+
| F16F16 | [42] | y |
+------------------------------+---------+---------+
| F8F16 | [41] | y |
+------------------------------+---------+---------+
| F8F32 | [40] | y |
+------------------------------+---------+---------+
| I8I32 | [39-36] | y |
+------------------------------+---------+---------+
| F16F32 | [35] | y |
+------------------------------+---------+---------+
| B16F32 | [34] | y |
+------------------------------+---------+---------+
| BI32I32 | [33] | y |
+------------------------------+---------+---------+
| F32F32 | [32] | y |
+------------------------------+---------+---------+
| SF8FMA | [30] | y |
+------------------------------+---------+---------+
| SF8DP4 | [29] | y |
+------------------------------+---------+---------+
| SF8DP2 | [28] | y |
+------------------------------+---------+---------+
| SBitPerm | [25] | y |
+------------------------------+---------+---------+
| AES | [24] | y |
+------------------------------+---------+---------+
| SFEXPA | [23] | y |
+------------------------------+---------+---------+
| STMOP | [16] | y |
+------------------------------+---------+---------+
| SMOP4 | [0] | y |
+------------------------------+---------+---------+
ID_AA64ZFR0_EL1 - SVE feature ID register 0
+------------------------------+---------+---------+
@ -265,6 +366,8 @@ infrastructure:
+------------------------------+---------+---------+
| F32MM | [55-52] | y |
+------------------------------+---------+---------+
| F16MM | [51-48] | y |
+------------------------------+---------+---------+
| I8MM | [47-44] | y |
+------------------------------+---------+---------+
| SM4 | [43-40] | y |
@ -277,6 +380,8 @@ infrastructure:
+------------------------------+---------+---------+
| BitPerm | [19-16] | y |
+------------------------------+---------+---------+
| EltPerm | [15-12] | y |
+------------------------------+---------+---------+
| AES | [7-4] | y |
+------------------------------+---------+---------+
| SVEVer | [3-0] | y |
@ -295,6 +400,8 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| LUT | [59-56] | y |
+------------------------------+---------+---------+
| CSSC | [55-52] | y |
+------------------------------+---------+---------+
| RPRFM | [51-48] | y |
@ -312,6 +419,18 @@ infrastructure:
| WFXT | [3-0] | y |
+------------------------------+---------+---------+
ID_AA64ISAR3_EL1 - Instruction set attribute register 3
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| FPRCVT | [31-28] | y |
+------------------------------+---------+---------+
| LSFE | [19-16] | y |
+------------------------------+---------+---------+
| FAMINMAX | [7-4] | y |
+------------------------------+---------+---------+
MVFR0_EL1 - AArch32 Media and VFP Feature Register 0
+------------------------------+---------+---------+
@ -327,6 +446,10 @@ infrastructure:
+------------------------------+---------+---------+
| SIMDFMAC | [31-28] | y |
+------------------------------+---------+---------+
| FPHP | [27-24] | y |
+------------------------------+---------+---------+
| SIMDHP | [23-20] | y |
+------------------------------+---------+---------+
| SIMDSP | [19-16] | y |
+------------------------------+---------+---------+
| SIMDInt | [15-12] | y |
@ -348,6 +471,29 @@ infrastructure:
| AES | [7-4] | y |
+------------------------------+---------+---------+
ID_ISAR6_EL1 - AArch32 Instruction Set Attribute Register 6
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| I8MM | [27-24] | y |
+------------------------------+---------+---------+
| BF16 | [23-20] | y |
+------------------------------+---------+---------+
| SB | [15-12] | y |
+------------------------------+---------+---------+
| FHM | [11-8] | y |
+------------------------------+---------+---------+
| DP | [7-4] | y |
+------------------------------+---------+---------+
ID_PFR2_EL1 - AArch32 Processor Feature Register 2
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
| SSBS | [7-4] | y |
+------------------------------+---------+---------+
Appendix I: Example
-------------------