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arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region

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This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe node.

Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-j7200-evm-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250402113201.151195-4-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Andrew Davis 2025-04-02 17:01:59 +05:30 committed by Nishanth Menon
parent df2210b2da
commit 1f326fb84a
2 changed files with 7 additions and 2 deletions
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2
arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso
View File

@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 {
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
};
};

7
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View File

@ -32,6 +32,11 @@ scm_conf: scm-conf@100000 {
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
pcie1_ctrl: pcie-ctrl@4074 {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x4074 0x4>;
};
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x4080 0x20>;
@ -764,7 +769,7 @@ pcie1_rc: pcie@2910000 {
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;