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arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region

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This region is used for controlling the function of the PCIe IP. It is
compatible with "ti,j784s4-pcie-ctrl", add this here and use it with
the PCIe nodes.

Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: Add changes to k3-j721e-evm-pcie1-ep.dtso]
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20250402113201.151195-3-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Andrew Davis 2025-04-02 17:01:58 +05:30 committed by Nishanth Menon
parent c574db0b68
commit df2210b2da
3 changed files with 26 additions and 6 deletions
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2
arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso
View File

@ -38,7 +38,7 @@ pcie0_ep: pcie-ep@2900000 {
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <1>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;

2
arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso
View File

@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 {
dma-coherent;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
};
};

28
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View File

@ -44,6 +44,26 @@ scm_conf: scm-conf@100000 {
#size-cells = <1>;
ranges = <0x0 0x0 0x00100000 0x1c000>;
pcie0_ctrl: pcie-ctrl@4070 {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x4070 0x4>;
};
pcie1_ctrl: pcie-ctrl@4074 {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x4074 0x4>;
};
pcie2_ctrl: pcie-ctrl@4078 {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x4078 0x4>;
};
pcie3_ctrl: pcie-ctrl@407c {
compatible = "ti,j784s4-pcie-ctrl", "syscon";
reg = <0x407c 0x4>;
};
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x4080 0x50>;
@ -946,7 +966,7 @@ pcie0_rc: pcie@2900000 {
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
@ -975,7 +995,7 @@ pcie1_rc: pcie@2910000 {
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
@ -1004,7 +1024,7 @@ pcie2_rc: pcie@2920000 {
interrupt-names = "link_state";
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
@ -1033,7 +1053,7 @@ pcie3_rc: pcie@2930000 {
interrupt-names = "link_state";
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
max-link-speed = <3>;
num-lanes = <2>;
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;