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drm/panel: jadard-jd9365da-h3: support Waveshare 720p DSI panels
Add configuration for Waveshare 9.0" and 10.1" 720p DSI panels using JD9365 controller. Tested-by: Riccardo Mereu <r.mereu@arduino.cc> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260413-waveshare-dsi-touch-v3-16-3aeb53022c32@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Dmitry Baryshkov
parent
5a7770a06f
commit
13414cfd48
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@ -21,6 +21,8 @@
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#include <linux/of.h>
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#include <linux/regulator/consumer.h>
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#include <video/mipi_display.h>
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struct jadard;
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struct jadard_panel_desc {
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@ -2283,6 +2285,49 @@ static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {
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MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
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};
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static int waveshare_10_1_b_init(struct jadard *jadard);
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static const struct jadard_panel_desc waveshare_9_0_inch_b_desc = {
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.mode_4ln = &(const struct drm_display_mode) {
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.clock = (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,
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.hdisplay = 720,
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.hsync_start = 720 + 60,
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.hsync_end = 720 + 60 + 60,
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.htotal = 720 + 60 + 60 + 4,
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.vdisplay = 1280,
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.vsync_start = 1280 + 16,
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.vsync_end = 1280 + 16 + 12,
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.vtotal = 1280 + 16 + 12 + 4,
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.width_mm = 114,
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.height_mm = 196,
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.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
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},
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.mode_2ln = &(const struct drm_display_mode) {
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.clock = (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,
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.hdisplay = 720,
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.hsync_start = 720 + 50,
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.hsync_end = 720 + 50 + 50,
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.htotal = 720 + 50 + 50 + 50,
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.vdisplay = 1280,
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.vsync_start = 1280 + 26,
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.vsync_end = 1280 + 26 + 12,
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.vtotal = 1280 + 26 + 12 + 4,
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.width_mm = 114,
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.height_mm = 196,
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.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
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},
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.format = MIPI_DSI_FMT_RGB888,
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.init = waveshare_10_1_b_init,
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.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
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MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
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};
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static const struct drm_display_mode waveshare_10_1_a_mode = {
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.clock = (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,
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@ -2627,6 +2672,265 @@ static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {
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MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
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};
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static int waveshare_10_1_b_init(struct jadard *jadard)
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{
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struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
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jd9365da_switch_page(&dsi_ctx, 0x00);
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jadard_enable_standard_cmds(&dsi_ctx);
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jd9365da_switch_page(&dsi_ctx, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x3f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x74);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x7e);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x24);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x38);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x65);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x52);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x44);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x2d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x14);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x28);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x25);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x23);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x3f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x2d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x34);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x27);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x24);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x18);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x65);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x52);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x44);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x2d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x14);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x28);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x25);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x23);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x3f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x2d);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x34);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x27);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x24);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x18);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);
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jd9365da_switch_page(&dsi_ctx, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x51);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x50);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x51);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x77);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x57);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x47);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x46);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x45);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x44);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x4b);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x4a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x49);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x48);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x40);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x41);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x51);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x50);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x77);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x57);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x47);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x46);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x44);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x4b);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x4a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x49);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x48);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x40);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x41);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x11);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x15);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x17);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x08);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x09);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x0b);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x05);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x06);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x07);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x11);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x10);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x11);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x15);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x17);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x08);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x09);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x0b);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x04);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x05);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x06);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x07);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x11);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x10);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x07);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x06);
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mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x66);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x55);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x13);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x06);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x66);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xe3);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x21);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x06);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x66);
|
||||
|
||||
jd9365da_switch_page(&dsi_ctx, 0x04);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);
|
||||
|
||||
jd9365da_switch_page(&dsi_ctx, 0x05);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1d);
|
||||
|
||||
jd9365da_switch_page(&dsi_ctx, 0x00);
|
||||
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
|
||||
msleep(120);
|
||||
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
|
||||
msleep(5);
|
||||
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_TEAR_ON);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct jadard_panel_desc waveshare_10_1_inch_b_desc = {
|
||||
.mode_4ln = &(const struct drm_display_mode) {
|
||||
.clock = (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,
|
||||
|
||||
.hdisplay = 720,
|
||||
.hsync_start = 720 + 60,
|
||||
.hsync_end = 720 + 60 + 60,
|
||||
.htotal = 720 + 60 + 60 + 4,
|
||||
|
||||
.vdisplay = 1280,
|
||||
.vsync_start = 1280 + 16,
|
||||
.vsync_end = 1280 + 16 + 12,
|
||||
.vtotal = 1280 + 16 + 12 + 4,
|
||||
|
||||
.width_mm = 125,
|
||||
.height_mm = 222,
|
||||
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
||||
},
|
||||
.mode_2ln = &(const struct drm_display_mode) {
|
||||
.clock = (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,
|
||||
|
||||
.hdisplay = 720,
|
||||
.hsync_start = 720 + 50,
|
||||
.hsync_end = 720 + 50 + 50,
|
||||
.htotal = 720 + 50 + 50 + 50,
|
||||
|
||||
.vdisplay = 1280,
|
||||
.vsync_start = 1280 + 26,
|
||||
.vsync_end = 1280 + 26 + 12,
|
||||
.vtotal = 1280 + 26 + 12 + 4,
|
||||
|
||||
.width_mm = 125,
|
||||
.height_mm = 222,
|
||||
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
|
||||
},
|
||||
.format = MIPI_DSI_FMT_RGB888,
|
||||
.init = waveshare_10_1_b_init,
|
||||
.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
|
||||
MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
|
||||
};
|
||||
|
||||
static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
|
||||
{
|
||||
struct device *dev = &dsi->dev;
|
||||
|
|
@ -2762,10 +3066,18 @@ static const struct of_device_id jadard_of_match[] = {
|
|||
.compatible = "waveshare,8.0-dsi-touch-a",
|
||||
.data = &waveshare_8_0_inch_a_desc
|
||||
},
|
||||
{
|
||||
.compatible = "waveshare,9.0-dsi-touch-b",
|
||||
.data = &waveshare_9_0_inch_b_desc
|
||||
},
|
||||
{
|
||||
.compatible = "waveshare,10.1-dsi-touch-a",
|
||||
.data = &waveshare_10_1_inch_a_desc
|
||||
},
|
||||
{
|
||||
.compatible = "waveshare,10.1-dsi-touch-b",
|
||||
.data = &waveshare_10_1_inch_b_desc
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, jadard_of_match);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user