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RISC-V Devicetrees for v6.17
Sophgo: For CV18xx serials: There are three major changes. The first is to add the RTCSYS MFD node, which provides rich control registers for soc power management and other rich control functions; the second is to add the reset controller node and add related reset properties for other peripherals; the third is to add ethernet controller related nodes to the soc and enable ethernet device control for HuashanPi. For SG2042: There are three major changes. The first is to add ISA extensions such as xtheadvector/ziccrse/zfh for cpu cores; the second is add ethernet controller support; the third is add two new boards EVB_V1 & EVB_V2 which use SG2042 SoC. For SG2044: There are many changes. The first is to add pmu configuration; the second is to add ISA extensions ziccrse and add missing riscv,cbop-block-size property for cpu cores; the third is to add more peripherals nodes for SoC after clock controller is ready, such as MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU device for the sophgo-srd3-10 board and reserve uart0 node for sophgo-srd3-10 board because uart0 is already occupied by the firmware. This PR also moves sophgo.yaml from the riscv directory to soc/sophgo for sharing between riscv and arm. CV18xx SoC contains a RISC-V big core and an ARM64 big core. Moving sophgo.yaml to a shared location will help us add support for ARM cores to the CV18xx chip in the future. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> -----BEGIN PGP SIGNATURE----- iQGzBAABCgAdFiEEdoBX2jyDC9ZCTwZjDCzASqG0i0IFAmiAhvwACgkQDCzASqG0 i0IyCgv/UwnfACCIfPEOH1jLNwJqP1iUmsy5zyrcwapIZJMTiOE5PpizFPwgplKq CUBZJhIsfS9VjpUsiE8fslOezNrJHXRDK8uR5MCZQe/IGm46xnoxsAKVoLnjMbLR SWBN2I20xaEDNptyWNw5PNJmEMs9PVcvutFvGdLFBTdL6X8gf21XwO3B/K/jUimE S3eck5PAnUhvIV6uBxedi16FqPB5MD/4cwMnIJnwMiwWrmim0vLYKD1L7fzUbYu6 vPRwv5JZZJg9/1QE+pgLm90dJ36J4sg5CYmRaCmgq05gyd5XXd6GSbbpChjvqrWy sUmZNKsiwA5+yZR972cc3Rjt0QKjn79v/eV/A4gSsyBRH6d3oc+KgDJl1ZttcVWu G0Yq+HcLwJnVL9A5hIMJEHSQkzLplScxzcRk94ii2vFS6uHtzd0K8fG8G47E/i6j qrMpczNHiHCijPxDIHXLdvUDmHpRSwp3isciwouvU35b+wsLHrMgEsnpGF/cmHUO kuPXLk6p =/XJ6 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiBQ18ACgkQmmx57+YA GNn9ABAAvCqpUHtM68k72FYDC4Xt312i8q1APdetj+f5vTQxNYemIkO5hTwv5Sbe GJqXcfglFtQ52+B7IazfGG+CQr7srDOAjD7DLrhuZvuF+AZRuotnEnt1fF7xvtsz EK0JqkCq1gnZJ+ZLLutotuU6708IULAEFIxszH8gedcBygdcogXKxYPWdqd6IDtB djjrHrU1caL7ioo3yEYLIIh6fDZpjUeXeWutrWVdrXi97d8YvsAypFBGjmRZw0wf yNmwuGHru4vi8woxe11r5117xV4mBHoFrkx7MvSbZmUXTN3gufbnMGenj2/DbsHJ T/fP5nijTjJUeyj2NuudKQqTbOsqmz10SE7n/E3l5vlx9rm4dayWEFufXXOrPWgx Hyd8vz151HkvzkhgokXIwiTvpSF3us0c2SmoskMeZm+gOWYw4amr4jujOHEF8yGt uDcdmnaZnys1+PMCfHHYq6nrtSy5SNV9bedasPuI5qw/Tmdx2oZ+JrI9zqP9gwrS rDVdLcChDhdxLRAPKM9jHu9mjDJWlxmG3WbjYbaTztWNKvT6tIArcIGX65VbyNDc xqFOc7wXtN2ZbXhEvAvxODdYLksUrJNRwJhNdwhD8PTbLR70VC3yCLb8UNJCVqY8 vqKzd9jl9HaujDeHfas8BPIgaIZCkYRTRWG4gXTwC+ClA3EQeZs= =up6v -----END PGP SIGNATURE----- Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt RISC-V Devicetrees for v6.17 Sophgo: For CV18xx serials: There are three major changes. The first is to add the RTCSYS MFD node, which provides rich control registers for soc power management and other rich control functions; the second is to add the reset controller node and add related reset properties for other peripherals; the third is to add ethernet controller related nodes to the soc and enable ethernet device control for HuashanPi. For SG2042: There are three major changes. The first is to add ISA extensions such as xtheadvector/ziccrse/zfh for cpu cores; the second is add ethernet controller support; the third is add two new boards EVB_V1 & EVB_V2 which use SG2042 SoC. For SG2044: There are many changes. The first is to add pmu configuration; the second is to add ISA extensions ziccrse and add missing riscv,cbop-block-size property for cpu cores; the third is to add more peripherals nodes for SoC after clock controller is ready, such as MSI/PCIe/pwm/SPI-NOR etc. This PR also add HWMON MCU device for the sophgo-srd3-10 board and reserve uart0 node for sophgo-srd3-10 board because uart0 is already occupied by the firmware. This PR also moves sophgo.yaml from the riscv directory to soc/sophgo for sharing between riscv and arm. CV18xx SoC contains a RISC-V big core and an ARM64 big core. Moving sophgo.yaml to a shared location will help us add support for ARM cores to the CV18xx chip in the future. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux: (32 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ... Link: https://lore.kernel.org/r/MAUPR01MB1107297124C9DA0CD77DA3DC1FE5FA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
11949d263a
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/sophgo.yaml#
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$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo SoC-based boards
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@ -26,6 +26,11 @@ properties:
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- enum:
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- sophgo,huashan-pi
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- const: sophgo,cv1812h
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- items:
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- enum:
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- milkv,duo-module-01-evb
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- const: milkv,duo-module-01
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- const: sophgo,sg2000
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- items:
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- enum:
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- sipeed,licheerv-nano-b
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@ -34,6 +39,8 @@ properties:
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- items:
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- enum:
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- milkv,pioneer
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- sophgo,sg2042-evb-v1
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- sophgo,sg2042-evb-v2
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- const: sophgo,sg2042
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- items:
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- enum:
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@ -3,4 +3,6 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb
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dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb
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@ -7,6 +7,7 @@
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#include <dt-bindings/clock/sophgo,cv1800.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "cv18xx-reset.h"
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/ {
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#address-cells = <1>;
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@ -24,11 +25,45 @@ soc {
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#size-cells = <1>;
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ranges;
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rst: reset-controller@3003000 {
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compatible = "sophgo,cv1800b-reset";
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reg = <0x3003000 0x1000>;
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#reset-cells = <1>;
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};
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mdio: mdio-mux@3009800 {
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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reg = <0x3009800 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio-parent-bus = <&gmac0_mdio>;
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mux-mask = <0x80>;
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status = "disabled";
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internal_mdio: mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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internal_ephy: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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external_mdio: mdio@80 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80>;
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};
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};
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gpio0: gpio@3020000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3020000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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@ -47,6 +82,7 @@ gpio1: gpio@3021000 {
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reg = <0x3021000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO1>;
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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@ -65,6 +101,7 @@ gpio2: gpio@3022000 {
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reg = <0x3022000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO2>;
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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@ -83,6 +120,7 @@ gpio3: gpio@3023000 {
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reg = <0x3023000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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resets = <&rst RST_GPIO3>;
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portd: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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@ -126,6 +164,7 @@ i2c0: i2c@4000000 {
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C0>;
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status = "disabled";
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};
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@ -137,6 +176,7 @@ i2c1: i2c@4010000 {
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C1>;
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status = "disabled";
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};
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@ -148,6 +188,7 @@ i2c2: i2c@4020000 {
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C2>;
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status = "disabled";
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};
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@ -159,6 +200,7 @@ i2c3: i2c@4030000 {
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C3>;
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status = "disabled";
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};
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@ -170,9 +212,56 @@ i2c4: i2c@4040000 {
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
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clock-names = "ref", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_I2C4>;
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status = "disabled";
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};
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gmac0: ethernet@4070000 {
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compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a";
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reg = <0x04070000 0x10000>;
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clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>;
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clock-names = "stmmaceth", "ptp_ref";
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interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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phy-handle = <&internal_ephy>;
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phy-mode = "internal";
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resets = <&rst RST_ETH0>;
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reset-names = "stmmaceth";
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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snps,multicast-filter-bins = <0>;
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snps,perfect-filter-entries = <1>;
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snps,aal;
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snps,txpbl = <8>;
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snps,rxpbl = <8>;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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status = "disabled";
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gmac0_mdio: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <1>;
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queue0 {};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <1>;
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queue0 {};
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,blen = <16 8 4 0 0 0 0>;
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snps,rd_osr_lmt = <2>;
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snps,wr_osr_lmt = <1>;
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};
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};
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uart0: serial@4140000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04140000 0x100>;
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@ -181,6 +270,7 @@ uart0: serial@4140000 {
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART0>;
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status = "disabled";
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};
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@ -192,6 +282,7 @@ uart1: serial@4150000 {
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART1>;
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status = "disabled";
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};
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@ -203,6 +294,7 @@ uart2: serial@4160000 {
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART2>;
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status = "disabled";
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};
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@ -214,6 +306,7 @@ uart3: serial@4170000 {
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART3>;
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status = "disabled";
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};
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@ -225,6 +318,7 @@ spi0: spi@4180000 {
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI0>;
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status = "disabled";
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};
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@ -236,6 +330,7 @@ spi1: spi@4190000 {
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI1>;
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status = "disabled";
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};
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@ -247,6 +342,7 @@ spi2: spi@41a0000 {
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI2>;
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status = "disabled";
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};
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@ -258,6 +354,7 @@ spi3: spi@41b0000 {
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rst RST_SPI3>;
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status = "disabled";
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};
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@ -269,6 +366,7 @@ uart4: serial@41c0000 {
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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resets = <&rst RST_UART4>;
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status = "disabled";
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};
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@ -307,5 +405,17 @@ dmac: dma-controller@4330000 {
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snps,data-width = <2>;
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status = "disabled";
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};
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rtc@5025000 {
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compatible = "sophgo,cv1800b-rtc", "syscon";
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reg = <0x5025000 0x2000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(1) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "alarm", "longpress", "vbat";
|
||||
clocks = <&clk CLK_RTC_25M>,
|
||||
<&clk CLK_SRC_RTC_SYS_0>;
|
||||
clock-names = "rtc", "mcu";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -55,6 +55,14 @@ &emmc {
|
|||
non-removable;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
|
|
|
|||
98
arch/riscv/boot/dts/sophgo/cv18xx-reset.h
Normal file
98
arch/riscv/boot/dts/sophgo/cv18xx-reset.h
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2025 Inochi Amaoto <inochiama@outlook.com>
|
||||
*/
|
||||
|
||||
#ifndef _SOPHGO_CV18XX_RESET
|
||||
#define _SOPHGO_CV18XX_RESET
|
||||
|
||||
#define RST_DDR 2
|
||||
#define RST_H264C 3
|
||||
#define RST_JPEG 4
|
||||
#define RST_H265C 5
|
||||
#define RST_VIPSYS 6
|
||||
#define RST_TDMA 7
|
||||
#define RST_TPU 8
|
||||
#define RST_TPUSYS 9
|
||||
#define RST_USB 11
|
||||
#define RST_ETH0 12
|
||||
#define RST_ETH1 13
|
||||
#define RST_NAND 14
|
||||
#define RST_EMMC 15
|
||||
#define RST_SD0 16
|
||||
#define RST_SDMA 18
|
||||
#define RST_I2S0 19
|
||||
#define RST_I2S1 20
|
||||
#define RST_I2S2 21
|
||||
#define RST_I2S3 22
|
||||
#define RST_UART0 23
|
||||
#define RST_UART1 24
|
||||
#define RST_UART2 25
|
||||
#define RST_UART3 26
|
||||
#define RST_I2C0 27
|
||||
#define RST_I2C1 28
|
||||
#define RST_I2C2 29
|
||||
#define RST_I2C3 30
|
||||
#define RST_I2C4 31
|
||||
#define RST_PWM0 32
|
||||
#define RST_PWM1 33
|
||||
#define RST_PWM2 34
|
||||
#define RST_PWM3 35
|
||||
#define RST_SPI0 40
|
||||
#define RST_SPI1 41
|
||||
#define RST_SPI2 42
|
||||
#define RST_SPI3 43
|
||||
#define RST_GPIO0 44
|
||||
#define RST_GPIO1 45
|
||||
#define RST_GPIO2 46
|
||||
#define RST_EFUSE 47
|
||||
#define RST_WDT 48
|
||||
#define RST_AHB_ROM 49
|
||||
#define RST_SPIC 50
|
||||
#define RST_TEMPSEN 51
|
||||
#define RST_SARADC 52
|
||||
#define RST_COMBO_PHY0 58
|
||||
#define RST_SPI_NAND 61
|
||||
#define RST_SE 62
|
||||
#define RST_UART4 74
|
||||
#define RST_GPIO3 75
|
||||
#define RST_SYSTEM 76
|
||||
#define RST_TIMER 77
|
||||
#define RST_TIMER0 78
|
||||
#define RST_TIMER1 79
|
||||
#define RST_TIMER2 80
|
||||
#define RST_TIMER3 81
|
||||
#define RST_TIMER4 82
|
||||
#define RST_TIMER5 83
|
||||
#define RST_TIMER6 84
|
||||
#define RST_TIMER7 85
|
||||
#define RST_WGN0 86
|
||||
#define RST_WGN1 87
|
||||
#define RST_WGN2 88
|
||||
#define RST_KEYSCAN 89
|
||||
#define RST_AUDDAC 91
|
||||
#define RST_AUDDAC_APB 92
|
||||
#define RST_AUDADC 93
|
||||
#define RST_VCSYS 95
|
||||
#define RST_ETHPHY 96
|
||||
#define RST_ETHPHY_APB 97
|
||||
#define RST_AUDSRC 98
|
||||
#define RST_VIP_CAM0 99
|
||||
#define RST_WDT1 100
|
||||
#define RST_WDT2 101
|
||||
#define RST_AUTOCLEAR_CPUCORE0 256
|
||||
#define RST_AUTOCLEAR_CPUCORE1 257
|
||||
#define RST_AUTOCLEAR_CPUCORE2 258
|
||||
#define RST_AUTOCLEAR_CPUCORE3 259
|
||||
#define RST_AUTOCLEAR_CPUSYS0 260
|
||||
#define RST_AUTOCLEAR_CPUSYS1 261
|
||||
#define RST_AUTOCLEAR_CPUSYS2 262
|
||||
#define RST_CPUCORE0 288
|
||||
#define RST_CPUCORE1 289
|
||||
#define RST_CPUCORE2 290
|
||||
#define RST_CPUCORE3 291
|
||||
#define RST_CPUSYS0 292
|
||||
#define RST_CPUSYS1 293
|
||||
#define RST_CPUSYS2 294
|
||||
|
||||
#endif /* _SOPHGO_CV18XX_RESET */
|
||||
|
|
@ -259,8 +259,10 @@ cpu0: cpu@0 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <0>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -284,8 +286,10 @@ cpu1: cpu@1 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <1>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -309,8 +313,10 @@ cpu2: cpu@2 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <2>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -334,8 +340,10 @@ cpu3: cpu@3 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <3>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -359,8 +367,10 @@ cpu4: cpu@4 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <4>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -384,8 +394,10 @@ cpu5: cpu@5 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <5>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -409,8 +421,10 @@ cpu6: cpu@6 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <6>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -434,8 +448,10 @@ cpu7: cpu@7 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <7>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -459,8 +475,10 @@ cpu8: cpu@8 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <8>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -484,8 +502,10 @@ cpu9: cpu@9 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <9>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -509,8 +529,10 @@ cpu10: cpu@10 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <10>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -534,8 +556,10 @@ cpu11: cpu@11 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <11>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -559,8 +583,10 @@ cpu12: cpu@12 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <12>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -584,8 +610,10 @@ cpu13: cpu@13 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <13>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -609,8 +637,10 @@ cpu14: cpu@14 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <14>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -634,8 +664,10 @@ cpu15: cpu@15 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <15>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -659,8 +691,10 @@ cpu16: cpu@16 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <16>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -684,8 +718,10 @@ cpu17: cpu@17 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <17>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -709,8 +745,10 @@ cpu18: cpu@18 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <18>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -734,8 +772,10 @@ cpu19: cpu@19 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <19>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -759,8 +799,10 @@ cpu20: cpu@20 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <20>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -784,8 +826,10 @@ cpu21: cpu@21 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <21>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -809,8 +853,10 @@ cpu22: cpu@22 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <22>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -834,8 +880,10 @@ cpu23: cpu@23 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <23>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -859,8 +907,10 @@ cpu24: cpu@24 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <24>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -884,8 +934,10 @@ cpu25: cpu@25 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <25>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -909,8 +961,10 @@ cpu26: cpu@26 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <26>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -934,8 +988,10 @@ cpu27: cpu@27 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <27>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -959,8 +1015,10 @@ cpu28: cpu@28 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <28>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -984,8 +1042,10 @@ cpu29: cpu@29 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <29>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1009,8 +1069,10 @@ cpu30: cpu@30 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <30>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1034,8 +1096,10 @@ cpu31: cpu@31 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <31>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1059,8 +1123,10 @@ cpu32: cpu@32 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <32>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1084,8 +1150,10 @@ cpu33: cpu@33 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <33>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1109,8 +1177,10 @@ cpu34: cpu@34 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <34>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1134,8 +1204,10 @@ cpu35: cpu@35 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <35>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1159,8 +1231,10 @@ cpu36: cpu@36 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <36>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1184,8 +1258,10 @@ cpu37: cpu@37 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <37>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1209,8 +1285,10 @@ cpu38: cpu@38 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <38>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1234,8 +1312,10 @@ cpu39: cpu@39 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <39>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1259,8 +1339,10 @@ cpu40: cpu@40 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <40>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1284,8 +1366,10 @@ cpu41: cpu@41 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <41>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1309,8 +1393,10 @@ cpu42: cpu@42 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <42>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1334,8 +1420,10 @@ cpu43: cpu@43 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <43>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1359,8 +1447,10 @@ cpu44: cpu@44 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <44>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1384,8 +1474,10 @@ cpu45: cpu@45 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <45>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1409,8 +1501,10 @@ cpu46: cpu@46 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <46>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1434,8 +1528,10 @@ cpu47: cpu@47 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <47>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1459,8 +1555,10 @@ cpu48: cpu@48 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <48>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1484,8 +1582,10 @@ cpu49: cpu@49 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <49>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1509,8 +1609,10 @@ cpu50: cpu@50 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <50>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1534,8 +1636,10 @@ cpu51: cpu@51 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <51>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1559,8 +1663,10 @@ cpu52: cpu@52 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <52>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1584,8 +1690,10 @@ cpu53: cpu@53 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <53>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1609,8 +1717,10 @@ cpu54: cpu@54 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <54>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1634,8 +1744,10 @@ cpu55: cpu@55 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <55>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1659,8 +1771,10 @@ cpu56: cpu@56 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <56>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1684,8 +1798,10 @@ cpu57: cpu@57 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <57>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1709,8 +1825,10 @@ cpu58: cpu@58 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <58>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1734,8 +1852,10 @@ cpu59: cpu@59 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <59>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1759,8 +1879,10 @@ cpu60: cpu@60 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <60>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1784,8 +1906,10 @@ cpu61: cpu@61 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <61>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1809,8 +1933,10 @@ cpu62: cpu@62 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <62>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
@ -1834,8 +1960,10 @@ cpu63: cpu@63 {
|
|||
riscv,isa = "rv64imafdc";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
|
||||
"zicntr", "zicsr", "zifencei",
|
||||
"zihpm";
|
||||
"ziccrse", "zicntr", "zicsr",
|
||||
"zifencei", "zihpm", "zfh",
|
||||
"xtheadvector";
|
||||
thead,vlenb = <16>;
|
||||
reg = <63>;
|
||||
i-cache-block-size = <64>;
|
||||
i-cache-size = <65536>;
|
||||
|
|
|
|||
245
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
Normal file
245
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
Normal file
|
|
@ -0,0 +1,245 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sg2042.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Sophgo SG2042 EVB V1.X";
|
||||
compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
gpio-power {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-power {
|
||||
label = "Power Key";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&port0a 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,input-type = <EV_KEY>;
|
||||
debounce-interval = <100>;
|
||||
};
|
||||
};
|
||||
|
||||
pwmfan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <103 128 179 230 255>;
|
||||
pwms = <&pwm 0 40000 0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&mcu 0>;
|
||||
|
||||
trips {
|
||||
soc_active1: soc-active1 {
|
||||
temperature = <30000>;
|
||||
hysteresis = <8000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
soc_active2: soc-active2 {
|
||||
temperature = <58000>;
|
||||
hysteresis = <12000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
soc_active3: soc-active3 {
|
||||
temperature = <70000>;
|
||||
hysteresis = <10000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
soc_hot: soc-hot {
|
||||
temperature = <80000>;
|
||||
hysteresis = <5000>;
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&soc_active1>;
|
||||
cooling-device = <&pwmfan 0 1>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&soc_active2>;
|
||||
cooling-device = <&pwmfan 1 2>;
|
||||
};
|
||||
|
||||
map2 {
|
||||
trip = <&soc_active3>;
|
||||
cooling-device = <&pwmfan 2 3>;
|
||||
};
|
||||
|
||||
map3 {
|
||||
trip = <&soc_hot>;
|
||||
cooling-device = <&pwmfan 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
board-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&mcu 1>;
|
||||
|
||||
trips {
|
||||
board_active: board-active {
|
||||
temperature = <75000>;
|
||||
hysteresis = <8000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map4 {
|
||||
trip = <&board_active>;
|
||||
cooling-device = <&pwmfan 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cgi_main {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&cgi_dpll0 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&cgi_dpll1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
pinctrl-0 = <&emmc_cfg>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
wp-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_cfg>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
mcu: syscon@17 {
|
||||
compatible = "sophgo,sg2042-hwmon-mcu";
|
||||
reg = <0x17>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
emmc_cfg: sdhci-emmc-cfg {
|
||||
sdhci-emmc-wp-pins {
|
||||
pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
|
||||
bias-disable;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-disable;
|
||||
};
|
||||
|
||||
sdhci-emmc-cd-pins {
|
||||
pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
sdhci-emmc-rst-pwr-pins {
|
||||
pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
|
||||
<PINMUX(PIN_EMMC_PWR_EN, 0)>;
|
||||
bias-disable;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_cfg: i2c1-cfg {
|
||||
i2c1-pins {
|
||||
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
|
||||
<PINMUX(PIN_IIC1_SCL, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
sd_cfg: sdhci-sd-cfg {
|
||||
sdhci-sd-cd-wp-pins {
|
||||
pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
|
||||
<PINMUX(PIN_SDIO_WP, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
sdhci-sd-rst-pwr-pins {
|
||||
pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
|
||||
<PINMUX(PIN_SDIO_PWR_EN, 0)>;
|
||||
bias-disable;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_cfg: uart0-cfg {
|
||||
uart0-rx-pins {
|
||||
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
|
||||
<PINMUX(PIN_UART0_RX, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sd {
|
||||
pinctrl-0 = <&sd_cfg>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
wp-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_cfg>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
233
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
Normal file
233
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
Normal file
|
|
@ -0,0 +1,233 @@
|
|||
// SPDX-License-Identifier: GPL-2.0 OR MIT
|
||||
/*
|
||||
* Copyright (C) 2025 Sophgo Technology Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#include "sg2042.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Sophgo SG2042 EVB V2.0";
|
||||
compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0";
|
||||
};
|
||||
|
||||
pwmfan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <103 128 179 230 255>;
|
||||
pwms = <&pwm 0 40000 0>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
soc-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&mcu 0>;
|
||||
|
||||
trips {
|
||||
soc_active1: soc-active1 {
|
||||
temperature = <30000>;
|
||||
hysteresis = <8000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
soc_active2: soc-active2 {
|
||||
temperature = <58000>;
|
||||
hysteresis = <12000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
soc_active3: soc-active3 {
|
||||
temperature = <70000>;
|
||||
hysteresis = <10000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
soc_hot: soc-hot {
|
||||
temperature = <80000>;
|
||||
hysteresis = <5000>;
|
||||
type = "hot";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&soc_active1>;
|
||||
cooling-device = <&pwmfan 0 1>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&soc_active2>;
|
||||
cooling-device = <&pwmfan 1 2>;
|
||||
};
|
||||
|
||||
map2 {
|
||||
trip = <&soc_active3>;
|
||||
cooling-device = <&pwmfan 2 3>;
|
||||
};
|
||||
|
||||
map3 {
|
||||
trip = <&soc_hot>;
|
||||
cooling-device = <&pwmfan 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
board-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&mcu 1>;
|
||||
|
||||
trips {
|
||||
board_active: board-active {
|
||||
temperature = <75000>;
|
||||
hysteresis = <8000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map4 {
|
||||
trip = <&board_active>;
|
||||
cooling-device = <&pwmfan 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cgi_main {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&cgi_dpll0 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&cgi_dpll1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
pinctrl-0 = <&emmc_cfg>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
wp-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_cfg>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
mcu: syscon@17 {
|
||||
compatible = "sophgo,sg2042-hwmon-mcu";
|
||||
reg = <0x17>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
emmc_cfg: sdhci-emmc-cfg {
|
||||
sdhci-emmc-wp-pins {
|
||||
pinmux = <PINMUX(PIN_EMMC_WP, 0)>;
|
||||
bias-disable;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-disable;
|
||||
};
|
||||
|
||||
sdhci-emmc-cd-pins {
|
||||
pinmux = <PINMUX(PIN_EMMC_CD, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
sdhci-emmc-rst-pwr-pins {
|
||||
pinmux = <PINMUX(PIN_EMMC_RST, 0)>,
|
||||
<PINMUX(PIN_EMMC_PWR_EN, 0)>;
|
||||
bias-disable;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_cfg: i2c1-cfg {
|
||||
i2c1-pins {
|
||||
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
|
||||
<PINMUX(PIN_IIC1_SCL, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
sd_cfg: sdhci-sd-cfg {
|
||||
sdhci-sd-cd-wp-pins {
|
||||
pinmux = <PINMUX(PIN_SDIO_CD, 0)>,
|
||||
<PINMUX(PIN_SDIO_WP, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
|
||||
sdhci-sd-rst-pwr-pins {
|
||||
pinmux = <PINMUX(PIN_SDIO_RST, 0)>,
|
||||
<PINMUX(PIN_SDIO_PWR_EN, 0)>;
|
||||
bias-disable;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart0_cfg: uart0-cfg {
|
||||
uart0-rx-pins {
|
||||
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
|
||||
<PINMUX(PIN_UART0_RX, 0)>;
|
||||
bias-pull-up;
|
||||
drive-strength-microamp = <26800>;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sd {
|
||||
pinctrl-0 = <&sd_cfg>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
wp-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_cfg>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -569,6 +569,67 @@ spi1: spi@7040005000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: ethernet@7040026000 {
|
||||
compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a";
|
||||
reg = <0x70 0x40026000 0x0 0x4000>;
|
||||
clocks = <&clkgen GATE_CLK_AXI_ETH0>,
|
||||
<&clkgen GATE_CLK_PTP_REF_I_ETH0>,
|
||||
<&clkgen GATE_CLK_TX_ETH0>;
|
||||
clock-names = "stmmaceth", "ptp_ref", "tx";
|
||||
dma-noncoherent;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
resets = <&rstgen RST_ETH0>;
|
||||
reset-names = "stmmaceth";
|
||||
snps,multicast-filter-bins = <0>;
|
||||
snps,perfect-filter-entries = <1>;
|
||||
snps,aal;
|
||||
snps,tso;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gmac0_mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
queue2 {};
|
||||
queue3 {};
|
||||
queue4 {};
|
||||
queue5 {};
|
||||
queue6 {};
|
||||
queue7 {};
|
||||
};
|
||||
|
||||
gmac0_mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
queue2 {};
|
||||
queue3 {};
|
||||
queue4 {};
|
||||
queue5 {};
|
||||
queue6 {};
|
||||
queue7 {};
|
||||
};
|
||||
|
||||
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
snps,wr_osr_lmt = <1>;
|
||||
snps,rd_osr_lmt = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc: mmc@704002a000 {
|
||||
compatible = "sophgo,sg2042-dwcmshc";
|
||||
reg = <0x70 0x4002a000 0x0 0x1000>;
|
||||
|
|
|
|||
|
|
@ -32,12 +32,13 @@ cpu0: cpu@0 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu0_intc: interrupt-controller {
|
||||
|
|
@ -67,12 +68,13 @@ cpu1: cpu@1 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu1_intc: interrupt-controller {
|
||||
|
|
@ -102,12 +104,13 @@ cpu2: cpu@2 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu2_intc: interrupt-controller {
|
||||
|
|
@ -137,12 +140,13 @@ cpu3: cpu@3 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu3_intc: interrupt-controller {
|
||||
|
|
@ -172,12 +176,13 @@ cpu4: cpu@4 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu4_intc: interrupt-controller {
|
||||
|
|
@ -207,12 +212,13 @@ cpu5: cpu@5 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu5_intc: interrupt-controller {
|
||||
|
|
@ -242,12 +248,13 @@ cpu6: cpu@6 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu6_intc: interrupt-controller {
|
||||
|
|
@ -277,12 +284,13 @@ cpu7: cpu@7 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu7_intc: interrupt-controller {
|
||||
|
|
@ -312,12 +320,13 @@ cpu8: cpu@8 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu8_intc: interrupt-controller {
|
||||
|
|
@ -347,12 +356,13 @@ cpu9: cpu@9 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu9_intc: interrupt-controller {
|
||||
|
|
@ -382,12 +392,13 @@ cpu10: cpu@10 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu10_intc: interrupt-controller {
|
||||
|
|
@ -417,12 +428,13 @@ cpu11: cpu@11 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu11_intc: interrupt-controller {
|
||||
|
|
@ -452,12 +464,13 @@ cpu12: cpu@12 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu12_intc: interrupt-controller {
|
||||
|
|
@ -487,12 +500,13 @@ cpu13: cpu@13 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu13_intc: interrupt-controller {
|
||||
|
|
@ -522,12 +536,13 @@ cpu14: cpu@14 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu14_intc: interrupt-controller {
|
||||
|
|
@ -557,12 +572,13 @@ cpu15: cpu@15 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu15_intc: interrupt-controller {
|
||||
|
|
@ -592,12 +608,13 @@ cpu16: cpu@16 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu16_intc: interrupt-controller {
|
||||
|
|
@ -627,12 +644,13 @@ cpu17: cpu@17 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu17_intc: interrupt-controller {
|
||||
|
|
@ -662,12 +680,13 @@ cpu18: cpu@18 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu18_intc: interrupt-controller {
|
||||
|
|
@ -697,12 +716,13 @@ cpu19: cpu@19 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu19_intc: interrupt-controller {
|
||||
|
|
@ -732,12 +752,13 @@ cpu20: cpu@20 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu20_intc: interrupt-controller {
|
||||
|
|
@ -767,12 +788,13 @@ cpu21: cpu@21 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu21_intc: interrupt-controller {
|
||||
|
|
@ -802,12 +824,13 @@ cpu22: cpu@22 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu22_intc: interrupt-controller {
|
||||
|
|
@ -837,12 +860,13 @@ cpu23: cpu@23 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu23_intc: interrupt-controller {
|
||||
|
|
@ -872,12 +896,13 @@ cpu24: cpu@24 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu24_intc: interrupt-controller {
|
||||
|
|
@ -907,12 +932,13 @@ cpu25: cpu@25 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu25_intc: interrupt-controller {
|
||||
|
|
@ -942,12 +968,13 @@ cpu26: cpu@26 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu26_intc: interrupt-controller {
|
||||
|
|
@ -977,12 +1004,13 @@ cpu27: cpu@27 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu27_intc: interrupt-controller {
|
||||
|
|
@ -1012,12 +1040,13 @@ cpu28: cpu@28 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu28_intc: interrupt-controller {
|
||||
|
|
@ -1047,12 +1076,13 @@ cpu29: cpu@29 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu29_intc: interrupt-controller {
|
||||
|
|
@ -1082,12 +1112,13 @@ cpu30: cpu@30 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu30_intc: interrupt-controller {
|
||||
|
|
@ -1117,12 +1148,13 @@ cpu31: cpu@31 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu31_intc: interrupt-controller {
|
||||
|
|
@ -1152,12 +1184,13 @@ cpu32: cpu@32 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu32_intc: interrupt-controller {
|
||||
|
|
@ -1187,12 +1220,13 @@ cpu33: cpu@33 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu33_intc: interrupt-controller {
|
||||
|
|
@ -1222,12 +1256,13 @@ cpu34: cpu@34 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu34_intc: interrupt-controller {
|
||||
|
|
@ -1257,12 +1292,13 @@ cpu35: cpu@35 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu35_intc: interrupt-controller {
|
||||
|
|
@ -1292,12 +1328,13 @@ cpu36: cpu@36 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu36_intc: interrupt-controller {
|
||||
|
|
@ -1327,12 +1364,13 @@ cpu37: cpu@37 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu37_intc: interrupt-controller {
|
||||
|
|
@ -1362,12 +1400,13 @@ cpu38: cpu@38 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu38_intc: interrupt-controller {
|
||||
|
|
@ -1397,12 +1436,13 @@ cpu39: cpu@39 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu39_intc: interrupt-controller {
|
||||
|
|
@ -1432,12 +1472,13 @@ cpu40: cpu@40 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu40_intc: interrupt-controller {
|
||||
|
|
@ -1467,12 +1508,13 @@ cpu41: cpu@41 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu41_intc: interrupt-controller {
|
||||
|
|
@ -1502,12 +1544,13 @@ cpu42: cpu@42 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu42_intc: interrupt-controller {
|
||||
|
|
@ -1537,12 +1580,13 @@ cpu43: cpu@43 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu43_intc: interrupt-controller {
|
||||
|
|
@ -1572,12 +1616,13 @@ cpu44: cpu@44 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu44_intc: interrupt-controller {
|
||||
|
|
@ -1607,12 +1652,13 @@ cpu45: cpu@45 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu45_intc: interrupt-controller {
|
||||
|
|
@ -1642,12 +1688,13 @@ cpu46: cpu@46 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu46_intc: interrupt-controller {
|
||||
|
|
@ -1677,12 +1724,13 @@ cpu47: cpu@47 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu47_intc: interrupt-controller {
|
||||
|
|
@ -1712,12 +1760,13 @@ cpu48: cpu@48 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu48_intc: interrupt-controller {
|
||||
|
|
@ -1747,12 +1796,13 @@ cpu49: cpu@49 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu49_intc: interrupt-controller {
|
||||
|
|
@ -1782,12 +1832,13 @@ cpu50: cpu@50 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu50_intc: interrupt-controller {
|
||||
|
|
@ -1817,12 +1868,13 @@ cpu51: cpu@51 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu51_intc: interrupt-controller {
|
||||
|
|
@ -1852,12 +1904,13 @@ cpu52: cpu@52 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu52_intc: interrupt-controller {
|
||||
|
|
@ -1887,12 +1940,13 @@ cpu53: cpu@53 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu53_intc: interrupt-controller {
|
||||
|
|
@ -1922,12 +1976,13 @@ cpu54: cpu@54 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu54_intc: interrupt-controller {
|
||||
|
|
@ -1957,12 +2012,13 @@ cpu55: cpu@55 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu55_intc: interrupt-controller {
|
||||
|
|
@ -1992,12 +2048,13 @@ cpu56: cpu@56 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu56_intc: interrupt-controller {
|
||||
|
|
@ -2027,12 +2084,13 @@ cpu57: cpu@57 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu57_intc: interrupt-controller {
|
||||
|
|
@ -2062,12 +2120,13 @@ cpu58: cpu@58 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu58_intc: interrupt-controller {
|
||||
|
|
@ -2097,12 +2156,13 @@ cpu59: cpu@59 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu59_intc: interrupt-controller {
|
||||
|
|
@ -2132,12 +2192,13 @@ cpu60: cpu@60 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu60_intc: interrupt-controller {
|
||||
|
|
@ -2167,12 +2228,13 @@ cpu61: cpu@61 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu61_intc: interrupt-controller {
|
||||
|
|
@ -2202,12 +2264,13 @@ cpu62: cpu@62 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu62_intc: interrupt-controller {
|
||||
|
|
@ -2237,12 +2300,13 @@ cpu63: cpu@63 {
|
|||
"zawrs", "zba", "zbb", "zbc",
|
||||
"zbs", "zca", "zcb", "zcd",
|
||||
"zfa", "zfbfmin", "zfh", "zfhmin",
|
||||
"zicbom", "zicbop", "zicboz",
|
||||
"zicbom", "zicbop", "zicboz", "ziccrse",
|
||||
"zicntr", "zicond","zicsr", "zifencei",
|
||||
"zihintntl", "zihintpause", "zihpm",
|
||||
"zvfbfmin", "zvfbfwma", "zvfh",
|
||||
"zvfhmin";
|
||||
riscv,cbom-block-size = <64>;
|
||||
riscv,cbop-block-size = <64>;
|
||||
riscv,cboz-block-size = <64>;
|
||||
|
||||
cpu63_intc: interrupt-controller {
|
||||
|
|
@ -2714,6 +2778,97 @@ l3_cache: cache-controller-16 {
|
|||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "riscv,pmu";
|
||||
riscv,event-to-mhpmevent =
|
||||
<0x00003 0x00000000 0x00000010>,
|
||||
<0x00004 0x00000000 0x00000011>,
|
||||
<0x00005 0x00000000 0x00000007>,
|
||||
<0x00006 0x00000000 0x00000006>,
|
||||
<0x00008 0x00000000 0x00000027>,
|
||||
<0x00009 0x00000000 0x00000028>,
|
||||
<0x10000 0x00000000 0x0000000c>,
|
||||
<0x10001 0x00000000 0x0000000d>,
|
||||
<0x10002 0x00000000 0x0000000e>,
|
||||
<0x10003 0x00000000 0x0000000f>,
|
||||
<0x10008 0x00000000 0x00000001>,
|
||||
<0x10009 0x00000000 0x00000002>,
|
||||
<0x10010 0x00000000 0x00000010>,
|
||||
<0x10011 0x00000000 0x00000011>,
|
||||
<0x10012 0x00000000 0x00000012>,
|
||||
<0x10013 0x00000000 0x00000013>,
|
||||
<0x10019 0x00000000 0x00000004>,
|
||||
<0x10021 0x00000000 0x00000003>,
|
||||
<0x10030 0x00000000 0x0000001c>,
|
||||
<0x10031 0x00000000 0x0000001b>;
|
||||
riscv,event-to-mhpmcounters =
|
||||
<0x00003 0x00003 0xfffffff8>,
|
||||
<0x00004 0x00004 0xfffffff8>,
|
||||
<0x00005 0x00005 0xfffffff8>,
|
||||
<0x00006 0x00006 0xfffffff8>,
|
||||
<0x00007 0x00007 0xfffffff8>,
|
||||
<0x00008 0x00008 0xfffffff8>,
|
||||
<0x00009 0x00009 0xfffffff8>,
|
||||
<0x0000a 0x0000a 0xfffffff8>,
|
||||
<0x10000 0x10000 0xfffffff8>,
|
||||
<0x10001 0x10001 0xfffffff8>,
|
||||
<0x10002 0x10002 0xfffffff8>,
|
||||
<0x10003 0x10003 0xfffffff8>,
|
||||
<0x10008 0x10008 0xfffffff8>,
|
||||
<0x10009 0x10009 0xfffffff8>,
|
||||
<0x10010 0x10010 0xfffffff8>,
|
||||
<0x10011 0x10011 0xfffffff8>,
|
||||
<0x10012 0x10012 0xfffffff8>,
|
||||
<0x10013 0x10013 0xfffffff8>,
|
||||
<0x10019 0x10019 0xfffffff8>,
|
||||
<0x10021 0x10021 0xfffffff8>,
|
||||
<0x10030 0x10030 0xfffffff8>,
|
||||
<0x10031 0x10031 0xfffffff8>;
|
||||
riscv,raw-event-to-mhpmcounters =
|
||||
<0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
|
||||
<0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
|
||||
};
|
||||
|
||||
soc {
|
||||
intc: interrupt-controller@6d40000000 {
|
||||
compatible = "sophgo,sg2044-plic", "thead,c900-plic";
|
||||
|
|
|
|||
|
|
@ -27,6 +27,93 @@ &osc {
|
|||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
non-removable;
|
||||
wp-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
reset-gpios = <&porta 28 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <10000>;
|
||||
rx-internal-delay-ps = <2050>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
mcu: syscon@17 {
|
||||
compatible = "sophgo,sg2044-hwmon-mcu", "sophgo,sg2042-hwmon-mcu";
|
||||
reg = <0x17>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&msi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
bus-range = <0x00 0xff>;
|
||||
linux,pci-domain = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
bus-range = <0x00 0xff>;
|
||||
linux,pci-domain = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
bus-range = <0x00 0xff>;
|
||||
linux,pci-domain = <3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3 {
|
||||
bus-range = <0x00 0xff>;
|
||||
linux,pci-domain = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
bus-range = <0x00 0xff>;
|
||||
linux,pci-domain = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sd {
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
wp-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
/* for firmware */
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,7 +3,11 @@
|
|||
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/sophgo,sg2044-pll.h>
|
||||
#include <dt-bindings/clock/sophgo,sg2044-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-sg2044.h>
|
||||
|
||||
#include "sg2044-cpus.dtsi"
|
||||
#include "sg2044-reset.h"
|
||||
|
|
@ -28,10 +32,243 @@ soc {
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pcie0: pcie@6c00000000 {
|
||||
compatible = "sophgo,sg2044-pcie";
|
||||
reg = <0x6c 0x00000000 0x0 0x00001000>,
|
||||
<0x6c 0x00300000 0x0 0x00004000>,
|
||||
<0x48 0x00000000 0x0 0x00001000>,
|
||||
<0x6c 0x000c0000 0x0 0x00001000>;
|
||||
reg-names = "dbi", "atu", "config", "app";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
clocks = <&clk CLK_GATE_PCIE_1G>;
|
||||
clock-names = "core";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
msi-parent = <&msi>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>,
|
||||
<0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>,
|
||||
<0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>,
|
||||
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
|
||||
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc0: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@6c00400000 {
|
||||
compatible = "sophgo,sg2044-pcie";
|
||||
reg = <0x6c 0x00400000 0x0 0x00001000>,
|
||||
<0x6c 0x00700000 0x0 0x00004000>,
|
||||
<0x40 0x00000000 0x0 0x00001000>,
|
||||
<0x6c 0x00780000 0x0 0x00001000>;
|
||||
reg-names = "dbi", "atu", "config", "app";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
clocks = <&clk CLK_GATE_PCIE_1G>;
|
||||
clock-names = "core";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
msi-parent = <&msi>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
|
||||
<0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
|
||||
<0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
|
||||
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
|
||||
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc1: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2: pcie@6c04000000 {
|
||||
compatible = "sophgo,sg2044-pcie";
|
||||
reg = <0x6c 0x04000000 0x0 0x00001000>,
|
||||
<0x6c 0x04300000 0x0 0x00004000>,
|
||||
<0x58 0x00000000 0x0 0x00001000>,
|
||||
<0x6c 0x040c0000 0x0 0x00001000>;
|
||||
reg-names = "dbi", "atu", "config", "app";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
clocks = <&clk CLK_GATE_PCIE_1G>;
|
||||
clock-names = "core";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
|
||||
<0 0 0 2 &pcie_intc2 1>,
|
||||
<0 0 0 3 &pcie_intc2 2>,
|
||||
<0 0 0 4 &pcie_intc2 3>;
|
||||
msi-parent = <&msi>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>,
|
||||
<0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>,
|
||||
<0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>,
|
||||
<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
|
||||
<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc2: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie3: pcie@6c04400000 {
|
||||
compatible = "sophgo,sg2044-pcie";
|
||||
reg = <0x6c 0x04400000 0x0 0x00001000>,
|
||||
<0x6c 0x04700000 0x0 0x00004000>,
|
||||
<0x50 0x00000000 0x0 0x00001000>,
|
||||
<0x6c 0x04780000 0x0 0x00001000>;
|
||||
reg-names = "dbi", "atu", "config", "app";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
clocks = <&clk CLK_GATE_PCIE_1G>;
|
||||
clock-names = "core";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc3 0>,
|
||||
<0 0 0 2 &pcie_intc3 1>,
|
||||
<0 0 0 3 &pcie_intc3 2>,
|
||||
<0 0 0 4 &pcie_intc3 3>;
|
||||
msi-parent = <&msi>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>,
|
||||
<0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>,
|
||||
<0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>,
|
||||
<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
|
||||
<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc3: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie4: pcie@6c08400000 {
|
||||
compatible = "sophgo,sg2044-pcie";
|
||||
reg = <0x6c 0x08400000 0x0 0x00001000>,
|
||||
<0x6c 0x08700000 0x0 0x00004000>,
|
||||
<0x60 0x00000000 0x0 0x00001000>,
|
||||
<0x6c 0x08780000 0x0 0x00001000>;
|
||||
reg-names = "dbi", "atu", "config", "app";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
clocks = <&clk CLK_GATE_PCIE_1G>;
|
||||
clock-names = "core";
|
||||
device_type = "pci";
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc4 0>,
|
||||
<0 0 0 2 &pcie_intc4 1>,
|
||||
<0 0 0 3 &pcie_intc4 2>,
|
||||
<0 0 0 4 &pcie_intc4 3>;
|
||||
msi-parent = <&msi>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>,
|
||||
<0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>,
|
||||
<0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>,
|
||||
<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
|
||||
<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc4: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
msi: msi-controller@6d50000000 {
|
||||
compatible = "sophgo,sg2044-msi";
|
||||
reg = <0x6d 0x50000000 0x0 0x800>,
|
||||
<0x0 0x7ee00000 0x0 0x40>;
|
||||
reg-names = "clr", "doorbell";
|
||||
#msi-cells = <0>;
|
||||
msi-controller;
|
||||
msi-ranges = <&intc 352 IRQ_TYPE_LEVEL_HIGH 512>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spifmc0: spi@7001000000 {
|
||||
compatible = "sophgo,sg2044-spifmc-nor";
|
||||
reg = <0x70 0x01000000 0x0 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk CLK_GATE_AHB_SPIFMC>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rst RST_SPIFMC0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spifmc1: spi@7005000000 {
|
||||
compatible = "sophgo,sg2044-spifmc-nor";
|
||||
reg = <0x70 0x05000000 0x0 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk CLK_GATE_AHB_SPIFMC>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rst RST_SPIFMC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac0: dma-controller@7020000000 {
|
||||
compatible = "snps,axi-dma-1.01a";
|
||||
reg = <0x70 0x20000000 0x0 0x10000>;
|
||||
#dma-cells = <1>;
|
||||
clock-names = "core-clk", "cfgr-clk";
|
||||
clocks = <&clk CLK_GATE_SYSDMA_AXI>,
|
||||
<&clk CLK_GATE_SYSDMA_AXI>;
|
||||
dma-noncoherent;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dma-channels = <8>;
|
||||
snps,priority = <0 1 2 3 4 5 6 7>;
|
||||
snps,block-size = <4096 4096 4096 4096
|
||||
4096 4096 4096 4096>;
|
||||
snps,dma-masters = <2>;
|
||||
snps,data-width = <2>;
|
||||
snps,axi-max-burst-len = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@7030000000 {
|
||||
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
|
||||
reg = <0x70 0x30000000 0x0 0x1000>;
|
||||
clock-frequency = <500000000>;
|
||||
clocks = <&clk CLK_GATE_UART_500M>,
|
||||
<&clk CLK_GATE_APB_UART>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
|
|
@ -44,6 +281,9 @@ uart1: serial@7030001000 {
|
|||
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
|
||||
reg = <0x70 0x30001000 0x0 0x1000>;
|
||||
clock-frequency = <500000000>;
|
||||
clocks = <&clk CLK_GATE_UART_500M>,
|
||||
<&clk CLK_GATE_APB_UART>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
|
|
@ -56,6 +296,9 @@ uart2: serial@7030002000 {
|
|||
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
|
||||
reg = <0x70 0x30002000 0x0 0x1000>;
|
||||
clock-frequency = <500000000>;
|
||||
clocks = <&clk CLK_GATE_UART_500M>,
|
||||
<&clk CLK_GATE_APB_UART>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
|
|
@ -68,6 +311,9 @@ uart3: serial@7030003000 {
|
|||
compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
|
||||
reg = <0x70 0x30003000 0x0 0x1000>;
|
||||
clock-frequency = <500000000>;
|
||||
clocks = <&clk CLK_GATE_UART_500M>,
|
||||
<&clk CLK_GATE_APB_UART>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
|
|
@ -76,6 +322,259 @@ uart3: serial@7030003000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: ethernet@7030006000 {
|
||||
compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a";
|
||||
reg = <0x70 0x30006000 0x0 0x4000>;
|
||||
clocks = <&clk CLK_GATE_AXI_ETH0>,
|
||||
<&clk CLK_GATE_PTP_REF_I_ETH0>,
|
||||
<&clk CLK_GATE_TX_ETH0>;
|
||||
clock-names = "stmmaceth", "ptp_ref", "tx";
|
||||
dma-noncoherent;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <296 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
resets = <&rst RST_ETH0>;
|
||||
reset-names = "stmmaceth";
|
||||
snps,multicast-filter-bins = <0>;
|
||||
snps,perfect-filter-entries = <1>;
|
||||
snps,aal;
|
||||
snps,tso;
|
||||
snps,txpbl = <32>;
|
||||
snps,rxpbl = <32>;
|
||||
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
gmac0_mtl_rx_setup: rx-queues-config {
|
||||
snps,rx-queues-to-use = <8>;
|
||||
snps,rx-sched-wsp;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
queue2 {};
|
||||
queue3 {};
|
||||
queue4 {};
|
||||
queue5 {};
|
||||
queue6 {};
|
||||
queue7 {};
|
||||
};
|
||||
|
||||
gmac0_mtl_tx_setup: tx-queues-config {
|
||||
snps,tx-queues-to-use = <8>;
|
||||
queue0 {};
|
||||
queue1 {};
|
||||
queue2 {};
|
||||
queue3 {};
|
||||
queue4 {};
|
||||
queue5 {};
|
||||
queue6 {};
|
||||
queue7 {};
|
||||
};
|
||||
|
||||
gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
snps,blen = <16 8 4 0 0 0 0>;
|
||||
snps,wr_osr_lmt = <1>;
|
||||
snps,rd_osr_lmt = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc: mmc@703000a000 {
|
||||
compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
|
||||
reg = <0x70 0x3000a000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_GATE_EMMC>,
|
||||
<&clk CLK_GATE_AXI_EMMC>,
|
||||
<&clk CLK_GATE_EMMC_100K>;
|
||||
clock-names = "core", "bus", "timer";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <298 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sd: mmc@703000b000 {
|
||||
compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
|
||||
reg = <0x70 0x3000b000 0x0 0x1000>;
|
||||
clocks = <&clk CLK_GATE_SD>,
|
||||
<&clk CLK_GATE_AXI_SD>,
|
||||
<&clk CLK_GATE_SD_100K>;
|
||||
clock-names = "core", "bus", "timer";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@7040005000 {
|
||||
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
|
||||
reg = <0x70 0x40005000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&clk CLK_GATE_APB_I2C>;
|
||||
clock-names = "ref";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rst RST_I2C0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@7040006000 {
|
||||
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
|
||||
reg = <0x70 0x40006000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&clk CLK_GATE_APB_I2C>;
|
||||
clock-names = "ref";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rst RST_I2C1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@7040007000 {
|
||||
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
|
||||
reg = <0x70 0x40007000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&clk CLK_GATE_APB_I2C>;
|
||||
clock-names = "ref";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rst RST_I2C2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@7040008000 {
|
||||
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
|
||||
reg = <0x70 0x40008000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <100000>;
|
||||
clocks = <&clk CLK_GATE_APB_I2C>;
|
||||
clock-names = "ref";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rst RST_I2C3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@7040009000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x70 0x40009000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk CLK_GATE_APB_GPIO>,
|
||||
<&clk CLK_GATE_GPIO_DB>;
|
||||
clock-names = "bus", "db";
|
||||
resets = <&rst RST_GPIO0>;
|
||||
|
||||
porta: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@704000a000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x70 0x4000a000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk CLK_GATE_APB_GPIO>,
|
||||
<&clk CLK_GATE_GPIO_DB>;
|
||||
clock-names = "bus", "db";
|
||||
resets = <&rst RST_GPIO1>;
|
||||
|
||||
portb: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@704000b000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x70 0x4000b000 0x0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk CLK_GATE_APB_GPIO>,
|
||||
<&clk CLK_GATE_GPIO_DB>;
|
||||
clock-names = "bus", "db";
|
||||
resets = <&rst RST_GPIO2>;
|
||||
|
||||
portc: gpio-controller@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <32>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm: pwm@704000c000 {
|
||||
compatible = "sophgo,sg2044-pwm";
|
||||
reg = <0x70 0x4000c000 0x0 0x1000>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&clk CLK_GATE_APB_PWM>;
|
||||
clock-names = "apb";
|
||||
resets = <&rst RST_PWM>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscon: syscon@7050000000 {
|
||||
compatible = "sophgo,sg2044-top-syscon", "syscon";
|
||||
reg = <0x70 0x50000000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@7050001000 {
|
||||
compatible = "sophgo,sg2044-pinctrl";
|
||||
reg = <0x70 0x50001000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
clk: clock-controller@7050002000 {
|
||||
compatible = "sophgo,sg2044-clk";
|
||||
reg = <0x70 0x50002000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
|
||||
<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
|
||||
<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
|
||||
<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
|
||||
<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
|
||||
<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
|
||||
<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
|
||||
<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
|
||||
<&syscon CLK_MPLL5>;
|
||||
clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
|
||||
"dpll1", "dpll2", "dpll3", "dpll4",
|
||||
"dpll5", "dpll6", "dpll7", "mpll0",
|
||||
"mpll1", "mpll2", "mpll3", "mpll4",
|
||||
"mpll5";
|
||||
};
|
||||
|
||||
rst: reset-controller@7050003000 {
|
||||
compatible = "sophgo,sg2044-reset",
|
||||
"sophgo,sg2042-reset";
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user