From 616c84f0473b1292a232b979c5a441de3039bb88 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Tue, 13 May 2025 22:31:25 +0200 Subject: [PATCH 01/32] riscv: dts: sophgo: cv18xx: Add RTCSYS device node Add the RTCSYS MFD node: in Cvitek CV18xx and its successors RTC Subsystem is quite advanced and provides SoC power management functions as well. The SoC family also contains DW8051 block (Intel 8051 compatible CPU core) and an associated SRAM. The corresponding control registers are mapped into RTCSYS address space as well. Link: https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM Signed-off-by: Alexander Sverdlin Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/20250513203128.620731-1-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index ed06c3609fb2..280c45bd3b3d 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -307,5 +307,17 @@ dmac: dma-controller@4330000 { snps,data-width = <2>; status = "disabled"; }; + + rtc@5025000 { + compatible = "sophgo,cv1800b-rtc", "syscon"; + reg = <0x5025000 0x2000>; + interrupts = , + , + ; + interrupt-names = "alarm", "longpress", "vbat"; + clocks = <&clk CLK_RTC_25M>, + <&clk CLK_SRC_RTC_SYS_0>; + clock-names = "rtc", "mcu"; + }; }; }; From 95f119e36443b0028d78986f01f382024c811ddb Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:25 +0800 Subject: [PATCH 02/32] riscv: dts: sophgo: sg2044: Add system controller device The TOP system controller device is necessary for the SG2044 clock controller. Add it to the SoC device tree. Link: https://lore.kernel.org/r/20250608232836.784737-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index d67e45f77d6e..a0c13d8d26af 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -76,6 +76,13 @@ uart3: serial@7030003000 { status = "disabled"; }; + syscon: syscon@7050000000 { + compatible = "sophgo,sg2044-top-syscon", "syscon"; + reg = <0x70 0x50000000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&osc>; + }; + rst: reset-controller@7050003000 { compatible = "sophgo,sg2044-reset", "sophgo,sg2042-reset"; From 1995b2644fd9534058c4e4d3e7e44588ca663daf Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:26 +0800 Subject: [PATCH 03/32] riscv: dts: sophgo: sg2044: Add clock controller device Add clock controller and pll clock node for sg2044. Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index a0c13d8d26af..d21a59948186 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2025 Inochi Amaoto */ +#include +#include #include #include "sg2044-cpus.dtsi" @@ -32,6 +34,9 @@ uart0: serial@7030000000 { compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; reg = <0x70 0x30000000 0x0 0x1000>; clock-frequency = <500000000>; + clocks = <&clk CLK_GATE_UART_500M>, + <&clk CLK_GATE_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupt-parent = <&intc>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; @@ -44,6 +49,9 @@ uart1: serial@7030001000 { compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; reg = <0x70 0x30001000 0x0 0x1000>; clock-frequency = <500000000>; + clocks = <&clk CLK_GATE_UART_500M>, + <&clk CLK_GATE_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupt-parent = <&intc>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; @@ -56,6 +64,9 @@ uart2: serial@7030002000 { compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; reg = <0x70 0x30002000 0x0 0x1000>; clock-frequency = <500000000>; + clocks = <&clk CLK_GATE_UART_500M>, + <&clk CLK_GATE_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupt-parent = <&intc>; interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; @@ -68,6 +79,9 @@ uart3: serial@7030003000 { compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; reg = <0x70 0x30003000 0x0 0x1000>; clock-frequency = <500000000>; + clocks = <&clk CLK_GATE_UART_500M>, + <&clk CLK_GATE_APB_UART>; + clock-names = "baudclk", "apb_pclk"; interrupt-parent = <&intc>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; @@ -83,6 +97,26 @@ syscon: syscon@7050000000 { clocks = <&osc>; }; + clk: clock-controller@7050002000 { + compatible = "sophgo,sg2044-clk"; + reg = <0x70 0x50002000 0x0 0x1000>; + #clock-cells = <1>; + clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>, + <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>, + <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>, + <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>, + <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>, + <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>, + <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>, + <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>, + <&syscon CLK_MPLL5>; + clock-names = "fpll0", "fpll1", "fpll2", "dpll0", + "dpll1", "dpll2", "dpll3", "dpll4", + "dpll5", "dpll6", "dpll7", "mpll0", + "mpll1", "mpll2", "mpll3", "mpll4", + "mpll5"; + }; + rst: reset-controller@7050003000 { compatible = "sophgo,sg2044-reset", "sophgo,sg2042-reset"; From cfb8869685caf80b16c2ec77a85f9093dddc9ac6 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:27 +0800 Subject: [PATCH 04/32] riscv: dts: sophgo: sg2044: Add GPIO device The GPIO controller is a standard Synopsys IP, which is already supported by the kernel. Add GPIO DT node for SG2044 SoC. Link: https://lore.kernel.org/r/20250608232836.784737-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 70 ++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index d21a59948186..70d1096f959f 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include "sg2044-cpus.dtsi" #include "sg2044-reset.h" @@ -90,6 +91,75 @@ uart3: serial@7030003000 { status = "disabled"; }; + gpio0: gpio@7040009000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x70 0x40009000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_GATE_APB_GPIO>, + <&clk CLK_GATE_GPIO_DB>; + clock-names = "bus", "db"; + resets = <&rst RST_GPIO0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@704000a000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x70 0x4000a000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_GATE_APB_GPIO>, + <&clk CLK_GATE_GPIO_DB>; + clock-names = "bus", "db"; + resets = <&rst RST_GPIO1>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio2: gpio@704000b000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x70 0x4000b000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_GATE_APB_GPIO>, + <&clk CLK_GATE_GPIO_DB>; + clock-names = "bus", "db"; + resets = <&rst RST_GPIO2>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + syscon: syscon@7050000000 { compatible = "sophgo,sg2044-top-syscon", "syscon"; reg = <0x70 0x50000000 0x0 0x1000>; From 11350d2f88641c9108b82f64a4d57556a0429b67 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:28 +0800 Subject: [PATCH 05/32] riscv: dts: sophgo: sg2044: Add I2C device The I2C controller of SG2044 is a standard Synopsys IP, with one the ref clock is need. Add I2C DT node for SG2044 SoC. Link: https://lore.kernel.org/r/20250608232836.784737-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 56 ++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index 70d1096f959f..a25cbb78913d 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -91,6 +91,62 @@ uart3: serial@7030003000 { status = "disabled"; }; + i2c0: i2c@7040005000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40005000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + clocks = <&clk CLK_GATE_APB_I2C>; + clock-names = "ref"; + interrupt-parent = <&intc>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst RST_I2C0>; + status = "disabled"; + }; + + i2c1: i2c@7040006000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40006000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + clocks = <&clk CLK_GATE_APB_I2C>; + clock-names = "ref"; + interrupt-parent = <&intc>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst RST_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@7040007000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40007000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + clocks = <&clk CLK_GATE_APB_I2C>; + clock-names = "ref"; + interrupt-parent = <&intc>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst RST_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@7040008000 { + compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; + reg = <0x70 0x40008000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + clocks = <&clk CLK_GATE_APB_I2C>; + clock-names = "ref"; + interrupt-parent = <&intc>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst RST_I2C3>; + status = "disabled"; + }; + gpio0: gpio@7040009000 { compatible = "snps,dw-apb-gpio"; reg = <0x70 0x40009000 0x0 0x1000>; From f88aa1f14c6bccd9a498f842ed16155fe3279b23 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:29 +0800 Subject: [PATCH 06/32] riscv: dts: sophgo: sg2044: add DMA controller device The DMA controller of SG2044 is a standard Synopsys IP, which is already supported by the kernel. Add DMA controller DT node for SG2044. Link: https://lore.kernel.org/r/20250608232836.784737-6-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index a25cbb78913d..a4d2f8a13cc3 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -31,6 +31,26 @@ soc { #size-cells = <2>; ranges; + dmac0: dma-controller@7020000000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x70 0x20000000 0x0 0x10000>; + #dma-cells = <1>; + clock-names = "core-clk", "cfgr-clk"; + clocks = <&clk CLK_GATE_SYSDMA_AXI>, + <&clk CLK_GATE_SYSDMA_AXI>; + dma-noncoherent; + interrupt-parent = <&intc>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + snps,priority = <0 1 2 3 4 5 6 7>; + snps,block-size = <4096 4096 4096 4096 + 4096 4096 4096 4096>; + snps,dma-masters = <2>; + snps,data-width = <2>; + snps,axi-max-burst-len = <4>; + status = "disabled"; + }; + uart0: serial@7030000000 { compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; reg = <0x70 0x30000000 0x0 0x1000>; From ddaa0b550022fd56167a592e23b9aa0b737753f5 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:30 +0800 Subject: [PATCH 07/32] riscv: dts: sophgo: sg2044: Add MMC controller device Add emmc controller and sd controller DT node for SG2044. Link: https://lore.kernel.org/r/20250608232836.784737-7-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 17 +++++++++++++ arch/riscv/boot/dts/sophgo/sg2044.dtsi | 24 +++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index 54cdf4239d5f..d077923097e8 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -27,6 +27,23 @@ &osc { clock-frequency = <25000000>; }; +&emmc { + bus-width = <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status = "okay"; +}; + +&sd { + bus-width = <4>; + no-sdio; + no-mmc; + wp-inverted; + status = "okay"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index a4d2f8a13cc3..6067901cde1e 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -111,6 +111,30 @@ uart3: serial@7030003000 { status = "disabled"; }; + emmc: mmc@703000a000 { + compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc"; + reg = <0x70 0x3000a000 0x0 0x1000>; + clocks = <&clk CLK_GATE_EMMC>, + <&clk CLK_GATE_AXI_EMMC>, + <&clk CLK_GATE_EMMC_100K>; + clock-names = "core", "bus", "timer"; + interrupt-parent = <&intc>; + interrupts = <298 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sd: mmc@703000b000 { + compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc"; + reg = <0x70 0x3000b000 0x0 0x1000>; + clocks = <&clk CLK_GATE_SD>, + <&clk CLK_GATE_AXI_SD>, + <&clk CLK_GATE_SD_100K>; + clock-names = "core", "bus", "timer"; + interrupt-parent = <&intc>; + interrupts = <300 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c0: i2c@7040005000 { compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; reg = <0x70 0x40005000 0x0 0x1000>; From 2b09dad74e5ab2e20772a9a7293c40ea64bcd936 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:31 +0800 Subject: [PATCH 08/32] riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device Add MCU devicetree node for Sophgo SRD3-10 board. This is used to provide SUSP function for the board. Link: https://lore.kernel.org/r/20250608232836.784737-8-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index d077923097e8..75564b2719cd 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -36,6 +36,16 @@ &emmc { status = "okay"; }; +&i2c1 { + status = "okay"; + + mcu: syscon@17 { + compatible = "sophgo,sg2044-hwmon-mcu", "sophgo,sg2042-hwmon-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; +}; + &sd { bus-width = <4>; no-sdio; From 2c7ef3dc129f5c6697101cfe75cdcdc3afb4d672 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:32 +0800 Subject: [PATCH 09/32] riscv: dts: sophgo: sg2044: Add ethernet control device Add ethernet control node for sg2044. Link: https://lore.kernel.org/r/20250608232836.784737-9-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 17 +++++ arch/riscv/boot/dts/sophgo/sg2044.dtsi | 62 +++++++++++++++++++ 2 files changed, 79 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index 75564b2719cd..01340f21848f 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -36,6 +36,23 @@ &emmc { status = "okay"; }; +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&porta 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + rx-internal-delay-ps = <2050>; + }; + }; +}; + &i2c1 { status = "okay"; diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index 6067901cde1e..bbf4191fb87d 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -111,6 +111,68 @@ uart3: serial@7030003000 { status = "disabled"; }; + gmac0: ethernet@7030006000 { + compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a"; + reg = <0x70 0x30006000 0x0 0x4000>; + clocks = <&clk CLK_GATE_AXI_ETH0>, + <&clk CLK_GATE_PTP_REF_I_ETH0>, + <&clk CLK_GATE_TX_ETH0>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + dma-noncoherent; + interrupt-parent = <&intc>; + interrupts = <296 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&rst RST_ETH0>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + snps,aal; + snps,tso; + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-wsp; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <16 8 4 0 0 0 0>; + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <2>; + }; + }; + emmc: mmc@703000a000 { compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc"; reg = <0x70 0x3000a000 0x0 0x1000>; From c20e152a08681e6bb5dfefed9acc768ecc859c41 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 9 Jun 2025 07:28:33 +0800 Subject: [PATCH 10/32] riscv: dts: sophgo: sg2044: Add pinctrl device Add pinctrl DT node and configuration for SG2044. Link: https://lore.kernel.org/r/20250608232836.784737-10-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index bbf4191fb87d..be20efd8e2ac 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "sg2044-cpus.dtsi" #include "sg2044-reset.h" @@ -329,6 +330,11 @@ syscon: syscon@7050000000 { clocks = <&osc>; }; + pinctrl: pinctrl@7050001000 { + compatible = "sophgo,sg2044-pinctrl"; + reg = <0x70 0x50001000 0x0 0x1000>; + }; + clk: clock-controller@7050002000 { compatible = "sophgo,sg2044-clk"; reg = <0x70 0x50002000 0x0 0x1000>; From 162b265ce05ec02e0909ef5e1de6483f1e1c78f4 Mon Sep 17 00:00:00 2001 From: Longbin Li Date: Mon, 9 Jun 2025 07:28:34 +0800 Subject: [PATCH 11/32] riscv: dts: sophgo: add SG2044 SPI NOR controller driver Add SPI NOR device node for SG2044. Signed-off-by: Longbin Li Link: https://lore.kernel.org/r/20250608232836.784737-11-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index be20efd8e2ac..b65e491deb8f 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -32,6 +32,30 @@ soc { #size-cells = <2>; ranges; + spifmc0: spi@7001000000 { + compatible = "sophgo,sg2044-spifmc-nor"; + reg = <0x70 0x01000000 0x0 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_GATE_AHB_SPIFMC>; + interrupt-parent = <&intc>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst RST_SPIFMC0>; + status = "disabled"; + }; + + spifmc1: spi@7005000000 { + compatible = "sophgo,sg2044-spifmc-nor"; + reg = <0x70 0x05000000 0x0 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk CLK_GATE_AHB_SPIFMC>; + interrupt-parent = <&intc>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst RST_SPIFMC1>; + status = "disabled"; + }; + dmac0: dma-controller@7020000000 { compatible = "snps,axi-dma-1.01a"; reg = <0x70 0x20000000 0x0 0x10000>; From ff9089739784a9766487672b98c8c2caa9aa659b Mon Sep 17 00:00:00 2001 From: Longbin Li Date: Mon, 9 Jun 2025 07:28:35 +0800 Subject: [PATCH 12/32] riscv: dts: sophgo: add pwm controller for SG2044 Add pwm device node for SG2044. Signed-off-by: Longbin Li Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250608232836.784737-12-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ arch/riscv/boot/dts/sophgo/sg2044.dtsi | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index 01340f21848f..b50c3a872d8b 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -63,6 +63,10 @@ mcu: syscon@17 { }; }; +&pwm { + status = "okay"; +}; + &sd { bus-width = <4>; no-sdio; diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index b65e491deb8f..f88cabe75790 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -347,6 +347,16 @@ portc: gpio-controller@0 { }; }; + pwm: pwm@704000c000 { + compatible = "sophgo,sg2044-pwm"; + reg = <0x70 0x4000c000 0x0 0x1000>; + #pwm-cells = <3>; + clocks = <&clk CLK_GATE_APB_PWM>; + clock-names = "apb"; + resets = <&rst RST_PWM>; + status = "disabled"; + }; + syscon: syscon@7050000000 { compatible = "sophgo,sg2044-top-syscon", "syscon"; reg = <0x70 0x50000000 0x0 0x1000>; From 02d548e553d161813b7d3702a311b9067806057d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 13 Jun 2025 15:45:12 +0800 Subject: [PATCH 13/32] riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property The kernel complains no "riscv,cbop-block-size" and disables the Zicbop extension. Add the missing property to keep it functional. Fixes: ae5bac370ed4 ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10") Link: https://lore.kernel.org/r/20250613074513.1683624-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 64 +++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 2a4267078ce6..6a35ed8f253c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -38,6 +38,7 @@ cpu0: cpu@0 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu0_intc: interrupt-controller { @@ -73,6 +74,7 @@ cpu1: cpu@1 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu1_intc: interrupt-controller { @@ -108,6 +110,7 @@ cpu2: cpu@2 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu2_intc: interrupt-controller { @@ -143,6 +146,7 @@ cpu3: cpu@3 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu3_intc: interrupt-controller { @@ -178,6 +182,7 @@ cpu4: cpu@4 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu4_intc: interrupt-controller { @@ -213,6 +218,7 @@ cpu5: cpu@5 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu5_intc: interrupt-controller { @@ -248,6 +254,7 @@ cpu6: cpu@6 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu6_intc: interrupt-controller { @@ -283,6 +290,7 @@ cpu7: cpu@7 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu7_intc: interrupt-controller { @@ -318,6 +326,7 @@ cpu8: cpu@8 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu8_intc: interrupt-controller { @@ -353,6 +362,7 @@ cpu9: cpu@9 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu9_intc: interrupt-controller { @@ -388,6 +398,7 @@ cpu10: cpu@10 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu10_intc: interrupt-controller { @@ -423,6 +434,7 @@ cpu11: cpu@11 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu11_intc: interrupt-controller { @@ -458,6 +470,7 @@ cpu12: cpu@12 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu12_intc: interrupt-controller { @@ -493,6 +506,7 @@ cpu13: cpu@13 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu13_intc: interrupt-controller { @@ -528,6 +542,7 @@ cpu14: cpu@14 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu14_intc: interrupt-controller { @@ -563,6 +578,7 @@ cpu15: cpu@15 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu15_intc: interrupt-controller { @@ -598,6 +614,7 @@ cpu16: cpu@16 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu16_intc: interrupt-controller { @@ -633,6 +650,7 @@ cpu17: cpu@17 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu17_intc: interrupt-controller { @@ -668,6 +686,7 @@ cpu18: cpu@18 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu18_intc: interrupt-controller { @@ -703,6 +722,7 @@ cpu19: cpu@19 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu19_intc: interrupt-controller { @@ -738,6 +758,7 @@ cpu20: cpu@20 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu20_intc: interrupt-controller { @@ -773,6 +794,7 @@ cpu21: cpu@21 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu21_intc: interrupt-controller { @@ -808,6 +830,7 @@ cpu22: cpu@22 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu22_intc: interrupt-controller { @@ -843,6 +866,7 @@ cpu23: cpu@23 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu23_intc: interrupt-controller { @@ -878,6 +902,7 @@ cpu24: cpu@24 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu24_intc: interrupt-controller { @@ -913,6 +938,7 @@ cpu25: cpu@25 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu25_intc: interrupt-controller { @@ -948,6 +974,7 @@ cpu26: cpu@26 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu26_intc: interrupt-controller { @@ -983,6 +1010,7 @@ cpu27: cpu@27 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu27_intc: interrupt-controller { @@ -1018,6 +1046,7 @@ cpu28: cpu@28 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu28_intc: interrupt-controller { @@ -1053,6 +1082,7 @@ cpu29: cpu@29 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu29_intc: interrupt-controller { @@ -1088,6 +1118,7 @@ cpu30: cpu@30 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu30_intc: interrupt-controller { @@ -1123,6 +1154,7 @@ cpu31: cpu@31 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu31_intc: interrupt-controller { @@ -1158,6 +1190,7 @@ cpu32: cpu@32 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu32_intc: interrupt-controller { @@ -1193,6 +1226,7 @@ cpu33: cpu@33 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu33_intc: interrupt-controller { @@ -1228,6 +1262,7 @@ cpu34: cpu@34 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu34_intc: interrupt-controller { @@ -1263,6 +1298,7 @@ cpu35: cpu@35 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu35_intc: interrupt-controller { @@ -1298,6 +1334,7 @@ cpu36: cpu@36 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu36_intc: interrupt-controller { @@ -1333,6 +1370,7 @@ cpu37: cpu@37 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu37_intc: interrupt-controller { @@ -1368,6 +1406,7 @@ cpu38: cpu@38 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu38_intc: interrupt-controller { @@ -1403,6 +1442,7 @@ cpu39: cpu@39 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu39_intc: interrupt-controller { @@ -1438,6 +1478,7 @@ cpu40: cpu@40 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu40_intc: interrupt-controller { @@ -1473,6 +1514,7 @@ cpu41: cpu@41 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu41_intc: interrupt-controller { @@ -1508,6 +1550,7 @@ cpu42: cpu@42 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu42_intc: interrupt-controller { @@ -1543,6 +1586,7 @@ cpu43: cpu@43 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu43_intc: interrupt-controller { @@ -1578,6 +1622,7 @@ cpu44: cpu@44 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu44_intc: interrupt-controller { @@ -1613,6 +1658,7 @@ cpu45: cpu@45 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu45_intc: interrupt-controller { @@ -1648,6 +1694,7 @@ cpu46: cpu@46 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu46_intc: interrupt-controller { @@ -1683,6 +1730,7 @@ cpu47: cpu@47 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu47_intc: interrupt-controller { @@ -1718,6 +1766,7 @@ cpu48: cpu@48 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu48_intc: interrupt-controller { @@ -1753,6 +1802,7 @@ cpu49: cpu@49 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu49_intc: interrupt-controller { @@ -1788,6 +1838,7 @@ cpu50: cpu@50 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu50_intc: interrupt-controller { @@ -1823,6 +1874,7 @@ cpu51: cpu@51 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu51_intc: interrupt-controller { @@ -1858,6 +1910,7 @@ cpu52: cpu@52 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu52_intc: interrupt-controller { @@ -1893,6 +1946,7 @@ cpu53: cpu@53 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu53_intc: interrupt-controller { @@ -1928,6 +1982,7 @@ cpu54: cpu@54 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu54_intc: interrupt-controller { @@ -1963,6 +2018,7 @@ cpu55: cpu@55 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu55_intc: interrupt-controller { @@ -1998,6 +2054,7 @@ cpu56: cpu@56 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu56_intc: interrupt-controller { @@ -2033,6 +2090,7 @@ cpu57: cpu@57 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu57_intc: interrupt-controller { @@ -2068,6 +2126,7 @@ cpu58: cpu@58 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu58_intc: interrupt-controller { @@ -2103,6 +2162,7 @@ cpu59: cpu@59 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu59_intc: interrupt-controller { @@ -2138,6 +2198,7 @@ cpu60: cpu@60 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu60_intc: interrupt-controller { @@ -2173,6 +2234,7 @@ cpu61: cpu@61 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu61_intc: interrupt-controller { @@ -2208,6 +2270,7 @@ cpu62: cpu@62 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu62_intc: interrupt-controller { @@ -2243,6 +2306,7 @@ cpu63: cpu@63 { "zvfbfmin", "zvfbfwma", "zvfh", "zvfhmin"; riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; riscv,cboz-block-size = <64>; cpu63_intc: interrupt-controller { From 610f943a66bee95101f329d8a8e9a4a82123a66c Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Thu, 12 Jun 2025 15:28:09 +0200 Subject: [PATCH 14/32] dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 Move sophgo.yaml from riscv into soc/sophgo so that it can be shared for all SoCs containing ARM cores as well. This already applies to SG2002. Add SG2000 SoC, Milk-V Duo Module 01 and Milk-V Module 01 EVB. Reviewed-by: Chen Wang Reviewed-by: Inochi Amaoto Acked-by: Conor Dooley Signed-off-by: Alexander Sverdlin Link: https://lore.kernel.org/r/20250612132844.767216-2-alexander.sverdlin@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) rename Documentation/devicetree/bindings/{riscv => soc/sophgo}/sophgo.yaml (81%) diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml similarity index 81% rename from Documentation/devicetree/bindings/riscv/sophgo.yaml rename to Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml index b4c4d7a7d7ad..602c092b4ad5 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sophgo.yaml# +$id: http://devicetree.org/schemas/soc/sophgo/sophgo.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sophgo SoC-based boards @@ -26,6 +26,11 @@ properties: - enum: - sophgo,huashan-pi - const: sophgo,cv1812h + - items: + - enum: + - milkv,duo-module-01-evb + - const: milkv,duo-module-01 + - const: sophgo,sg2000 - items: - enum: - sipeed,licheerv-nano-b From f5742f67a47cc1bd44368706d41bb2657f8e487d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 17 Jun 2025 15:01:41 +0800 Subject: [PATCH 15/32] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC Add reset generator node for all CV18XX series SoC. Reviewed-by: Alexander Sverdlin Tested-by: Junhui Liu Tested-by: Alexander Sverdlin Link: https://lore.kernel.org/r/20250617070144.1149926-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 7 ++ arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 280c45bd3b3d..1000de865d07 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "cv18xx-reset.h" / { #address-cells = <1>; @@ -24,6 +25,12 @@ soc { #size-cells = <1>; ranges; + rst: reset-controller@3003000 { + compatible = "sophgo,cv1800b-reset"; + reg = <0x3003000 0x1000>; + #reset-cells = <1>; + }; + gpio0: gpio@3020000 { compatible = "snps,dw-apb-gpio"; reg = <0x3020000 0x1000>; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx-reset.h b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h new file mode 100644 index 000000000000..7e7c5ca2dbbd --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx-reset.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2025 Inochi Amaoto + */ + +#ifndef _SOPHGO_CV18XX_RESET +#define _SOPHGO_CV18XX_RESET + +#define RST_DDR 2 +#define RST_H264C 3 +#define RST_JPEG 4 +#define RST_H265C 5 +#define RST_VIPSYS 6 +#define RST_TDMA 7 +#define RST_TPU 8 +#define RST_TPUSYS 9 +#define RST_USB 11 +#define RST_ETH0 12 +#define RST_ETH1 13 +#define RST_NAND 14 +#define RST_EMMC 15 +#define RST_SD0 16 +#define RST_SDMA 18 +#define RST_I2S0 19 +#define RST_I2S1 20 +#define RST_I2S2 21 +#define RST_I2S3 22 +#define RST_UART0 23 +#define RST_UART1 24 +#define RST_UART2 25 +#define RST_UART3 26 +#define RST_I2C0 27 +#define RST_I2C1 28 +#define RST_I2C2 29 +#define RST_I2C3 30 +#define RST_I2C4 31 +#define RST_PWM0 32 +#define RST_PWM1 33 +#define RST_PWM2 34 +#define RST_PWM3 35 +#define RST_SPI0 40 +#define RST_SPI1 41 +#define RST_SPI2 42 +#define RST_SPI3 43 +#define RST_GPIO0 44 +#define RST_GPIO1 45 +#define RST_GPIO2 46 +#define RST_EFUSE 47 +#define RST_WDT 48 +#define RST_AHB_ROM 49 +#define RST_SPIC 50 +#define RST_TEMPSEN 51 +#define RST_SARADC 52 +#define RST_COMBO_PHY0 58 +#define RST_SPI_NAND 61 +#define RST_SE 62 +#define RST_UART4 74 +#define RST_GPIO3 75 +#define RST_SYSTEM 76 +#define RST_TIMER 77 +#define RST_TIMER0 78 +#define RST_TIMER1 79 +#define RST_TIMER2 80 +#define RST_TIMER3 81 +#define RST_TIMER4 82 +#define RST_TIMER5 83 +#define RST_TIMER6 84 +#define RST_TIMER7 85 +#define RST_WGN0 86 +#define RST_WGN1 87 +#define RST_WGN2 88 +#define RST_KEYSCAN 89 +#define RST_AUDDAC 91 +#define RST_AUDDAC_APB 92 +#define RST_AUDADC 93 +#define RST_VCSYS 95 +#define RST_ETHPHY 96 +#define RST_ETHPHY_APB 97 +#define RST_AUDSRC 98 +#define RST_VIP_CAM0 99 +#define RST_WDT1 100 +#define RST_WDT2 101 +#define RST_AUTOCLEAR_CPUCORE0 256 +#define RST_AUTOCLEAR_CPUCORE1 257 +#define RST_AUTOCLEAR_CPUCORE2 258 +#define RST_AUTOCLEAR_CPUCORE3 259 +#define RST_AUTOCLEAR_CPUSYS0 260 +#define RST_AUTOCLEAR_CPUSYS1 261 +#define RST_AUTOCLEAR_CPUSYS2 262 +#define RST_CPUCORE0 288 +#define RST_CPUCORE1 289 +#define RST_CPUCORE2 290 +#define RST_CPUCORE3 291 +#define RST_CPUSYS0 292 +#define RST_CPUSYS1 293 +#define RST_CPUSYS2 294 + +#endif /* _SOPHGO_CV18XX_RESET */ From 817c89a6b5c0df6e018857e1e540d86d38779d24 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 17 Jun 2025 15:01:42 +0800 Subject: [PATCH 16/32] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC Add known reset configuration for existed device. Reviewed-by: Alexander Sverdlin Link: https://lore.kernel.org/r/20250617070144.1149926-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 1000de865d07..9a25b8c6c2f3 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -36,6 +36,7 @@ gpio0: gpio@3020000 { reg = <0x3020000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO0>; porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -54,6 +55,7 @@ gpio1: gpio@3021000 { reg = <0x3021000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO1>; portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -72,6 +74,7 @@ gpio2: gpio@3022000 { reg = <0x3022000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO2>; portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -90,6 +93,7 @@ gpio3: gpio@3023000 { reg = <0x3023000 0x1000>; #address-cells = <1>; #size-cells = <0>; + resets = <&rst RST_GPIO3>; portd: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -133,6 +137,7 @@ i2c0: i2c@4000000 { clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C0>; status = "disabled"; }; @@ -144,6 +149,7 @@ i2c1: i2c@4010000 { clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C1>; status = "disabled"; }; @@ -155,6 +161,7 @@ i2c2: i2c@4020000 { clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C2>; status = "disabled"; }; @@ -166,6 +173,7 @@ i2c3: i2c@4030000 { clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C3>; status = "disabled"; }; @@ -177,6 +185,7 @@ i2c4: i2c@4040000 { clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; clock-names = "ref", "pclk"; interrupts = ; + resets = <&rst RST_I2C4>; status = "disabled"; }; @@ -188,6 +197,7 @@ uart0: serial@4140000 { clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART0>; status = "disabled"; }; @@ -199,6 +209,7 @@ uart1: serial@4150000 { clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART1>; status = "disabled"; }; @@ -210,6 +221,7 @@ uart2: serial@4160000 { clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART2>; status = "disabled"; }; @@ -221,6 +233,7 @@ uart3: serial@4170000 { clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART3>; status = "disabled"; }; @@ -232,6 +245,7 @@ spi0: spi@4180000 { clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI0>; status = "disabled"; }; @@ -243,6 +257,7 @@ spi1: spi@4190000 { clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI1>; status = "disabled"; }; @@ -254,6 +269,7 @@ spi2: spi@41a0000 { clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI2>; status = "disabled"; }; @@ -265,6 +281,7 @@ spi3: spi@41b0000 { clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; clock-names = "ssi_clk", "pclk"; interrupts = ; + resets = <&rst RST_SPI3>; status = "disabled"; }; @@ -276,6 +293,7 @@ uart4: serial@41c0000 { clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; + resets = <&rst RST_UART4>; status = "disabled"; }; From 7cc925594c10e18a6d99688aa008a8bc8b1e25d7 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 18 Jun 2025 09:58:48 +0800 Subject: [PATCH 17/32] riscv: dts: sophgo: sg2044: add MSI device support for SG2044 Add MSI device tree node for SG2044. Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250618015851.272188-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 4 ++++ arch/riscv/boot/dts/sophgo/sg2044.dtsi | 11 +++++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index b50c3a872d8b..c97bd62e5f06 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -63,6 +63,10 @@ mcu: syscon@17 { }; }; +&msi { + status = "okay"; +}; + &pwm { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index f88cabe75790..aae4539dea98 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -32,6 +32,17 @@ soc { #size-cells = <2>; ranges; + msi: msi-controller@6d50000000 { + compatible = "sophgo,sg2044-msi"; + reg = <0x6d 0x50000000 0x0 0x800>, + <0x0 0x7ee00000 0x0 0x40>; + reg-names = "clr", "doorbell"; + #msi-cells = <0>; + msi-controller; + msi-ranges = <&intc 352 IRQ_TYPE_LEVEL_HIGH 512>; + status = "disabled"; + }; + spifmc0: spi@7001000000 { compatible = "sophgo,sg2044-spifmc-nor"; reg = <0x70 0x01000000 0x0 0x4000000>; From 3309df45e6b5f1c1a9e91019054b7662d56ef31a Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 18 Jun 2025 09:58:49 +0800 Subject: [PATCH 18/32] riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 Add PCIe device node for SG2044 and configuration for Sophgo SRD3-10. Link: https://lore.kernel.org/r/20250618015851.272188-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 30 +++ arch/riscv/boot/dts/sophgo/sg2044.dtsi | 175 ++++++++++++++++++ 2 files changed, 205 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index c97bd62e5f06..1ca5fb707061 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -67,6 +67,36 @@ &msi { status = "okay"; }; +&pcie0 { + bus-range = <0x00 0xff>; + linux,pci-domain = <1>; + status = "okay"; +}; + +&pcie1 { + bus-range = <0x00 0xff>; + linux,pci-domain = <0>; + status = "okay"; +}; + +&pcie2 { + bus-range = <0x00 0xff>; + linux,pci-domain = <3>; + status = "okay"; +}; + +&pcie3 { + bus-range = <0x00 0xff>; + linux,pci-domain = <2>; + status = "okay"; +}; + +&pcie4 { + bus-range = <0x00 0xff>; + linux,pci-domain = <4>; + status = "okay"; +}; + &pwm { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi index aae4539dea98..6ec955744b0c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi @@ -32,6 +32,181 @@ soc { #size-cells = <2>; ranges; + pcie0: pcie@6c00000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x00000000 0x0 0x00001000>, + <0x6c 0x00300000 0x0 0x00004000>, + <0x48 0x00000000 0x0 0x00001000>, + <0x6c 0x000c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + clocks = <&clk CLK_GATE_PCIE_1G>; + clock-names = "core"; + device_type = "pci"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + msi-parent = <&msi>; + ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, + <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; + status = "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + }; + + pcie1: pcie@6c00400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x00400000 0x0 0x00001000>, + <0x6c 0x00700000 0x0 0x00004000>, + <0x40 0x00000000 0x0 0x00001000>, + <0x6c 0x00780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + clocks = <&clk CLK_GATE_PCIE_1G>; + clock-names = "core"; + device_type = "pci"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + msi-parent = <&msi>; + ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, + <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + status = "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + }; + + pcie2: pcie@6c04000000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04000000 0x0 0x00001000>, + <0x6c 0x04300000 0x0 0x00004000>, + <0x58 0x00000000 0x0 0x00001000>, + <0x6c 0x040c0000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + clocks = <&clk CLK_GATE_PCIE_1G>; + clock-names = "core"; + device_type = "pci"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + msi-parent = <&msi>; + ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, + <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, + <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, + <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; + status = "disabled"; + + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + }; + + pcie3: pcie@6c04400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x04400000 0x0 0x00001000>, + <0x6c 0x04700000 0x0 0x00004000>, + <0x50 0x00000000 0x0 0x00001000>, + <0x6c 0x04780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + clocks = <&clk CLK_GATE_PCIE_1G>; + clock-names = "core"; + device_type = "pci"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc3 0>, + <0 0 0 2 &pcie_intc3 1>, + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + msi-parent = <&msi>; + ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, + <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, + <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, + <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; + status = "disabled"; + + pcie_intc3: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + }; + + pcie4: pcie@6c08400000 { + compatible = "sophgo,sg2044-pcie"; + reg = <0x6c 0x08400000 0x0 0x00001000>, + <0x6c 0x08700000 0x0 0x00004000>, + <0x60 0x00000000 0x0 0x00001000>, + <0x6c 0x08780000 0x0 0x00001000>; + reg-names = "dbi", "atu", "config", "app"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + clocks = <&clk CLK_GATE_PCIE_1G>; + clock-names = "core"; + device_type = "pci"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc4 0>, + <0 0 0 2 &pcie_intc4 1>, + <0 0 0 3 &pcie_intc4 2>, + <0 0 0 4 &pcie_intc4 3>; + msi-parent = <&msi>; + ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>, + <0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>, + <0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>, + <0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>, + <0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>; + status = "disabled"; + + pcie_intc4: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + }; + msi: msi-controller@6d50000000 { compatible = "sophgo,sg2044-msi"; reg = <0x6d 0x50000000 0x0 0x800>, From a5fb9056f26011f24525f0083b9c1ad300413269 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 5 Jul 2025 15:00:12 +0800 Subject: [PATCH 19/32] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree The sg2042 SoCs support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2]. This can be tested by passing the "mitigations=off" kernel parameter. Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1] Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] Signed-off-by: Han Gao Reviewed-by: Inochi Amaoto Reviewed-by: Nutty Liu Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/915bef0530dee6c8bc0ae473837a4bd6786fa4fb.1751698574.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++------- 1 file changed, 128 insertions(+), 64 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c..dcc984965b6b 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -260,7 +260,8 @@ cpu0: cpu@0 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -285,7 +286,8 @@ cpu1: cpu@1 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -310,7 +312,8 @@ cpu2: cpu@2 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -335,7 +338,8 @@ cpu3: cpu@3 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -360,7 +364,8 @@ cpu4: cpu@4 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -385,7 +390,8 @@ cpu5: cpu@5 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -410,7 +416,8 @@ cpu6: cpu@6 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -435,7 +442,8 @@ cpu7: cpu@7 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -460,7 +468,8 @@ cpu8: cpu@8 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -485,7 +494,8 @@ cpu9: cpu@9 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -510,7 +520,8 @@ cpu10: cpu@10 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -535,7 +546,8 @@ cpu11: cpu@11 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -560,7 +572,8 @@ cpu12: cpu@12 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -585,7 +598,8 @@ cpu13: cpu@13 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -610,7 +624,8 @@ cpu14: cpu@14 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -635,7 +650,8 @@ cpu15: cpu@15 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -660,7 +676,8 @@ cpu16: cpu@16 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -685,7 +702,8 @@ cpu17: cpu@17 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -710,7 +728,8 @@ cpu18: cpu@18 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -735,7 +754,8 @@ cpu19: cpu@19 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -760,7 +780,8 @@ cpu20: cpu@20 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -785,7 +806,8 @@ cpu21: cpu@21 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -810,7 +832,8 @@ cpu22: cpu@22 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -835,7 +858,8 @@ cpu23: cpu@23 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -860,7 +884,8 @@ cpu24: cpu@24 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -885,7 +910,8 @@ cpu25: cpu@25 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -910,7 +936,8 @@ cpu26: cpu@26 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -935,7 +962,8 @@ cpu27: cpu@27 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -960,7 +988,8 @@ cpu28: cpu@28 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -985,7 +1014,8 @@ cpu29: cpu@29 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1010,7 +1040,8 @@ cpu30: cpu@30 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1035,7 +1066,8 @@ cpu31: cpu@31 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1060,7 +1092,8 @@ cpu32: cpu@32 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1085,7 +1118,8 @@ cpu33: cpu@33 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1110,7 +1144,8 @@ cpu34: cpu@34 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1135,7 +1170,8 @@ cpu35: cpu@35 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1160,7 +1196,8 @@ cpu36: cpu@36 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1185,7 +1222,8 @@ cpu37: cpu@37 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1210,7 +1248,8 @@ cpu38: cpu@38 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1235,7 +1274,8 @@ cpu39: cpu@39 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1260,7 +1300,8 @@ cpu40: cpu@40 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1285,7 +1326,8 @@ cpu41: cpu@41 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1310,7 +1352,8 @@ cpu42: cpu@42 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1335,7 +1378,8 @@ cpu43: cpu@43 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1360,7 +1404,8 @@ cpu44: cpu@44 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1385,7 +1430,8 @@ cpu45: cpu@45 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1410,7 +1456,8 @@ cpu46: cpu@46 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1435,7 +1482,8 @@ cpu47: cpu@47 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1460,7 +1508,8 @@ cpu48: cpu@48 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1485,7 +1534,8 @@ cpu49: cpu@49 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1510,7 +1560,8 @@ cpu50: cpu@50 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1535,7 +1586,8 @@ cpu51: cpu@51 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1560,7 +1612,8 @@ cpu52: cpu@52 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1585,7 +1638,8 @@ cpu53: cpu@53 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1610,7 +1664,8 @@ cpu54: cpu@54 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1635,7 +1690,8 @@ cpu55: cpu@55 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1660,7 +1716,8 @@ cpu56: cpu@56 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1685,7 +1742,8 @@ cpu57: cpu@57 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1710,7 +1768,8 @@ cpu58: cpu@58 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1735,7 +1794,8 @@ cpu59: cpu@59 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1760,7 +1820,8 @@ cpu60: cpu@60 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1785,7 +1846,8 @@ cpu61: cpu@61 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1810,7 +1872,8 @@ cpu62: cpu@62 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1835,7 +1898,8 @@ cpu63: cpu@63 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>; From 6ebff712f4b4be64a80b405fd263c11f522069ab Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 5 Jul 2025 15:00:13 +0800 Subject: [PATCH 20/32] riscv: dts: sophgo: add ziccrse for sg2042 sg2042 support Ziccrse ISA extension [1]. Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1] Signed-off-by: Han Gao Reviewed-by: Inochi Amaoto Reviewed-by: Nutty Liu Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/859df9a05e1693fec9bd2c7dcf14415bb15230bd.1751698574.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 320 ++++++++++++-------- 1 file changed, 192 insertions(+), 128 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index dcc984965b6b..f483f62ab0c4 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -259,8 +259,9 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <0>; i-cache-block-size = <64>; @@ -285,8 +286,9 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <1>; i-cache-block-size = <64>; @@ -311,8 +313,9 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <2>; i-cache-block-size = <64>; @@ -337,8 +340,9 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <3>; i-cache-block-size = <64>; @@ -363,8 +367,9 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <4>; i-cache-block-size = <64>; @@ -389,8 +394,9 @@ cpu5: cpu@5 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <5>; i-cache-block-size = <64>; @@ -415,8 +421,9 @@ cpu6: cpu@6 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <6>; i-cache-block-size = <64>; @@ -441,8 +448,9 @@ cpu7: cpu@7 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <7>; i-cache-block-size = <64>; @@ -467,8 +475,9 @@ cpu8: cpu@8 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <8>; i-cache-block-size = <64>; @@ -493,8 +502,9 @@ cpu9: cpu@9 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <9>; i-cache-block-size = <64>; @@ -519,8 +529,9 @@ cpu10: cpu@10 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <10>; i-cache-block-size = <64>; @@ -545,8 +556,9 @@ cpu11: cpu@11 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <11>; i-cache-block-size = <64>; @@ -571,8 +583,9 @@ cpu12: cpu@12 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <12>; i-cache-block-size = <64>; @@ -597,8 +610,9 @@ cpu13: cpu@13 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <13>; i-cache-block-size = <64>; @@ -623,8 +637,9 @@ cpu14: cpu@14 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <14>; i-cache-block-size = <64>; @@ -649,8 +664,9 @@ cpu15: cpu@15 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <15>; i-cache-block-size = <64>; @@ -675,8 +691,9 @@ cpu16: cpu@16 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <16>; i-cache-block-size = <64>; @@ -701,8 +718,9 @@ cpu17: cpu@17 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <17>; i-cache-block-size = <64>; @@ -727,8 +745,9 @@ cpu18: cpu@18 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <18>; i-cache-block-size = <64>; @@ -753,8 +772,9 @@ cpu19: cpu@19 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <19>; i-cache-block-size = <64>; @@ -779,8 +799,9 @@ cpu20: cpu@20 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <20>; i-cache-block-size = <64>; @@ -805,8 +826,9 @@ cpu21: cpu@21 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <21>; i-cache-block-size = <64>; @@ -831,8 +853,9 @@ cpu22: cpu@22 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <22>; i-cache-block-size = <64>; @@ -857,8 +880,9 @@ cpu23: cpu@23 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <23>; i-cache-block-size = <64>; @@ -883,8 +907,9 @@ cpu24: cpu@24 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <24>; i-cache-block-size = <64>; @@ -909,8 +934,9 @@ cpu25: cpu@25 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <25>; i-cache-block-size = <64>; @@ -935,8 +961,9 @@ cpu26: cpu@26 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <26>; i-cache-block-size = <64>; @@ -961,8 +988,9 @@ cpu27: cpu@27 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <27>; i-cache-block-size = <64>; @@ -987,8 +1015,9 @@ cpu28: cpu@28 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <28>; i-cache-block-size = <64>; @@ -1013,8 +1042,9 @@ cpu29: cpu@29 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <29>; i-cache-block-size = <64>; @@ -1039,8 +1069,9 @@ cpu30: cpu@30 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <30>; i-cache-block-size = <64>; @@ -1065,8 +1096,9 @@ cpu31: cpu@31 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <31>; i-cache-block-size = <64>; @@ -1091,8 +1123,9 @@ cpu32: cpu@32 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <32>; i-cache-block-size = <64>; @@ -1117,8 +1150,9 @@ cpu33: cpu@33 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <33>; i-cache-block-size = <64>; @@ -1143,8 +1177,9 @@ cpu34: cpu@34 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <34>; i-cache-block-size = <64>; @@ -1169,8 +1204,9 @@ cpu35: cpu@35 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <35>; i-cache-block-size = <64>; @@ -1195,8 +1231,9 @@ cpu36: cpu@36 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <36>; i-cache-block-size = <64>; @@ -1221,8 +1258,9 @@ cpu37: cpu@37 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <37>; i-cache-block-size = <64>; @@ -1247,8 +1285,9 @@ cpu38: cpu@38 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <38>; i-cache-block-size = <64>; @@ -1273,8 +1312,9 @@ cpu39: cpu@39 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <39>; i-cache-block-size = <64>; @@ -1299,8 +1339,9 @@ cpu40: cpu@40 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <40>; i-cache-block-size = <64>; @@ -1325,8 +1366,9 @@ cpu41: cpu@41 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <41>; i-cache-block-size = <64>; @@ -1351,8 +1393,9 @@ cpu42: cpu@42 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <42>; i-cache-block-size = <64>; @@ -1377,8 +1420,9 @@ cpu43: cpu@43 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <43>; i-cache-block-size = <64>; @@ -1403,8 +1447,9 @@ cpu44: cpu@44 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <44>; i-cache-block-size = <64>; @@ -1429,8 +1474,9 @@ cpu45: cpu@45 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <45>; i-cache-block-size = <64>; @@ -1455,8 +1501,9 @@ cpu46: cpu@46 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <46>; i-cache-block-size = <64>; @@ -1481,8 +1528,9 @@ cpu47: cpu@47 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <47>; i-cache-block-size = <64>; @@ -1507,8 +1555,9 @@ cpu48: cpu@48 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <48>; i-cache-block-size = <64>; @@ -1533,8 +1582,9 @@ cpu49: cpu@49 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <49>; i-cache-block-size = <64>; @@ -1559,8 +1609,9 @@ cpu50: cpu@50 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <50>; i-cache-block-size = <64>; @@ -1585,8 +1636,9 @@ cpu51: cpu@51 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <51>; i-cache-block-size = <64>; @@ -1611,8 +1663,9 @@ cpu52: cpu@52 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <52>; i-cache-block-size = <64>; @@ -1637,8 +1690,9 @@ cpu53: cpu@53 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <53>; i-cache-block-size = <64>; @@ -1663,8 +1717,9 @@ cpu54: cpu@54 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <54>; i-cache-block-size = <64>; @@ -1689,8 +1744,9 @@ cpu55: cpu@55 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <55>; i-cache-block-size = <64>; @@ -1715,8 +1771,9 @@ cpu56: cpu@56 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <56>; i-cache-block-size = <64>; @@ -1741,8 +1798,9 @@ cpu57: cpu@57 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <57>; i-cache-block-size = <64>; @@ -1767,8 +1825,9 @@ cpu58: cpu@58 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <58>; i-cache-block-size = <64>; @@ -1793,8 +1852,9 @@ cpu59: cpu@59 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <59>; i-cache-block-size = <64>; @@ -1819,8 +1879,9 @@ cpu60: cpu@60 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <60>; i-cache-block-size = <64>; @@ -1845,8 +1906,9 @@ cpu61: cpu@61 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <61>; i-cache-block-size = <64>; @@ -1871,8 +1933,9 @@ cpu62: cpu@62 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <62>; i-cache-block-size = <64>; @@ -1897,8 +1960,9 @@ cpu63: cpu@63 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <63>; i-cache-block-size = <64>; From cb074bed1186984f128e3719ee54ca529aba1b56 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 5 Jul 2025 15:00:14 +0800 Subject: [PATCH 21/32] riscv: dts: sophgo: add zfh for sg2042 sg2042 support Zfh ISA extension [1]. Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1] Signed-off-by: Han Gao Reviewed-by: Inochi Amaoto Reviewed-by: Nutty Liu Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/bcaf5684c614959f49a9770bf3cd41096cee5fe6.1751698574.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++---------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index f483f62ab0c4..77ded5304272 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -260,7 +260,7 @@ cpu0: cpu@0 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <0>; @@ -287,7 +287,7 @@ cpu1: cpu@1 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <1>; @@ -314,7 +314,7 @@ cpu2: cpu@2 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <2>; @@ -341,7 +341,7 @@ cpu3: cpu@3 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <3>; @@ -368,7 +368,7 @@ cpu4: cpu@4 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <4>; @@ -395,7 +395,7 @@ cpu5: cpu@5 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <5>; @@ -422,7 +422,7 @@ cpu6: cpu@6 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <6>; @@ -449,7 +449,7 @@ cpu7: cpu@7 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <7>; @@ -476,7 +476,7 @@ cpu8: cpu@8 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <8>; @@ -503,7 +503,7 @@ cpu9: cpu@9 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <9>; @@ -530,7 +530,7 @@ cpu10: cpu@10 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <10>; @@ -557,7 +557,7 @@ cpu11: cpu@11 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <11>; @@ -584,7 +584,7 @@ cpu12: cpu@12 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <12>; @@ -611,7 +611,7 @@ cpu13: cpu@13 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <13>; @@ -638,7 +638,7 @@ cpu14: cpu@14 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <14>; @@ -665,7 +665,7 @@ cpu15: cpu@15 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <15>; @@ -692,7 +692,7 @@ cpu16: cpu@16 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <16>; @@ -719,7 +719,7 @@ cpu17: cpu@17 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <17>; @@ -746,7 +746,7 @@ cpu18: cpu@18 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <18>; @@ -773,7 +773,7 @@ cpu19: cpu@19 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <19>; @@ -800,7 +800,7 @@ cpu20: cpu@20 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <20>; @@ -827,7 +827,7 @@ cpu21: cpu@21 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <21>; @@ -854,7 +854,7 @@ cpu22: cpu@22 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <22>; @@ -881,7 +881,7 @@ cpu23: cpu@23 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <23>; @@ -908,7 +908,7 @@ cpu24: cpu@24 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <24>; @@ -935,7 +935,7 @@ cpu25: cpu@25 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <25>; @@ -962,7 +962,7 @@ cpu26: cpu@26 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <26>; @@ -989,7 +989,7 @@ cpu27: cpu@27 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <27>; @@ -1016,7 +1016,7 @@ cpu28: cpu@28 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <28>; @@ -1043,7 +1043,7 @@ cpu29: cpu@29 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <29>; @@ -1070,7 +1070,7 @@ cpu30: cpu@30 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <30>; @@ -1097,7 +1097,7 @@ cpu31: cpu@31 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <31>; @@ -1124,7 +1124,7 @@ cpu32: cpu@32 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <32>; @@ -1151,7 +1151,7 @@ cpu33: cpu@33 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <33>; @@ -1178,7 +1178,7 @@ cpu34: cpu@34 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <34>; @@ -1205,7 +1205,7 @@ cpu35: cpu@35 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <35>; @@ -1232,7 +1232,7 @@ cpu36: cpu@36 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <36>; @@ -1259,7 +1259,7 @@ cpu37: cpu@37 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <37>; @@ -1286,7 +1286,7 @@ cpu38: cpu@38 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <38>; @@ -1313,7 +1313,7 @@ cpu39: cpu@39 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <39>; @@ -1340,7 +1340,7 @@ cpu40: cpu@40 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <40>; @@ -1367,7 +1367,7 @@ cpu41: cpu@41 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <41>; @@ -1394,7 +1394,7 @@ cpu42: cpu@42 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <42>; @@ -1421,7 +1421,7 @@ cpu43: cpu@43 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <43>; @@ -1448,7 +1448,7 @@ cpu44: cpu@44 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <44>; @@ -1475,7 +1475,7 @@ cpu45: cpu@45 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <45>; @@ -1502,7 +1502,7 @@ cpu46: cpu@46 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <46>; @@ -1529,7 +1529,7 @@ cpu47: cpu@47 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <47>; @@ -1556,7 +1556,7 @@ cpu48: cpu@48 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <48>; @@ -1583,7 +1583,7 @@ cpu49: cpu@49 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <49>; @@ -1610,7 +1610,7 @@ cpu50: cpu@50 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <50>; @@ -1637,7 +1637,7 @@ cpu51: cpu@51 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <51>; @@ -1664,7 +1664,7 @@ cpu52: cpu@52 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <52>; @@ -1691,7 +1691,7 @@ cpu53: cpu@53 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <53>; @@ -1718,7 +1718,7 @@ cpu54: cpu@54 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <54>; @@ -1745,7 +1745,7 @@ cpu55: cpu@55 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <55>; @@ -1772,7 +1772,7 @@ cpu56: cpu@56 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <56>; @@ -1799,7 +1799,7 @@ cpu57: cpu@57 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <57>; @@ -1826,7 +1826,7 @@ cpu58: cpu@58 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <58>; @@ -1853,7 +1853,7 @@ cpu59: cpu@59 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <59>; @@ -1880,7 +1880,7 @@ cpu60: cpu@60 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <60>; @@ -1907,7 +1907,7 @@ cpu61: cpu@61 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <61>; @@ -1934,7 +1934,7 @@ cpu62: cpu@62 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <62>; @@ -1961,7 +1961,7 @@ cpu63: cpu@63 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <63>; From a1de92f0cd4118652ec94a6c3be62d7571029a9b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Mon, 7 Jul 2025 11:15:18 +0800 Subject: [PATCH 22/32] riscv: dts: sophgo: sg2044: add ziccrse extension sg2044 support ziccrse extension. Signed-off-by: Han Gao Reviewed-by: Chen Wang Reviewed-by: Nutty Liu Link: https://lore.kernel.org/r/0889174f2e013e095b94940614f4a0a6e614b09c.1751858054.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 128 ++++++++++---------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 6a35ed8f253c..0d71a167ed22 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -32,7 +32,7 @@ cpu0: cpu@0 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -68,7 +68,7 @@ cpu1: cpu@1 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -104,7 +104,7 @@ cpu2: cpu@2 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -140,7 +140,7 @@ cpu3: cpu@3 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -176,7 +176,7 @@ cpu4: cpu@4 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -212,7 +212,7 @@ cpu5: cpu@5 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -248,7 +248,7 @@ cpu6: cpu@6 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -284,7 +284,7 @@ cpu7: cpu@7 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -320,7 +320,7 @@ cpu8: cpu@8 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -356,7 +356,7 @@ cpu9: cpu@9 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -392,7 +392,7 @@ cpu10: cpu@10 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -428,7 +428,7 @@ cpu11: cpu@11 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -464,7 +464,7 @@ cpu12: cpu@12 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -500,7 +500,7 @@ cpu13: cpu@13 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -536,7 +536,7 @@ cpu14: cpu@14 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -572,7 +572,7 @@ cpu15: cpu@15 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -608,7 +608,7 @@ cpu16: cpu@16 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -644,7 +644,7 @@ cpu17: cpu@17 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -680,7 +680,7 @@ cpu18: cpu@18 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -716,7 +716,7 @@ cpu19: cpu@19 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -752,7 +752,7 @@ cpu20: cpu@20 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -788,7 +788,7 @@ cpu21: cpu@21 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -824,7 +824,7 @@ cpu22: cpu@22 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -860,7 +860,7 @@ cpu23: cpu@23 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -896,7 +896,7 @@ cpu24: cpu@24 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -932,7 +932,7 @@ cpu25: cpu@25 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -968,7 +968,7 @@ cpu26: cpu@26 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1004,7 +1004,7 @@ cpu27: cpu@27 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1040,7 +1040,7 @@ cpu28: cpu@28 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1076,7 +1076,7 @@ cpu29: cpu@29 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1112,7 +1112,7 @@ cpu30: cpu@30 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1148,7 +1148,7 @@ cpu31: cpu@31 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1184,7 +1184,7 @@ cpu32: cpu@32 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1220,7 +1220,7 @@ cpu33: cpu@33 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1256,7 +1256,7 @@ cpu34: cpu@34 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1292,7 +1292,7 @@ cpu35: cpu@35 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1328,7 +1328,7 @@ cpu36: cpu@36 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1364,7 +1364,7 @@ cpu37: cpu@37 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1400,7 +1400,7 @@ cpu38: cpu@38 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1436,7 +1436,7 @@ cpu39: cpu@39 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1472,7 +1472,7 @@ cpu40: cpu@40 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1508,7 +1508,7 @@ cpu41: cpu@41 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1544,7 +1544,7 @@ cpu42: cpu@42 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1580,7 +1580,7 @@ cpu43: cpu@43 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1616,7 +1616,7 @@ cpu44: cpu@44 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1652,7 +1652,7 @@ cpu45: cpu@45 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1688,7 +1688,7 @@ cpu46: cpu@46 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1724,7 +1724,7 @@ cpu47: cpu@47 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1760,7 +1760,7 @@ cpu48: cpu@48 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1796,7 +1796,7 @@ cpu49: cpu@49 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1832,7 +1832,7 @@ cpu50: cpu@50 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1868,7 +1868,7 @@ cpu51: cpu@51 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1904,7 +1904,7 @@ cpu52: cpu@52 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1940,7 +1940,7 @@ cpu53: cpu@53 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -1976,7 +1976,7 @@ cpu54: cpu@54 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2012,7 +2012,7 @@ cpu55: cpu@55 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2048,7 +2048,7 @@ cpu56: cpu@56 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2084,7 +2084,7 @@ cpu57: cpu@57 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2120,7 +2120,7 @@ cpu58: cpu@58 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2156,7 +2156,7 @@ cpu59: cpu@59 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2192,7 +2192,7 @@ cpu60: cpu@60 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2228,7 +2228,7 @@ cpu61: cpu@61 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2264,7 +2264,7 @@ cpu62: cpu@62 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", @@ -2300,7 +2300,7 @@ cpu63: cpu@63 { "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfbfmin", "zfh", "zfhmin", - "zicbom", "zicbop", "zicboz", + "zicbom", "zicbop", "zicboz", "ziccrse", "zicntr", "zicond","zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zvfbfmin", "zvfbfwma", "zvfh", From 3f859e838285f8b6c90239e5d5c19fa7ad4de8af Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 3 Jul 2025 08:38:43 +0800 Subject: [PATCH 23/32] riscv: dts: sophgo: sg2044: add pmu configuration Add PMU configuration for the cpu of sg2044, which is the V2 version of C920. Reviewed-by: Chen Wang Tested-by: Han Gao Link: https://lore.kernel.org/r/20250703003844.84617-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 91 +++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 0d71a167ed22..523799a1a8b8 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -2778,6 +2778,97 @@ l3_cache: cache-controller-16 { }; }; + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000010>, + <0x00004 0x00000000 0x00000011>, + <0x00005 0x00000000 0x00000007>, + <0x00006 0x00000000 0x00000006>, + <0x00008 0x00000000 0x00000027>, + <0x00009 0x00000000 0x00000028>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10008 0x00000000 0x00000001>, + <0x10009 0x00000000 0x00000002>, + <0x10010 0x00000000 0x00000010>, + <0x10011 0x00000000 0x00000011>, + <0x10012 0x00000000 0x00000012>, + <0x10013 0x00000000 0x00000013>, + <0x10019 0x00000000 0x00000004>, + <0x10021 0x00000000 0x00000003>, + <0x10030 0x00000000 0x0000001c>, + <0x10031 0x00000000 0x0000001b>; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0xfffffff8>, + <0x00004 0x00004 0xfffffff8>, + <0x00005 0x00005 0xfffffff8>, + <0x00006 0x00006 0xfffffff8>, + <0x00007 0x00007 0xfffffff8>, + <0x00008 0x00008 0xfffffff8>, + <0x00009 0x00009 0xfffffff8>, + <0x0000a 0x0000a 0xfffffff8>, + <0x10000 0x10000 0xfffffff8>, + <0x10001 0x10001 0xfffffff8>, + <0x10002 0x10002 0xfffffff8>, + <0x10003 0x10003 0xfffffff8>, + <0x10008 0x10008 0xfffffff8>, + <0x10009 0x10009 0xfffffff8>, + <0x10010 0x10010 0xfffffff8>, + <0x10011 0x10011 0xfffffff8>, + <0x10012 0x10012 0xfffffff8>, + <0x10013 0x10013 0xfffffff8>, + <0x10019 0x10019 0xfffffff8>, + <0x10021 0x10021 0xfffffff8>, + <0x10030 0x10030 0xfffffff8>, + <0x10031 0x10031 0xfffffff8>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>; + }; + soc { intc: interrupt-controller@6d40000000 { compatible = "sophgo,sg2044-plic", "thead,c900-plic"; From 109b3d7b888cf3685b06c19fa7241fb2da280db8 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 3 Jul 2025 10:15:56 +0800 Subject: [PATCH 24/32] riscv: dts: sophgo: Add ethernet device for cv18xx Add ethernet controller device node for cv18xx SoC. Link: https://lore.kernel.org/r/20250703021600.125550-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 9a25b8c6c2f3..9e4559538cbc 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -189,6 +189,50 @@ i2c4: i2c@4040000 { status = "disabled"; }; + gmac0: ethernet@4070000 { + compatible = "sophgo,cv1800b-dwmac", "snps,dwmac-3.70a"; + reg = <0x04070000 0x10000>; + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; + clock-names = "stmmaceth", "ptp_ref"; + interrupts = ; + interrupt-names = "macirq"; + resets = <&rst RST_ETH0>; + reset-names = "stmmaceth"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + snps,aal; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + status = "disabled"; + + gmac0_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <16 8 4 0 0 0 0>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <1>; + }; + }; + uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; From ba1abacc57cb7c1bdc249d3d61ec75fbe3e598f2 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 3 Jul 2025 10:15:57 +0800 Subject: [PATCH 25/32] riscv: dts: sophgo: Add mdio multiplexer device for cv18xx Add DT device node of mdio multiplexer device for cv18xx SoC. Link: https://lore.kernel.org/r/20250703021600.125550-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 9e4559538cbc..56eb74c4a89e 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -31,6 +31,33 @@ rst: reset-controller@3003000 { #reset-cells = <1>; }; + mdio: mdio@3009800 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + reg = <0x3009800 0x4>; + #address-cells = <1>; + #size-cells = <0>; + mdio-parent-bus = <&gmac0_mdio>; + mux-mask = <0x80>; + status = "disabled"; + + internal_mdio: mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + internal_ephy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; + + external_mdio: mdio@80 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x80>; + }; + }; + gpio0: gpio@3020000 { compatible = "snps,dw-apb-gpio"; reg = <0x3020000 0x1000>; @@ -196,6 +223,8 @@ gmac0: ethernet@4070000 { clock-names = "stmmaceth", "ptp_ref"; interrupts = ; interrupt-names = "macirq"; + phy-handle = <&internal_ephy>; + phy-mode = "internal"; resets = <&rst RST_ETH0>; reset-names = "stmmaceth"; rx-fifo-depth = <8192>; From a9b547cefb0f4d8730cd66d92ba76dae723fae51 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 3 Jul 2025 10:15:58 +0800 Subject: [PATCH 26/32] riscv: dts: sophgo: Enable ethernet device for Huashan Pi Enable ethernet controller and mdio multiplexer device on Huashan Pi. Link: https://lore.kernel.org/r/20250703021600.125550-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts index 26b57e15adc1..4a5835fa9e96 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts @@ -55,6 +55,14 @@ &emmc { non-removable; }; +&gmac0 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + &sdhci0 { status = "okay"; bus-width = <4>; From 39539df543650dbaa570646e90f526fb55f79699 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 8 Jul 2025 14:46:25 +0800 Subject: [PATCH 27/32] riscv: dts: sophgo: add ethernet GMAC device for sg2042 Add ethernet GMAC device node for the sg2042. Tested-by: Han Gao Link: https://lore.kernel.org/r/20250708064627.509363-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 85636d1798f1..b3e4d3c18fdc 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -569,6 +569,67 @@ spi1: spi@7040005000 { status = "disabled"; }; + gmac0: ethernet@7040026000 { + compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a"; + reg = <0x70 0x40026000 0x0 0x4000>; + clocks = <&clkgen GATE_CLK_AXI_ETH0>, + <&clkgen GATE_CLK_PTP_REF_I_ETH0>, + <&clkgen GATE_CLK_TX_ETH0>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + dma-noncoherent; + interrupt-parent = <&intc>; + interrupts = <132 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&rstgen RST_ETH0>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + snps,aal; + snps,tso; + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <16 8 4 0 0 0 0>; + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <2>; + }; + }; + emmc: mmc@704002a000 { compatible = "sophgo,sg2042-dwcmshc"; reg = <0x70 0x4002a000 0x0 0x1000>; From e8dd24de123472595c9b5fe6258599d8290d75ce Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 5 Jul 2025 15:39:54 +0800 Subject: [PATCH 28/32] dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings Add DT binding documentation for the Sophgo SG2042_EVB_V1.X/V2.0 board [1]. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1] Acked-by: Conor Dooley Signed-off-by: Han Gao Reviewed-by: Nutty Liu Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/204c8214aa084d592e8dc45d6c5ca23381937b54.1751700954.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml index 602c092b4ad5..1c502618de51 100644 --- a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml @@ -39,6 +39,8 @@ properties: - items: - enum: - milkv,pioneer + - sophgo,sg2042-evb-v1 + - sophgo,sg2042-evb-v2 - const: sophgo,sg2042 - items: - enum: From 100513b2e54ab9f889c64e5bf13fca566a8e70ba Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 5 Jul 2025 15:39:55 +0800 Subject: [PATCH 29/32] riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree Sophgo SG2042_EVB_V1.X [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1] Signed-off-by: Han Gao Reviewed-by: Nutty Liu Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/27091134ce1f8a6541a349afc324d6f7402ea606.1751700954.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/Makefile | 1 + arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 245 +++++++++++++++++++ 2 files changed, 246 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 85966306801e..6c9b29681cad 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts new file mode 100644 index 000000000000..3320bc1dd2c6 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +#include +#include + +/ { + model = "Sophgo SG2042 EVB V1.X"; + compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042"; + + chosen { + stdout-path = "serial0"; + }; + + gpio-power { + compatible = "gpio-keys"; + + key-power { + label = "Power Key"; + linux,code = ; + gpios = <&port0a 22 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + debounce-interval = <100>; + }; + }; + + pwmfan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <103 128 179 230 255>; + pwms = <&pwm 0 40000 0>; + #cooling-cells = <2>; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 0>; + + trips { + soc_active1: soc-active1 { + temperature = <30000>; + hysteresis = <8000>; + type = "active"; + }; + + soc_active2: soc-active2 { + temperature = <58000>; + hysteresis = <12000>; + type = "active"; + }; + + soc_active3: soc-active3 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + + soc_hot: soc-hot { + temperature = <80000>; + hysteresis = <5000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_active1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_active2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_active3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_hot>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + + board-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 1>; + + trips { + board_active: board-active { + temperature = <75000>; + hysteresis = <8000>; + type = "active"; + }; + }; + + cooling-maps { + map4 { + trip = <&board_active>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + }; +}; + +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + +&emmc { + pinctrl-0 = <&emmc_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_cfg>; + pinctrl-names = "default"; + status = "okay"; + + mcu: syscon@17 { + compatible = "sophgo,sg2042-hwmon-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; +}; + +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&pinctrl { + emmc_cfg: sdhci-emmc-cfg { + sdhci-emmc-wp-pins { + pinmux = ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + + sdhci-emmc-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-emmc-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + + sd_cfg: sdhci-sd-cfg { + sdhci-sd-cd-wp-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-sd-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-rx-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; +}; + +&sd { + pinctrl-0 = <&sd_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-mmc; + wp-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; From 6ea2a06165e7c613e2efb9927c3537f76ccdfc1a Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 5 Jul 2025 15:39:56 +0800 Subject: [PATCH 30/32] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1] Signed-off-by: Han Gao Reviewed-by: Nutty Liu Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/c1b6ccdc69af0c1457fc1486a6bc8a1e83671537.1751700954.git.rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/Makefile | 1 + arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 233 +++++++++++++++++++ 2 files changed, 234 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 6c9b29681cad..6f65526d4193 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts new file mode 100644 index 000000000000..46980e41b886 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +#include +#include + +/ { + model = "Sophgo SG2042 EVB V2.0"; + compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042"; + + chosen { + stdout-path = "serial0"; + }; + + pwmfan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <103 128 179 230 255>; + pwms = <&pwm 0 40000 0>; + #cooling-cells = <2>; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 0>; + + trips { + soc_active1: soc-active1 { + temperature = <30000>; + hysteresis = <8000>; + type = "active"; + }; + + soc_active2: soc-active2 { + temperature = <58000>; + hysteresis = <12000>; + type = "active"; + }; + + soc_active3: soc-active3 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + + soc_hot: soc-hot { + temperature = <80000>; + hysteresis = <5000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_active1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_active2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_active3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_hot>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + + board-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 1>; + + trips { + board_active: board-active { + temperature = <75000>; + hysteresis = <8000>; + type = "active"; + }; + }; + + cooling-maps { + map4 { + trip = <&board_active>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + }; +}; + +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + +&emmc { + pinctrl-0 = <&emmc_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_cfg>; + pinctrl-names = "default"; + status = "okay"; + + mcu: syscon@17 { + compatible = "sophgo,sg2042-hwmon-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; +}; + +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&pinctrl { + emmc_cfg: sdhci-emmc-cfg { + sdhci-emmc-wp-pins { + pinmux = ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + + sdhci-emmc-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-emmc-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + + sd_cfg: sdhci-sd-cfg { + sdhci-sd-cd-wp-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-sd-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-rx-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; +}; + +&sd { + pinctrl-0 = <&sd_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-mmc; + wp-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; From 46683af1fb70d891d89cb9221b25b92f6b1d5193 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Thu, 3 Jul 2025 08:40:23 +0800 Subject: [PATCH 31/32] riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device As the uart0 is already occupied by the firmware, reserve it to avoid this port is used by mistake. Tested-by: Han Gao Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250703004024.85221-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts index 1ca5fb707061..fed3d9a384a0 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts +++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts @@ -109,6 +109,11 @@ &sd { status = "okay"; }; +&uart0 { + /* for firmware */ + status = "reserved"; +}; + &uart1 { status = "okay"; }; From 7f90573099e8a506a6874d691d884d7f5b77ec74 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 16 Jul 2025 06:13:48 +0800 Subject: [PATCH 32/32] riscv: dts: sophgo: fix mdio node name for CV180X As the mdio multipledxer is marked as mdio device, the check complains the mdio bus number exceed the maximum. Change the node name to mdio-mux to remove the following warnings: mdio@3009800 (mdio-mux-mmioreg): mdio@80:reg:0:0: 128 is greater than the maximum of 31 Fixes: b7945143bc33 ("riscv: dts: sophgo: Add mdio multiplexer device for cv18xx") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202507140738.XRjv3G8i-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202507121830.POx2KDVi-lkp@intel.com/ Reviewed-by: Alexander Sverdlin Link: https://lore.kernel.org/r/20250715221349.11034-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 56eb74c4a89e..ccdb45498653 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -31,7 +31,7 @@ rst: reset-controller@3003000 { #reset-cells = <1>; }; - mdio: mdio@3009800 { + mdio: mdio-mux@3009800 { compatible = "mdio-mux-mmioreg", "mdio-mux"; reg = <0x3009800 0x4>; #address-cells = <1>;