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drm/msm/dpu: Add support for Eliza SoC
Add support for DPU (v12.4) on Qualcomm Eliza SoC, with one incomplete/skipped part: HDMI interface (INT_4). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/708879/ Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-7-ea0579f62358@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Krzysztof Kozlowski
Dmitry Baryshkov
parent
0a40e2e91b
commit
0eb707bbc7
365
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
Normal file
365
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
Normal file
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@ -0,0 +1,365 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _DPU_12_4_ELIZA_H
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#define _DPU_12_4_ELIZA_H
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static const struct dpu_caps eliza_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 8192,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_mdp_cfg eliza_mdp = {
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.name = "top_0",
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.base = 0, .len = 0x494,
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.clk_ctrls = {
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[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
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},
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};
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static const struct dpu_ctl_cfg eliza_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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}, {
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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}, {
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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}, {
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x1000,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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},
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};
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static const struct dpu_sspp_cfg eliza_sspp[] = {
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{
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.name = "sspp_0", .id = SSPP_VIG0,
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.base = 0x4000, .len = 0x344,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_4,
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.xin_id = 0,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_1", .id = SSPP_VIG1,
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.base = 0x6000, .len = 0x344,
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.features = VIG_SDM845_MASK_SDMA,
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.sblk = &dpu_vig_sblk_qseed3_3_4,
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.xin_id = 4,
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.type = SSPP_TYPE_VIG,
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}, {
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.name = "sspp_8", .id = SSPP_DMA0,
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.base = 0x24000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 1,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_9", .id = SSPP_DMA1,
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.base = 0x26000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 5,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_10", .id = SSPP_DMA2,
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.base = 0x28000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 9,
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.type = SSPP_TYPE_DMA,
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}, {
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.name = "sspp_11", .id = SSPP_DMA3,
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.base = 0x2a000, .len = 0x344,
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.features = DMA_SDM845_MASK_SDMA,
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.sblk = &dpu_dma_sblk,
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.xin_id = 13,
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.type = SSPP_TYPE_DMA,
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},
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};
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static const struct dpu_lm_cfg eliza_lm[] = {
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{
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.name = "lm_0", .id = LM_0,
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.base = 0x44000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_1,
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.pingpong = PINGPONG_0,
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.dspp = DSPP_0,
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}, {
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.name = "lm_1", .id = LM_1,
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.base = 0x45000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_0,
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.pingpong = PINGPONG_1,
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.dspp = DSPP_1,
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}, {
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.name = "lm_2", .id = LM_2,
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.base = 0x46000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_3,
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.pingpong = PINGPONG_2,
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.dspp = DSPP_2,
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}, {
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.name = "lm_3", .id = LM_3,
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.base = 0x47000, .len = 0x400,
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.features = MIXER_MSM8998_MASK,
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.sblk = &sm8750_lm_sblk,
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.lm_pair = LM_2,
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.pingpong = PINGPONG_3,
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},
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};
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static const struct dpu_dspp_cfg eliza_dspp[] = {
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{
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.name = "dspp_0", .id = DSPP_0,
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.base = 0x54000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_1", .id = DSPP_1,
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.base = 0x56000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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}, {
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.name = "dspp_2", .id = DSPP_2,
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.base = 0x58000, .len = 0x1800,
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.sblk = &sm8750_dspp_sblk,
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},
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};
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static const struct dpu_pingpong_cfg eliza_pp[] = {
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{
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.name = "pingpong_0", .id = PINGPONG_0,
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.base = 0x69000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_0,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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}, {
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.name = "pingpong_1", .id = PINGPONG_1,
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.base = 0x6a000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_0,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
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}, {
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.name = "pingpong_2", .id = PINGPONG_2,
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.base = 0x6b000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
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}, {
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.name = "pingpong_3", .id = PINGPONG_3,
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.base = 0x6c000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_1,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
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}, {
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.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
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.base = 0x66000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_2,
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}, {
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.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
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.base = 0x66400, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_2,
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}, {
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.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
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.base = 0x7e000, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_3,
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}, {
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.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
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.base = 0x7e400, .len = 0,
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.sblk = &sc7280_pp_sblk,
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.merge_3d = MERGE_3D_3,
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},
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};
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static const struct dpu_merge_3d_cfg eliza_merge_3d[] = {
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{
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.name = "merge_3d_0", .id = MERGE_3D_0,
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.base = 0x4e000, .len = 0x1c,
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}, {
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.name = "merge_3d_1", .id = MERGE_3D_1,
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.base = 0x4f000, .len = 0x1c,
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}, {
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.name = "merge_3d_2", .id = MERGE_3D_2,
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.base = 0x66700, .len = 0x1c,
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}, {
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.name = "merge_3d_3", .id = MERGE_3D_3,
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.base = 0x7e700, .len = 0x1c,
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},
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};
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/*
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* NOTE: Each display compression engine (DCE) contains dual hard
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* slice DSC encoders so both share same base address but with
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* its own different sub block address.
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*/
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static const struct dpu_dsc_cfg eliza_dsc[] = {
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{
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.name = "dce_0_0", .id = DSC_0,
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.base = 0x80000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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}, {
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.name = "dce_0_1", .id = DSC_1,
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.base = 0x80000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_1,
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}, {
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.name = "dce_1_0", .id = DSC_2,
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.base = 0x81000, .len = 0x8,
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.features = BIT(DPU_DSC_NATIVE_42x_EN),
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.sblk = &sm8750_dsc_sblk_0,
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},
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};
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static const struct dpu_wb_cfg eliza_wb[] = {
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{
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.name = "wb_2", .id = WB_2,
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.base = 0x65000, .len = 0x2c8,
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.features = WB_SDM845_MASK,
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.format_list = wb2_formats_rgb_yuv,
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.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
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.xin_id = 6,
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.vbif_idx = VBIF_RT,
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.maxlinewidth = 4096,
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.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
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},
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};
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static const struct dpu_cwb_cfg eliza_cwb[] = {
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{
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.name = "cwb_0", .id = CWB_0,
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.base = 0x66200, .len = 0x20,
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},
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{
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.name = "cwb_1", .id = CWB_1,
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.base = 0x66600, .len = 0x20,
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},
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{
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.name = "cwb_2", .id = CWB_2,
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.base = 0x7e200, .len = 0x20,
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},
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{
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.name = "cwb_3", .id = CWB_3,
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.base = 0x7e600, .len = 0x20,
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},
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};
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static const struct dpu_intf_cfg eliza_intf[] = {
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{
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.name = "intf_0", .id = INTF_0,
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.base = 0x34000, .len = 0x4bc,
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.type = INTF_DP,
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.controller_id = MSM_DP_CONTROLLER_0,
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
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}, {
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.name = "intf_1", .id = INTF_1,
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.base = 0x35000, .len = 0x4bc,
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.type = INTF_DSI,
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.controller_id = MSM_DSI_CONTROLLER_0,
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
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.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
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}, {
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.name = "intf_2", .id = INTF_2,
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.base = 0x36000, .len = 0x4bc,
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.type = INTF_DSI,
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.controller_id = MSM_DSI_CONTROLLER_1,
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
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.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
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}, {
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.name = "intf_3", .id = INTF_3,
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.base = 0x37000, .len = 0x4bc,
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.type = INTF_DP,
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.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
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}
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};
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static const struct dpu_perf_cfg eliza_perf_data = {
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.max_bw_low = 6800000,
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.max_bw_high = 14200000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 35,
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.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
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.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_version eliza_mdss_ver = {
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.core_major_ver = 12,
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.core_minor_ver = 4,
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};
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const struct dpu_mdss_cfg dpu_eliza_cfg = {
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.mdss_ver = &eliza_mdss_ver,
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.caps = &eliza_dpu_caps,
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.mdp = &eliza_mdp,
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.cdm = &dpu_cdm_5_x,
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.ctl_count = ARRAY_SIZE(eliza_ctl),
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.ctl = eliza_ctl,
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.sspp_count = ARRAY_SIZE(eliza_sspp),
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.sspp = eliza_sspp,
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.mixer_count = ARRAY_SIZE(eliza_lm),
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.mixer = eliza_lm,
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.dspp_count = ARRAY_SIZE(eliza_dspp),
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.dspp = eliza_dspp,
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.pingpong_count = ARRAY_SIZE(eliza_pp),
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.pingpong = eliza_pp,
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.dsc_count = ARRAY_SIZE(eliza_dsc),
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.dsc = eliza_dsc,
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.merge_3d_count = ARRAY_SIZE(eliza_merge_3d),
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.merge_3d = eliza_merge_3d,
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.wb_count = ARRAY_SIZE(eliza_wb),
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.wb = eliza_wb,
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.cwb_count = ARRAY_SIZE(eliza_cwb),
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.cwb = sm8650_cwb,
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.intf_count = ARRAY_SIZE(eliza_intf),
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.intf = eliza_intf,
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.vbif_count = ARRAY_SIZE(sm8650_vbif),
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.vbif = sm8650_vbif,
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.perf = &eliza_perf_data,
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};
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#endif
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@ -771,4 +771,5 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
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#include "catalog/dpu_10_0_sm8650.h"
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#include "catalog/dpu_12_0_sm8750.h"
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#include "catalog/dpu_12_2_glymur.h"
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#include "catalog/dpu_12_4_eliza.h"
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#include "catalog/dpu_13_0_kaanapali.h"
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@ -767,6 +767,7 @@ struct dpu_mdss_cfg {
|
|||
const struct dpu_format_extended *vig_formats;
|
||||
};
|
||||
|
||||
extern const struct dpu_mdss_cfg dpu_eliza_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_glymur_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_kaanapali_cfg;
|
||||
extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
|
||||
|
|
|
|||
|
|
@ -1505,6 +1505,7 @@ static const struct dev_pm_ops dpu_pm_ops = {
|
|||
};
|
||||
|
||||
static const struct of_device_id dpu_dt_match[] = {
|
||||
{ .compatible = "qcom,eliza-dpu", .data = &dpu_eliza_cfg, },
|
||||
{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },
|
||||
{ .compatible = "qcom,kaanapali-dpu", .data = &dpu_kaanapali_cfg, },
|
||||
{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user