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dt-bindings: display/msm: qcom,eliza-mdss: Add Eliza SoC
Add MDSS/MDP display subsystem for Qualcomm Eliza SoC, being overall a minor revision change against SM8750, but coming with few different components, like different DSI PHY, missing DP1 and added HDMI. The binding does not include HDMI description yet. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/708878/ Link: https://lore.kernel.org/r/20260304-drm-display-eliza-v2-5-ea0579f62358@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Krzysztof Kozlowski
Dmitry Baryshkov
parent
df76187341
commit
0a40e2e91b
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@ -0,0 +1,494 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,eliza-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Eliza SoC Display MDSS
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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description:
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Eliza SoC Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU
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display controller, DSI and DP interfaces etc.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,eliza-mdss
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clocks:
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items:
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- description: Display AHB
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- description: Display hf AXI
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- description: Display core
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iommus:
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maxItems: 1
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interconnects:
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items:
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- description: Interconnect path from mdp0 port to the data bus
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- description: Interconnect path from CPU to the reg bus
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interconnect-names:
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items:
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- const: mdp0-mem
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- const: cpu-cfg
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,eliza-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,eliza-dp
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,eliza-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,eliza-dsi-phy-4nm
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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display-subsystem@ae00000 {
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compatible = "qcom,eliza-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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ranges;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&disp_cc_mdss_ahb_clk>,
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<&gcc_disp_hf_axi_clk>,
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<&disp_cc_mdss_mdp_clk>;
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resets = <&disp_cc_mdss_core_bcr>;
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interconnects = <&mmss_noc_master_mdp QCOM_ICC_TAG_ALWAYS
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&mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc_slave_display_cfg QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "mdp0-mem",
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"cpu-cfg";
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power-domains = <&mdss_gdsc>;
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iommus = <&apps_smmu 0x800 0x2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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mdss_mdp: display-controller@ae01000 {
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compatible = "qcom,eliza-dpu";
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reg = <0x0ae01000 0x93000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp",
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"vbif";
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interrupts-extended = <&mdss 0>;
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clocks = <&gcc_disp_hf_axi_clk>,
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<&disp_cc_mdss_ahb_clk>,
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<&disp_cc_mdss_mdp_lut_clk>,
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<&disp_cc_mdss_mdp_clk>,
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<&disp_cc_mdss_vsync_clk>;
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clock-names = "nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&disp_cc_mdss_vsync_clk>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&mdss_dsi1_in>;
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};
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};
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port@2 {
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reg = <2>;
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dpu_intf0_out: endpoint {
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remote-endpoint = <&mdss_dp0_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-150000000 {
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opp-hz = /bits/ 64 <150000000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-207000000 {
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opp-hz = /bits/ 64 <207000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-342000000 {
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opp-hz = /bits/ 64 <342000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-417000000 {
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opp-hz = /bits/ 64 <417000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-532000000 {
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opp-hz = /bits/ 64 <532000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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required-opps = <&rpmhpd_opp_nom_l1>;
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};
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opp-660000000 {
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opp-hz = /bits/ 64 <660000000>;
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required-opps = <&rpmhpd_opp_turbo>;
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupts-extended = <&mdss 4>;
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clocks = <&disp_cc_mdss_byte0_clk>,
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<&disp_cc_mdss_byte0_intf_clk>,
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<&disp_cc_mdss_pclk0_clk>,
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<&disp_cc_mdss_esc0_clk>,
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<&disp_cc_mdss_ahb_clk>,
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<&gcc_disp_hf_axi_clk>,
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<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
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<&disp_cc_esync0_clk>,
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<&disp_cc_osc_clk>,
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<&disp_cc_mdss_byte0_clk_src>,
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<&disp_cc_mdss_pclk0_clk_src>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus",
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"dsi_pll_pixel",
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"dsi_pll_byte",
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"esync",
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"osc",
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"byte_src",
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"pixel_src";
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operating-points-v2 = <&mdss_dsi_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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remote-endpoint = <&panel0_in>;
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data-lanes = <0 1 2 3>;
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};
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};
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};
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mdss_dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-140630000 {
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opp-hz = /bits/ 64 <140630000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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mdss_dsi0_phy: phy@ae95000 {
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compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
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reg = <0x0ae95000 0x200>,
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<0x0ae95200 0x280>,
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<0x0ae95500 0x400>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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clocks = <&disp_cc_mdss_ahb_clk>,
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<&bi_tcxo_div2>;
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clock-names = "iface",
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"ref";
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#clock-cells = <1>;
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#phy-cells = <0>;
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vdds-supply = <&vreg_l2b>;
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};
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dsi@ae96000 {
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compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0ae96000 0x400>;
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reg-names = "dsi_ctrl";
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interrupts-extended = <&mdss 5>;
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clocks = <&disp_cc_mdss_byte1_clk>,
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<&disp_cc_mdss_byte1_intf_clk>,
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<&disp_cc_mdss_pclk1_clk>,
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<&disp_cc_mdss_esc1_clk>,
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<&disp_cc_mdss_ahb_clk>,
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<&gcc_disp_hf_axi_clk>,
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<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
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<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
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<&disp_cc_esync1_clk>,
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<&disp_cc_osc_clk>,
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<&disp_cc_mdss_byte1_clk_src>,
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<&disp_cc_mdss_pclk1_clk_src>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus",
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"dsi_pll_pixel",
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"dsi_pll_byte",
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"esync",
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"osc",
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"byte_src",
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"pixel_src";
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operating-points-v2 = <&mdss_dsi_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dsi1_phy>;
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phy-names = "dsi";
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vdda-supply = <&vreg_l4b>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi1_out: endpoint {
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remote-endpoint = <&panel1_in>;
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data-lanes = <0 1 2 3>;
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};
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};
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};
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};
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mdss_dsi1_phy: phy@ae97000 {
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compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
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reg = <0x0ae97000 0x200>,
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<0x0ae97200 0x280>,
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<0x0ae97500 0x400>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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clocks = <&disp_cc_mdss_ahb_clk>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface",
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"ref";
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#clock-cells = <1>;
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#phy-cells = <0>;
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vdds-supply = <&vreg_l2b>;
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};
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displayport-controller@af54000 {
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compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
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reg = <0xaf54000 0x104>,
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<0xaf54200 0xc0>,
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<0xaf55000 0x770>,
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<0xaf56000 0x9c>,
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<0xaf57000 0x9c>;
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interrupts-extended = <&mdss 12>;
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clocks = <&disp_cc_mdss_ahb_clk>,
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<&disp_cc_mdss_dptx0_aux_clk>,
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<&disp_cc_mdss_dptx0_link_clk>,
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<&disp_cc_mdss_dptx0_link_intf_clk>,
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<&disp_cc_mdss_dptx0_pixel0_clk>,
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<&disp_cc_mdss_dptx0_pixel1_clk>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
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<&disp_cc_mdss_dptx0_pixel0_clk_src>,
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<&disp_cc_mdss_dptx0_pixel1_clk_src>;
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assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
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<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
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operating-points-v2 = <&dp_opp_table>;
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||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
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||||
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phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
|
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phy-names = "dp";
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||||
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||||
#sound-dai-cells = <0>;
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||||
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||||
dp_opp_table: opp-table {
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||||
compatible = "operating-points-v2";
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||||
|
||||
opp-192000000 {
|
||||
opp-hz = /bits/ 64 <192000000>;
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||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
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||||
};
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||||
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||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
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||||
};
|
||||
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||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
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||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mdss_dp0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dp0_out: endpoint {
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user